an implementation of morphological binary image processing ... · target for the implementation of...

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www.ijifr.com Copyright © IJIFR 2015

Reviewed Paper

International Journal of Informative & Futuristic Research ISSN (Online): 2347-1697

Volume 2 Issue 11 July 2015

Abstract

Field Programmable Gate Array (FPGA) technology has become a viable target for the implementation of real time algorithms suited to video image processing applications. A MATLAB graphical user interface allows the designer to open the image to be processed, setup the communication parameters, specify the required processing, send the input image, and receive the corresponding result after the process. This could be processed in real time. We can implement existing system for simplified computation method on a MRI image for tumor detection is detailed above using morphological filtering on a binary image which is extracted from the input image & also we can implement for In this work a moving object motion detection system based on background subtraction algorithm was developed.

1. Introduction Binary Images: A very important characteristic of a binary image is the distance transform. This

gives the distance of every set pixel from the nearest unset pixel. The distance transform can be

efficiently calculated. It allows efficient computation of Voronoi diagrams, where each pixel in an

image is assigned to the nearest of a set of points. It also allows skeletonization, which differs from

thinning in that skeletons allow recovery of the original image. Typically the two colors used for a

binary image are black and white though any two colors can be used. The color used for the objects

An Implementation of Morphological

Binary Image Processing Using FPGA

Paper ID IJIFR/ V2/ E11/ 033 Page No. 4164-4171 Subject Area Electronic & Tele

Comm. Engg.

Key Words Morphological Image, MRI, Matlab, FPGA

Received On 13-07-2015 Accepted On 21-07-2015 Published On 25-07-2015

R.V. Dharmadhikari 1 ME Student, Department of Electronic & Tele Communication Engg. Parvara Rural Engineering College, Loni

Prof. S.A. Shaikh 2 Associate Professor , Department of Electronic & Tele Communication Engg. Parvara Rural Engineering College, Loni

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ISSN (Online): 2347-1697 International Journal of Informative & Futuristic Research (IJIFR)

Volume - 2, Issue - 11, July 2015 23rdEdition, Page No: 4164-4171

R.V. Dharmadhikari , Prof. S.A. Shaikh .:: An Implementation of Morphological Binary Image Processing Using FPGA

in the image is the foreground color while the rest of the image is the background color. In the

document-scanning industry this is often referred to as "bi-tonal". Binary images are also called bi-

level or two-level. A binary image is a digital image that has only two possible values for

each pixel. That means that each pixel is stored as a single bit i.e., a 0 or 1.

The names black-and white, B&W, monochrome or monochromatic are often used for this concept,

but may also designate any images that have only one sample per pixel, such as gray scale images.

In Photoshop parlance, a binary image is the same as an image in "Bitmap" mode. Binary images

often arise in digital image processing as masks or as the result of certain operations such

as segmentation, threshold, and dithering. Some input/output devices, such as laser printers, fax

machines, and bi-level computer displays, can only handle bi-level images. A binary image can be

stored in memory as a bitmap, a packed array of bits. A 640×480 image requires 37.5 KB of

storage. Because of the small size of the image files, fax machine and document management

solutions usually use this format. Most binary images also compress well with simple run-length

compression schemes. Binary images can be interpreted as subsets of the two-dimensional integer

lattice Z2; the field of morphological image processing was largely inspired by this view.

Field-programmable Gate Array (FPGA)

FPGA is an integrated circuit designed to be configured by the customer or designer after

manufacturing hence "field-programmable". The FPGA configuration is generally specified using a

hardware description language (HDL), similar to that used for an application-specific integrated

circuit (ASIC) (circuit diagrams were previously used to specify the configuration, as they were for

ASICs, but this is increasingly rare). FPGAs can be used to implement any logical function that an

ASIC could perform. The ability to update the functionality after shipping, partial re-configuration

of the portion of the design and the low non-recurring engineering costs relative to an ASIC design

(notwithstanding the generally higher unit cost), offer advantages for many applications. FPGAs

contain programmable logic components called "logic blocks", and a hierarchy of reconfigurable

interconnects that allow the blocks to be "wired together" somewhat like many (changeable) logic

gates that can be inter-wired in (many) different configurations. Logic blocks can be configured to

perform complex combinational functions, or merely simple logic gates like AND and XOR. In

most FPGAs, the logic blocks also include memory elements, which may be simple flip-flops or

more complete blocks of memory. In addition to digital functions, some FPGAs have analog

features. The most common analog feature is programmable slew rate and drive strength on each

output pin, allowing the engineer to set slow rates on lightly loaded pins that would otherwise

unacceptably, and to set stronger, faster rates on heavily loaded pins on high-speed channels that

would otherwise run too slow. Another relatively common analog feature is differential

comparators on input pins designed to be connected to differential signaling channels. A few

"mixed signal FPGAs" have integrated peripheral Analog-to-Digital Converters (ADCs) and

Digital-to-Analog Converters (DACs) with analog signal conditioning blocks allowing them to

operate as a system-on-a-chip. Such devices blur the line between an FPGA, which carries digital

ones and zeros on its internal programmable interconnect fabric, and field-programmable analog

array (FPAA), which carries analog values on its internal programmable interconnect fabric.

2. Motivation

A Field-programmable Gate Array (FPGA) is an integrated circuit designed to be configured by the

customer or designer after manufacturing—hence "field-programmable". The FPGA configuration

is generally specified using a hardware description language (HDL), similar to that used for an

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application-specific integrated circuit (ASIC) (circuit diagrams were previously used to specify the

configuration, as they were for ASICs, but this is increasingly rare). FPGAs can be used to

implement any logical function that an ASIC could perform. The ability to update the functionality

after shipping, partial re-configuration of the portion of the design and the low non-recurring

engineering costs relative to an ASIC design (notwithstanding the generally higher unit cost), offer

advantages for many applications.

3. Literature Survey

Design and Implementation of a Fuzzy Hardware Structure for Morphological Color Image

Processing by G. Louverdis et.al. include A new design of a fuzzy processor, which is capable of

performing the morphological operations of standard and soft erosion/dilation of 24-bit color

images for a 3*3-pixel neighborhood is presented in this paper. Architecture of the processor

consists of five basic functional pipelined stages, in which several inference processing phases are

performed in parallel, in order to improve computational times .Speed for a fuzzy system designed

to perform morphological operations for color images. The system is suitable for real-time

applications where fast processing is required.

Spatially Variant Morphological Restoration and Skeleton Representation by Nidhal Bouaynaya

et.al proposed the presented general theory of Spatially Variant mathematical morphology and

showed its enormous potential through two important image processing applications. First, we

introduced Spatially Variant alternating sequential filters and Spatially Variant median filters for

Spatially Variant morphological denoising of degraded images. Simulation results demonstrated

that, not only is the noise removal capability of the Spatially Variant morphological filters

dramatically higher than their translation-invariant counterparts.

Optimized Morphological Operation Using Binary Image Processing by L.Arun et.al. contain the

dynamic reconfiguration approach was used to increase the processor performance. Basic

mathematical morphology operations and complicated algorithms can easily be implemented on it

because of its simple structure and it is verified. The processor, featured by high speed, simple

structure, and wide application range, is suitable for binary image processing, such as object

recognition, object tracking and motion detection, computer vision, identification, and

authentication.

FPGA Implementation of Reconfigurable Processor to Perform Multiple Operations of Binary

Image Processing, Vijay.A et.al. studied A reconfigurable binary image processor is proposed to

perform multiple operations of binary image processing. The processor consists of a reconfigurable

binary processing module and multiplexer circuits. The reconfigurable binary processing module

architecture with the characteristics of high efficiency, performance. Basic morphology operation

and complicated algorithms can easily be implemented on it because of its simple structure.

4. Project Functioning

i. Read the input image in MATLAB.

ii. Apply morphological algorithm to the input image

iii. Perform erosion on the image

iv. Perform dilation on image

v. Opening and closing of the image

vi. Apply sobel filter for image smoothing.

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vii. Generate Header file of image for VHDL simulation using MATLAB

viii. Import Header file in Xilinx Platform Studio (XPS)

ix. Debug Program in Xilinx Board (Spartan 3 EDK)

x. Run the Program using Xilinx Board (Spartan 3 EDK)

xi. Import the output file on PC show Output Image using Visual Basic Graphical User Interface

5. Typical Design Flow

Typical design flow for designing VLSI circuits is shown in the tool flow diagram. This design

flow is typically used by designers who use HDLs. In any design, specification is first.

Specification describes the functionality, interface and overall architecture of the digital circuit to

be designed. At this point, architects need not think about how they will implement their circuit. A

behavioral description is then created to analyze the design in terms of functionality, performances

and other high level issues. The behavioral description is manually converted to an RTL (Register

Transfer Level) description in an HDL. The designer has to describe the data flow that will

implement the desired digital circuit. From this point onward the design process is done with

assistance of CAD tools. Logic synthesis tools convert the RTL description to a gate level net list.

A gate level net list is a description of the circuit in terms of gates and connections between them.

The gate level net list is input to an automatic place and route tool, which creates a layout. The

layout is verified and then fabricated on a chip. Thus most digital design activity is concentrated on

manually optimizing the RTL description of the circuit. After the RTL description is frozen, CAD

tools are available to assist the designer in further process.

5. System Model

Block diagram

Figure 1: Block diagram of system model

JTAG: This JTAG header consists of 0.1-inch stake pins, located toward the top edge of

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the board, directly below the two expansion connectors. The low-cost parallel port to JTAG

cable fits directly over the header stake pins, as shown in Figure . When properly fitted, the

cable is perpendicular to the board. You must make sure that the signals at the end of the

JTAG cable align with the labels listed on the board. The other end of the cable connects to

the PC’s parallel port. The cable is directly compatible with the Xilinx impact software

FPGA:FPGA is an integrated circuit designed to be configured by the customer or designer

after manufacturing hence "field-programmable". The ability to update the functionality

after shipping, partial re-configuration of the portion of the design and the low non-

recurring engineering costs relative to an ASIC design (notwithstanding the generally

higher unit cost), offer advantages for many applications. FPGAs contain programmable

logic components called "logic blocks", and a hierarchy of reconfigurable interconnects that

allow the blocks to be "wired together" somewhat like many (changeable) logic gates that

can be inter-wired in (many) different configuration.

6. Implementation of Image Processing Algorithm

Detection Of Moving Object Based On Background Subtraction is implemented as Visual

surveillance has been a very active research topic in the last few years due to its growing

importance in security, law enforcement, and military applications. The making of video

surveillance systems smart requires fast and reliable algorithm for moving object detection.

In this work we propose the implementation of an efficient object detection algorithm that

can be employed in real time embedded systems due to its fast processing. This paper

proposes a new method to detect moving object based on background subtraction.

Morphological method is used for further processing to remove noise and to preserve the

shape of moving object. We compare our method with other modeling techniques and

report experimental results, both in terms of detection accuracy and in terms of processing

speed.

Reconfigurable Binary Image Processor for Brain Tumor Detection is implemented as

Nowadays medical field is looking forward for the sophisticated hardware and software

VLSI implementations. The next generation medical diagnosis requires fast and robust

dedicated hardware for precise applications, MRI images are commonly used for tumor

detection and complex hardware are necessary for its better computations .This rises the

necessity of dedicated hardware for improved performance. Binary images are optimal for

hardware implementation. We propose a novel method in which MRI images are

converted to binary images which allows the real time hardware implementation. VLSI

implementation using binary images effectively improves performance of the system in

terms of reduction in computational complexity, hardware requirements, reduces memory

space thus efficiently reduces cost.

I. Advantages

Any size of the image can be processed with any Pixel.

Binary image processing is used is state of the gray coding is used.

Support multiple image processing operations such as dilation, erosion, closing and

opening.

Output is better due to Edge detection of Sobel filter is used for Smoothening of Image.

Power Consumption of the board is 1.2V compared to 1.8V[2]

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II. Output of Project

Brain Tumor Detection

Figure 2: Output Images

II. Detection Of Moving Object Based On Background

Figure 2: Project output Snap Shot

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7. Result

Table 1: Comparision of Image Processors

Figure 4: Implementation

8. Conclusion In this Project, The Proposed reconfigurable binary image processor was studied to perform real-

time binary image processing. The processor performance has been increased by using the dynamic

reconfiguration approach. The most complicated algorithms and basic mathematical morphology

operations can be implemented easily on it because of its simple structure. The proposed processor,

were characterized by high speed, simple structure, and used for wide application range, which

suitable for binary image processing, like object recognition, object tracking and motion detection,

computer vision, identification, and authentication.We have Implemented existing system for

Simplified computation method on a MRI image for tumor detection is detailed above using

morphological filtering on a binary image which is extracted from the input image & our existing

system can also be used for In this work a moving object motion detection system based on

Sr.no Processor Base paper Results Result on this project

1. Process( ) 0.18 0.18

2. Area(mm2) 2.56 2.56

3. Area 180(mm2) 2.56 2.56

4. Image Pixels Any Size Any Size

5. Memory (bit) 40K 8 K

6. Image Processing Binary Binary

7. Speed(MHz) 220 50

8. Voltage (V) 1.8 1.2

9. Architecture 1-D MIMD Array Both 1D-MIMD 2-D MIMD Array

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background subtraction algorithm was developed.This were two applications which were developed

using existing system. Future Scope: Onboard Display can be Implemented which would reduce Processing Time

required due Transfer of Input Image File from PC to Xilinx Board (Spartan 3 EDK) using JTAG &

Output Image File from Xilinx Board (Spartan 3 EDK) to PC using RS 232

References

[1] G. Louverdis and I. Andreadis,―Design and Implementation of a Fuzzy Hardware Structure for

Morphological Color Image Processing,‖IEEE Transactions On Circuits And Systems For Video

Technology, Vol. 13, No. 3, March 2003.

[2] Bin Zhang, Kuizhi Mei, Member, IEEE, and Nanning Zheng, Fellow, IEEE, ―Reconfigurable

Processor for Binary,‖ ieee transactions on circuits and systems for video technology, vol. 23, no. 5, may

2013,pp.823-932.

[3] Petros maragos,―A Representation Theory for Morphological Image and Signal Processing,‖ IEEE

transactions on pattern analysis and machine intelligence. Vol ii. No. 6, june 1989,pp.586-600.

[4] J.-M. Daveau ang G. F. Marchioro, T. B. Ismail and A. A. Jerraya, ―Protocol selection and interface

generation for HW–SW codesign‖, IEEE Transactions on Very Large Scale Integration (VLSI) Systems,

Vol. 5, No. 1, pp 136–44, March 1997.

[5] D. F. Bacon, S. L. Graham and O. J. Sharp, ―Compiler Transformations for High- Performance

Computing‖, ACM Computing Surveys, Vol. 26, No. 4, pp 345–420, Dec 1994.

[6] Mr. Mahesh C. Pawaskar, Mr. N. S.Narkhede and Mr. Saurabh S. Athalye―Detection Of Moving

Object Based on Background Subtraction‖

International Journal of Emerging Trends & Technology in Computer Science (IJETTCS) SSN 2278-

6856 Volume 3, Issue 3 pp 215-218 May – June 2014.

[7] Sibin .P .A, D. Chidhambaram ―Reconfigurable Binary Image Processor for Brain Tumor Detection‖

International Journal of Science and Research (IJSR) ISSN (Online): 2319-7064 Index Copernicus Value

(2013): 6.14 pp 356-358 Impact Factor (2013): 4.438

[8] Basavarajeswari.B, Anitha.M, Prof.K.R.Kini, ―Design and Implementation of Morphological

Operations Using Reconfigurable Processor,‖ International Journal of Innovative Research in Computer

and Communication Engineering, Vol. 2, Issue 6, June 2014,pp-4767-4774.

[9] Mr . R.V. Dharmadhikari,& Prof. S.A. Shaikh―An overview of Morphological Binary Image

Processing Using FPGA‖ International Journal of Informative & Futuristic Research, July 2015. Index

Copernicus Value (2013): 6.62 pp 4073-4078, Impact Factor (2014): 4.164

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