AN-784APPLICATION NOTE

One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106 • Tel: 781/329-4700 • Fax: 781/461-3113 • www.analog.com

10-Bit Interface Board for High Performance Display Interface Evaluation Boardsby Del Jones

INTRODUCTIONThe purpose of the 10-bit display interface board (DIB) is to aid in the evaluation of the AD9981 or AD9980. It is designed to be used in conjunction with the evalua-tion boards for these parts, and is included as part of the evaluation board kits. It is a conduit for displaying images on any flat panel monitor, CRT, LCD (or DLP) projector, or TFT panel (with LVDS interface).

LIMITATIONSThe evaluation system using the 10-bit DIB is intended to provide the user a platform with which to evaluate the functionality and, to a limited extent, performance of the AD9981 or AD9980. When evaluating the 8-bit AD9980, the DVI or LVDS outputs of the 10-bit DIB offer the high-est quality image for performance evaluation. However, since both of these ports only offer 8-bit accuracy, they cannot truly reflect the enhanced performance provided by the 10-bit ADCs of the AD9981. The analog output of the 10-bit DIB uses high accuracy 12-bit DACs and can potentially offer a preferred interface for evaluation, depending on the display device that is used.

PACKAGE CONTENTS

• An evaluation board for the AD9981 or AD9980

• A 5 V dc power supply

• A Centronix printer cable or USB A to B cable for serial bus programming

REQUIREMENTSIn addition to the items included with the kit, the follow-ing items are needed to run this board:

• A computer with the evaluation software installed

• A 5 V dc power supply

• Any flat panel monitor, CRT, or projector 10-bit display interface board

Figure 1. Board Shown in Centimeters

05441-001

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EVALUATION BOARD HARDWARE

POWER This board is designed to receive 5 V dc through connec-tor J4. The power supply that is included in the kit plugs into this connector.

BOARD FUNCTIONSA block diagram of the 10-bit display interface board is shown in Figure 2. The following sections briefly describe these functional blocks.

DATA DEMULTIPLEXINGThe Altera EP1C6QC240 FPGA (U6) performs most of the logic functions on the 10-bit display interface board. Among these functions is the demultiplexing of the digital RGB data output from the AD998x when it is in single-port data output (30-bit) mode (the AD9981 and AD9980 are 30-bit only). The DVI and LVDS transmit-ters, as well as the digital-to-analog converters (DACs), require dual-port digital RGB data. Therefore, demulti-plexing is required when in single-port mode.

DE GENERATIONThe DVI and LVDS interfaces require a data enable (DE) signal which indicates when there is active image data. Since the analog graphics signal does not contain DE, the FPGA on the 10-bit display interface board is required to generate it. The duration of DE is programmable via the 10-bit DIB register map of the display electronics (DEPL) evaluation software and supports any display resolution up to 4096 pixels 4096 pixels.

COLOR SPACE CONVERSIONThe FPGA contains circuitry to perform color space con-version for 30-bit YPbPr data. This can be enabled via the 10-bit DIB register map of the DEPL evaluation software. This can be used in conjunction with the midscale clamp feature on the analog interface of the AD998x devices to provide the proper colors for an YPbPr video signal. The color space conversion also works with YPbPr signals transmitted over the DVI interface. For the most accurate color space conversion, the conversion results in a 12-bit output for each of the digital RGB output channels. This minimizes the rounding errors that can result from the conversion process.

1210 8

1210 8

1210 8

1210 8

1210 8

1210 8

BLU A

BLU B

GRN A

GRN B

RED A

RED B

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12

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LVDS XMITWITH CONNECTOR

POWER

VGACONN

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(SINGLE PORT MODE),DE GENERATION,

DE CONTROL, COLORCONVERSION]

TMDSXMIT

DIGITAL RGBAND SYNCS

FROM AD988x

PARALLELINTFC CONN USB

INTFC

SERIAL INTERFACE

SYNCS

TO FLAT PANELMONITORORLCD PROJECTOR

TO CRTORFLAT PANELMONITOR

DVI

CONNEC

TOR

TO TFT PANEL

05441-002

Figure 2. 10-Bit Display Interface Board Block Diagram

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DVI OUTPUTThe 10-bit display interface board provides a DVI output via SiI160 transmitter (U15) and DVI-I connector (J8). This can be connected via DVI cable to any display device (flat panel monitor or LCD projector) to display any image from VGA to UXGA-60 (the SiI160 is limited to 25 MHz to 165 MHz operation). Note that the SiI160 is capable of processing only 8-bit data. Therefore, only the 8 MSBs of the data output from the FPGA are used for the DVI output.

LVDS OUTPUTThe 10-bit display interface board provides an LVDS output via DS90C387 transmitter (U5) and LVDS data connector (J9). This can be connected via user-provided cable to any board flat panel with LVDS interface (such as Samsung’s 21.3’’ UXGA panel, LTM213U3-L01-0, or Sharp’s 18’’ SXGA panel, LQ181E1LW31) to display an image using that panel’s native resolution. This interface is capable of operating up to UXGA-75 (202.5 MHz). Note that the DS90C387 is capable of processing only 8-bit data. Therefore, only the 8 MSBs of the data output from the FPGA are used for the DVI output.

ANALOG OUTPUTThe 10-bit display interface board provides an analog output via high performance AD9753 DACs (U11 to U13) and 15-pin VGA connector (J6). The AD9753 is a 12-bit DAC that provides precision digital-to-analog conver-sion. Therefore, the analog output port is the best choice to demonstrate the full 10-bit performance of the AD998x devices. The analog output can be connected via VGA

cable to any display device (flat panel monitor, CRT, or projector) to display any image from VGA to UXGA-75.

SERIAL BUS TO COMPUTER INTERFACE (USB OR PRINTER PORT)Some circuitry is needed in order to interface the AD998x and the 10-bit display interface board’s serial register interface with a computer. The 10-bit display interface board provides both a USB and a parallel (printer) port interface. The USB interface consists of a USB-B con-nector (J2), USB controller (U14), and an EEPROM (U16) that contains board ID information. The circuitry for the printer port’s serial interface use U1 and U9, in addition to the Centronix connector, J1.

POWERThe 10-bit display interface board has two voltage regu-lators that generate 1.5 V and 3.3 V for its own logic. These voltages are regulated off of the 5 V input at J4. The 5 V input is also routed to the AD998x evaluation board interface connector (J3) to provide power for the AD998x evaluation board.

EVALUATION BOARD CONNECTIONSFigure 3 shows how the 10-bit display interface board interfaces with the AD9981 evaluation board. It also indicates the various connections needed to evaluate an image.

Figure 3. 10-Bit Display Interface Board with AD9981 Evaluation Board

05441-004ANALOG

OUTPUT

5VINPUT

DVIOUTPUT

LVDSOUTPUT

USBINTERFACE

PARALLEL INTERFACE

ANALOGINPUTS FOR

AD9981

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CONFIGURING THE BOARD

DE GenerationThe VS_SEL (W15 on schematic) and HS_SEL (W16 on schematic) jumpers allow you to choose raw VSYNC and HSYNC or the VSOUT and HSOUT outputs of the AD998x to generate DE. If the jumpers are placed between Pins 1 and 2 (closer to U2), the raw HSYNC and VSYNC are selected. If the jumpers are placed between Pins 2 and 3, the sync outputs (HSOUT and VSOUT) of the AD998x are selected. Either configuration works, although the HSYNC and VSYNC delay values used for DE generation vary slightly in each case.

PC Port SelectionThe jumpers at W1 and W2 must be configured appropri-ately to use the desired PC port for software control. To select USB, the jumpers must be placed between Pins 2 and 3. To select the printer port, the jumpers should be placed between Pin 1 and Pin 2.

To USB Driver InstallationFollow these steps to install the USB drivers on your PC:1. Connect the board to the power supply.2. Connect the USB cable from the PC to the board.3. Windows sees the new device and asks to install drivers for it. 4. Select Search for Drivers and click Next.5. Specify a location and browse on the CD-ROM to the USB Drivers\win2k directory.6. Click Next and follow any remaining instructions.7. If asked for any files, always browse to the same USB Drivers\win2k (or \win98) folder to find them.

DCLK SelectionThe 10-bit display interface board is configured so that the DCLK output of the AD998x drives the generation of PANEL_DCLK and PANEL_DE. This is accomplished through the placement of a jumper between Pins 1 and 2 of Header W3.

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EVALUATION BOARD SOFTWAREThe 10-bit display interface board (DIB) registers can be controlled using the 10-bit DIB register map of the DEPL evaluation software. This software is a Visual Basic® program requiring a Windows® 95, or later, operating system. It is on a self-installing CD package included with the evaluation board (in the \DEPL Evaluation Software subdirectory). The 10-bit DIB register map of the DEPL evaluation software should be loaded into the \Program Files\ADI Software directory upon completion of a suc-cessful installation.

Note: If a DriverX Install error is encountered during the software installation, rerun the driverxinstall.exe

program located in the Program Files\Analog Devices\DEPL Evaluation Software\DriverX directory.

The 10-bit DIB register map can be accessed two ways. From the menu bar, select Device > 10Bit DIB. The 10-bit DIB register map can also be accessed by selection Tools > 10-Bit Display Interface Board Configura-tion. The 10-bit DIB register map is shown in Figure 4. Using this screen, the user can control the features of the 10-bit DIB.

To implement the controls, click Load. This is true unless the Load Register on Change box is checked or the Read button is clicked. In this case, the registers are updated as soon as any change is made in the window.

05441-003

Figure 4. Display Interface Board Configuration Setup Window

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10-BIT DIB REGISTER DESCRIPTIONS

Hsync Delay (01–7:0)Register 01 controls the number of data clock cycles that occur between Hsync and the beginning of DE. This is a decimal number that is written to an 8-bit register. For ease of use, a sliding bar is also included as an alterna-tive method for controlling the Hsync delay. Moving the bar to the right increases the delay and is reflected in the box to the right. Moving the bar left decreases the delay.If using the DVI output of the 10-bit display interface board, note that an image might not be visible until the Hsync Delay is near the appropriate amount of delay from Hsync to active video.

Vsync Delay (02–7:2)Bits 7:2 of Register 02 control the number of Hsync periods that occur between Vsync and the beginning of DE. This is a decimal number that is written to a 6-bit register. A sliding bar is also included for Vsync delay control.

LVDS/DVI Interface Enable (02–1:0)Bits 1:0 of Register 02 serve as enable bits to turn on the LVDS and DVI interface outputs of the 10-bit DIB. It is recommended that these interfaces be powered down when not in use.

Horizontal Resolution (03–7:04–4)Horizontal resolution must be set using the 12 bits span-ning Register 3, Bit 7 (MSB) to Register 4, Bit 4 (LSB). The resolution is set in number of pixels by typing the decimal number directly into the text box on the right or by moving the scroll bar next to it. The maximum value is 4096.

Vertical Resolution (05–7:06–4)Vertical resolution must be set using the 12 bits span-ning Register 5, Bit 7 (MSB) to Register 6, Bit 4 (LSB). The resolution is set in number of lines by typing the decimal number directly into the text box on the right or by moving the scroll bar next to it. The maximum value is 4096.

DE Settings for Interlaced Video (06–3:0)When generating a data enable (DE) from an interlaced video source, it is necessary to provide for an offset between the odd and even fields. Bits 3:1 of Register 6 allow you to program the amount of offset (in number of lines) between the two fields. Bit 0 allows you to select how the even and odd fields are differentiated from each other. The AD998x devices have an ODD_EVEN~ signal that is routed to the 10-bit DIB’s FPGA and can be used to determine the differentiation by setting this bit to a Logic 1. If using a device that does not provide this signal, the FPGA generates its own signal to provide this function. This signal can be selected by setting Bit 0 to Logic 0.

DE Select (07–7)This bit allows you to select the source for data enable generation. If the analog interface of the AD998x is being used, Generated DE must be selected since the analog interface does not include a DE signal. If the DVI inter-face of the AD998x is being used, either Generated DE of Digital DE can be used. However, it is recommended that the Digital DE be selected in this case.

Port Mode (07–6)This bit allows the user to select the operating mode of the AD998x. If the AD998x is operating in single-channel (30-bit) output mode (the AD9981 and the AD9980 have single-channel output only), single port mode must be selected. If the AD998x is operating in dual-channel (60-bit) output mode, Dual Port (60 bit) must be selected.

DAC Frequency (07–5:4)From the DAC Frequency Range menu, you can select the operating range of the analog output. The 12 MHz to 100 MHz range should be adequate to display all resolu-tions XGA and above (including 720p and 1080p). For lower speed resolutions, the appropriate range should be selected.

Color Conversion Enable (07–3)The color conversion enable bit allows you to turn on the 30-bit color space converter in the FPGA.

Half Clock Invert (07–2)The bit allows the user to route the first pixel of demul-tiplexed 30-bit data to the even output port of the FPGA rather than the odd output port. The timing relation between data and the data clock (PANEL_CLK_OUT) remain the same. This bit is useful when centering the image using the Hsync delay register.

PC Port SelectionTo select between the USB and parallel ports for the software interface click on the Options pull-down menu and click on Device Interface and then select either USB or Parallel. Refer to the PC Port Selection section for further setup instructions.

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SCHEMATICS AND LAYOUTThe schematics and layout for this board can also be found on the CD.

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100101102103104105106107108109110111112113114115116117118119120

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1.5V

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RSTBLUA_IN9BLUA_IN8BLUA_IN7BLUA_IN6BLUA_IN5BLUA_IN4BLUA_IN3

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RSTPANEL_ENSPARE17SPARE16DE_DETECT1DE_DETECT2LATCH_DE

LATCH_DE

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3.3VSPARE3

DEV_CLRNBLUA_IN9BLUA_IN8BLUA_IN7BLUA_IN6BLUA_IN5BLUA_IN4BLUA_IN3

GND18VCCIO12

GND17VCCINT6

BLUA_IN2BLUA_IN1BLUA_IN0

SPARE_IO24SPARE_IO23SPARE_IO22SPARE_IO21SPARE_IO20

RSTPANEL_EN

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DE_DETECT1DE_DETECT2

LATCH_DELATCH_DE

GND16VCCINT5

GND15VCCIO11

SPARE_IO17SPARE_IO16SPARE_IO15SPARE_IO14SPARE_IO13SPARE_IO12SPARE_IO11SPARE_IO10

SPARE_IO9SPARE_IO8SPARE_IO7SPARE_IO6SPARE_IO5REGEN_VSREGEN_HS

DE_OUTGND14

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LVDS_ENBLU_EVEN11BLU_EVEN10

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TP25

TP1

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TP24

TP26

TP15TP16

TP4

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TP23

TP22

TP17

1

11

1

11

11

11

11

TP5

TP20TP19

11

1

TP391

LVD

S_E

NB

LU

_EV

EN

11B

LU

_EV

EN

10B

LU

_EV

EN

9B

LU

_EV

EN

8B

LU

_EV

EN

7B

LU

_EV

EN

6

TP45

TP46

TP42TP44

TP43

1

11

1

1

SM

T_L

ED

D1

TP41TP40

1

1

3.3V

10B

IT_D

IB_F

PG

AE

P1C

6QC

240

U6

AD

D T

HIS

TE

XT

TO

SIL

KS

CR

EE

N:

"DE

ON

"

U6

MO

LE

X_5

2760

-100

J3

AD

D N

ET

NA

ME

S F

OR

AL

L T

Ps

(EX

CE

PT

SP

AR

ES

) T

O S

ILK

SC

RE

EN

1T

P36

1T

P35

1T

P30

1T

P28

1T

P33

1T

P32

1T

P27

1

TP

6

SO

GO

UT

OD

D_E

VE

N~

VS

OU

T

DC

LK

HS

OU

T DIG

_DE

CL

AM

P

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100

BL

UA

_IN

8

BL

UA

_IN

6

BL

UA

_IN

5

RE

DA

_IN

9

RE

DA

_IN

8

NC

NC

NC

CT

L3

CT

L2

CT

L0

PW

R_D

N

DC

LK

CL

K_I

NV

VS

YN

C

HS

YN

C

SC

L

SD

AC

OA

ST

CT

L1

NC

NC

NC

NC

BL

UA

_IN

0B

LU

B_I

N0

BL

UB

_IN

9

BL

UB

_IN

8

BL

UB

_IN

7

BL

UB

_IN

6

BL

UB

_IN

5

BL

UB

_IN

4

BL

UB

_IN

3

BL

UB

_IN

2

BL

UB

_IN

1

GR

NB

_IN

6

GR

NB

_IN

8

GR

NB

_IN

9

GR

NB

_IN

7

GR

NB

_IN

5

GR

NB

_IN

4

GR

NB

_IN

3

GR

NB

_IN

2

GR

NB

_IN

1

GR

NB

_IN

0

RE

DB

_IN

6

RE

DB

_IN

8

RE

DB

_IN

9

RE

DB

_IN

7

RE

DB

_IN

5

RE

DB

_IN

4

RE

DB

_IN

3

RE

DB

_IN

2

RE

DB

_IN

1

RE

DB

_IN

0

RE

DA

_IN

1

RE

DA

_IN

2

RE

DA

_IN

3

RE

DA

_IN

4

RE

DA

_IN

5

RE

DA

_IN

6

RE

DA

_IN

7

RE

DA

_IN

0

GR

NA

_IN

6

GR

NA

_IN

8

GR

NA

_IN

9

BL

UA

_IN

4

BL

UA

_IN

3

BL

UA

_IN

2

BL

UA

_IN

1

GR

NA

_IN

7

BL

UA

_IN

7

BL

UA

_IN

9

GR

NA

_IN

0

GR

NA

_IN

1

GR

NA

_IN

2

GR

NA

_IN

3

GR

NA

_IN

4

GR

NA

_IN

5

5V

1

TP

31

1T

P29

1T

P34

1T

P49

1T

P48

1 3 5 7 9

2 4 6 8 10

J7

ALT

_CS

O

ALT

_NC

ON

FIG

ALT

_AS

DO

ALT

_DA

TA

ALT

_DC

LK

ALT

_CF

G_D

N

3.3V

ALT

_NC

E

R56

10k

10k

R55

10k

R54

EP

CS

1U

2

8 7 6 54321

ALT

_CS

O

ALT

_DA

TA

3.3V

ALT

_AS

DO

ALT

_DC

LK

3.3V

VC

C3

VC

C2

DC

LK

AS

DI

GN

D

VC

C1

DA

TA

NC

S

VS

OU

T

RA

W

RA

W

HS

OU

T

HS_SEL VS_SEL

AD

D T

HIS

TE

XT

TO

SIL

KS

CR

EE

N

VS

YN

C

VS

OU

T

HS

YN

C

HS

OU

T

W15

W16

HS

YN

C_I

N

VS

YN

C_I

N

05441-005

PE

VR

571k

R13 0 P

NL

_CL

K_D

VI

Figure 5.

REV. 0

–8–

AN-784

Figure 6.

RA1

RA3

2222

BLU

_B8

BLU

_A8

BLU

_B9

BLU

_A9

BLU

_B10

BLU

_A10

BLU

_B11

BLU

_A11

BLU

_EVE

N11

BLU

_ODD11

BLU

_EVE

N10

BLU

_ODD10

BLU

_EVE

N9

BLU

_ODD9

BLU

_EVE

N8

BLU

_ODD8

RA5

RA7

RA9

RA2

RA6

RA8

RA10

22 22 2222

22 22 22

1 1 11

1 1 1

16 16 1616

16 16 16

GRN_E

VEN11

GRN_O

DD7

RED

_EVE

N3

BLU

_EVE

N7

GRN_E

VEN3

RED

_EVE

N11

RED

_ODD7

GRN_B

11

GRN_A

7

RED

_B3

BLU

_B7

GRN_B

3

RED

_B11

RED

_A7

2 2 22

2 2 2

15 15 1515

15 15 15

GRN_E

VEN10

GRN_O

DD6

RED

_EVE

N2

BLU

_EVE

N6

GRN_E

VEN2

RED

_EVE

N10

RED

_ODD6

GRN_B

10

GRN_A

6

RED

_B2

BLU

_B6

GRN_B

2

RED

_B10

RED

_A6

3 3 33

3 3 3

14 14 1414

14 14 14

GRN_E

VEN9

GRN_O

DD5

RED

_EVE

N1

BLU

_EVE

N5

GRN_E

VEN1

RED

_EVE

N9

RED

_ODD5

GRN_B

9

GRN_A

5

RED

_B1

BLU

_B5

GRN_B

1

RED

_B9

RED

_A5

4 4 44

4 4 4

13 13 1313

13 13 13

GRN_E

VEN8

GRN_O

DD4

RED

_EVE

N0

BLU

_EVE

N4

GRN_E

VEN0

RED

_EVE

N8

RED

_ODD4

GRN_B

8

GRN_A

4

RED

_B0

BLU

_B4

GRN_B

0

RED

_B8

RED

_A4

5 5 55

5 5 5

12 12 1212

12 12 12

GRN_E

VEN7

GRN_O

DD3

RED

_ODD11

BLU

_EVE

N3

GRN_O

DD11

RED

_EVE

N7

RED

_ODD3

GRN_B

7

GRN_A

3

RED

_A11

BLU

_B3

GRN_A

11

RED

_B7

RED

_A3

6 6 66

6 6 6

11 11 1111

11 11 11

GRN_E

VEN6

GRN_O

DD2

RED

_ODD10

BLU

_EVE

N2

GRN_O

DD10

RED

_EVE

N6

RED

_ODD2

GRN_B

6

GRN_A

2

RED

_A10

BLU

_B2

GRN_A

10

RED

_B6

RED

_A2

7 7 77

7 7 7

10 10 1010

10 10 10

GRN_E

VEN5

GRN_O

DD1

RED

_ODD9

BLU

_EVE

N1

GRN_O

DD9

RED

_EVE

N5

RED

_ODD1

GRN_B

5

GRN_A

1

RED

_A9

BLU

_B1

GRN_A

9

RED

_B5

RED

_A1

8 8 88

8 8 8

9 9 99

9 9 9

GRN_E

VEN4

GRN_O

DD0

RED

_ODD8

BLU

_EVE

N0

GRN_O

DD8

RED

_EVE

N4

RED

_ODD0

RA4

22

116

BLU

_ODD7

BLU

_A7

215

BLU

_ODD6

BLU

_A6

314

BLU

_ODD5

BLU

_A5

413

BLU

_ODD4

BLU

_A4

512

BLU

_ODD3

BLU

_A3

611

BLU

_ODD2

BLU

_A2

710

BLU

_ODD1

BLU

_A1

89

BLU

_ODD0

BLU

_A0

GRN_B

4

GRN_A

0

RED

_A8

BLU

_B0

GRN_A

8

RED

_B4

RED

_A0

PLACEMOUNTINGHOLE

SIN

EACHCORNER

OFTH

EPC

B.

H1

H2

H3

H4

THECLO

CKDEL

AYCIRCUITSH

OWN

HER

EIS

AST

UFF

INGOPT

.

PLACEU10

ASCLO

SEASPO

SSIBLE

TOU6.

KEE

PTH

ESETR

ACES

ASSH

ORTASPO

SSIBLE

.

INOUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

OUT8

OUT9

OUT10

3D7110

GND;7

PLACENEA

RU6:174

PLACENEA

RW23

R14 0Ω

PNL_CLK

_LVD

S2

PANEL

_CLK

_IN_D

LY

PANEL

_CLK

_IN_D

LY2

R22

0Ω

PANEL_CLK_LVDS1

PNL_CLK

_LVD

S

R20

0Ω

W25

W24

R15

22Ω

1113 3 12 4 11 5 10 6 9 8

U10

3.3V

;14

W23

OUT10

OUT8

OUT789

OUT1

W22

OUT5

OUT6

OUT9

OUT7

OUT4

OUT3

OUT2

OUT123

OUT456

05441-006

REV. 0

–9–

AN-784

Figure 7.

SII160

U15

3.3V

;8,30,56,88

GND;7,19,31,33,37,41

GND;47,57,67,79,86,89

RES

1

RES

2

RES

3

RES

4

CTL1

CTL2

TXC–

TXC+

TX0–

TX0+

TX1–

TX1+

TX2–

TX2+

EXT_SWING

PIXS

EDGE

IDCK

DE

VSYN

C

HSY

NC

BE[7:0]

GE[7:0]

RE[7:0]

BO[7:0]

RO[7:0]

GO[7:0]

IVCC4

IVCC3

IVCC2

IVCC1

AVCC3

AVCC2

AVCC1

PVCC2

PVCC1

CTL3

PD

RES

5

RES

6

RES

7

RES

8GND;3,11,15,19,22

DVI_A

D(VIEW

FROMBOTT

OM)J8

RXC

+RXC

–

VSYC

HSY

C

BLU

EGREN

RED

RX0

–RX0

+

RX1

+RX1

–

RX2

+RX2

–

DDCSD

ADDCSC

L

ROUTE

THES

EAS50

ΩDIFFE

REN

TIALPA

IRS

EXT_SW

ING

PIXS

EDGE

DVI_E

N

23 24825282726 171810 92 17 6

DVI_TXC

–

PNL_CLK

_DVI

R8

510Ω

3.3V

DVI_TXC

+

DVI_TX0

–

84

83

3435394042434546

32

26

25

24

80787776

[9:16]

[99:100],[1:6]

[90:97]

[68:75]

[48:55]

[58:65]

98

81

66

17

44

38

36

85

18

82

2987 202122232728

AVD

D

R7

4.75kΩ

R3

4.75kΩ

3.3V

DVI_P

VCC

AVD

D

GRN_B

[11:4]

RED

_B[11:4]

BLU

_B[11:4]

RED

_A[11:4]

GRN_A

[11:4]

BLU

_A[11:4]

REG

EN_H

S

REG

EN_V

S

DE_

OUT

DVI_TX2

+

DVI_TX2

–

DVI_TX1

+

DVI_TX1

–

DVI_TX0

+

3.3V

05441-007

REV. 0

–10–

AN-784

Figure 8.

1

1011

1213

1415

1617

1819

2 2021

2223

2425

2627

28293

3031

45

67

89

FI-W

E31P

-HF

J9

1

1011

1213

1415

1617

1819

2 2021

2223

2425

2627

28293

3031

45

67

89

TXOUT7+

TXOUT7–

TXOUT6+

TXOUT6–

TXOUT4–

TXOUT5+

TXOUT5–

TXOUT4+

TXOUTC

LK+

TXOUTC

LK–

TXOUT3–

TXOUT3+

TXOUT2+

TXOUT2–

TXOUT1+

TXOUT1–

TXOUT0+

TXOUT0–

A1M A1P

A2M A2P

A3M A3P

A4M A4P

A5M A5P

A6M A6P

A7M A7P

AOM

AOP

B10

B11

B12

B13

B14

B15

B16

B17

B20B21B22B23B24B25B26B27

BAL

CLK

1MCLK

1P

CLK

2M/NC

CLK

2P/NC

CLKIN

DEDUAL

G10G11

G12

G13

G14

G15

G16

G17

G20G21G22G23G24G25G26G27

HSYNC

PLLSELPRE

R10R11R12R13R14R15R16R17

R20

R21

R22

R23

R24

R25

R26

R27

R_FBR_FDE

VSYNC

PD

FROMFP

GA

LVDS_

EN

RED_A10RED_A9RED_A8RED_A7RED_A6RED_A5RED_A4

RED

_B11

RED

_B10

RED

_B9

RED

_B8

RED

_B7

RED

_B6

RED

_B5

RED

_B4

BLU_B11BLU_B10BLU_B9BLU_B8BLU_B7BLU_B6BLU_B5BLU_B4

BLU

_A11

BLU

_A10

BLU

_A9

BLU

_A8

BLU

_A7

BLU

_A6

BLU

_A5

BLU

_A4

GRN_B11GRN_B10GRN_B9GRN_B8GRN_B7GRN_B6GRN_B5GRN_B4

GRN_A

11GRN_A

10GRN_A

9GRN_A

8GRN_A

7GRN_A

6

GRN_A

5GRN_A

4

PNL_CLK

_LVD

S2

47 46 45 44 39 38 37 36 34 33 32 31 29 2850 49

9291908988878685

6463626160595857

24

42 41 27 2611

5623

21

1009996959493

7473727170696665

54

1514

109876543

84818079787776

75

2021

5522

U5

DS9

0C387

GND;13,16,17,19,25,35,51,52,43,68,83,98

3.3V

;53,67,82,97

LVPL

L_VC

C;12,18

LVDS_

VCC;30,40,48

R27

4.75kΩ

R26

4.75kΩ

R25

4.75kΩ

R24

4.75kΩ

R23

4.75kΩ

RED_A11

TXOUT0–

TXOUT0+

TXOUT1–

TXOUT1+

TXOUT2–

TXOUT2+

TXOUTC

LK–

TXOUTC

LK+

TXOUT3–

TXOUT3+

TXOUT4–

TXOUT4+

TXOUT5–

TXOUT5+

TXOUT6–

TXOUT6+

TXOUT7–

TXOUT7+

REG

EN_H

S

REG

EN_V

SDE_

OUT

PRE

3.3V

R_FBR_FDE

DUALBAL

05441-008

LVDSOUTP

UTCONNEC

TOR

REV. 0

–11–

AN-784

Figure 9.

GND;4,22,44,45

AVDD

CLKVDD

DVDD1DVDD2

IOUTA

IOUTB

PLLVDD

PLLL

OCK

FSADJ

REF

IO

LPF

DIV1

DIV0

CLK

–CLK

+

RST PORT1B[11:0]

PORT2B[11:0]AD9753

U11

ACLK

R

PLLV

DD

RED

_A[11:0]

41

48

215

43 42

47

6 40 39

463837321

[7:18]

[23:34]

PNL_CLK

_ALG

C9

1µF

PLLV

DD

R28

392Ω

R29

4.75kΩ

R33

75Ω

R32

37.4

Ω

R31

2kΩ

C5

0.1µF

R30

4.75kΩ

1TP

12

3.3V

AVD

D

RED

_B[11:0]

DAC_D

IV0

DAC_D

IV1

RPL

L_LO

CK

ARED

_OUT

ROUT–

RFS

ADJ

RREF

CLK

VDD

GND;4,22,44,45

AVDD

CLKVDD

DVDD1DVDD2

IOUTA

IOUTB

PLLVDD

PLLL

OCK

FSADJ

REF

IO

LPF

DIV1

DIV0

CLK

–CLK

+

RST PORT1B[11:0]

PORT2B[11:0]AD9753

U12

ACLK

G

PLLV

DD

GRN_A

[11:0]

41

48

215

43 42

47

6 40 39

463837321

[7:18]

[23:34]

PNL_CLK

_ALG

C8

1µF

PLLV

DD

R34

392Ω

R45

4.75kΩ

R37

75Ω

R36

37.4

Ω

R35

2kΩ

C6

0.1µF

R44

4.75kΩ

1TP

13

3.3V

AVD

D

GRN_B

[11:0]

DAC_D

IV0

DAC_D

IV1

GPL

L_LO

CK

AGRN_O

UT

GOUT–

GFS

ADJ

GREF

CLK

VDD

GND;4,22,44,45

AVDD

CLKVDD

DVDD1DVDD2

IOUTA

IOUTB

PLLVDD

PLLL

OCK

FSADJ

REF

IO

LPF

DIV1

DIV0

CLK

–CLK

+

RST PORT1B[11:0]

PORT2B[11:0]AD9753

U13

ACLK

B

PLLV

DD

BLU

_A[11:0]

41

48

215

43 42

47

6 40 39

463837321

[7:18]

[23:34]

PNL_CLK

_ALG

C10 1µF

PLLV

DD

R38

392Ω

R43

4.75kΩ

R41

75Ω

R40

37.4

Ω

R39

2kΩ

C7

0.1µF

R42

4.75kΩ

1TP

14

3.3V

AVD

D

BLU

_B[11:0]

DAC_D

IV0

DAC_D

IV1

BPL

L_LO

CK

ABLU

_OUT

BOUT–

BFS

ADJ

BREF

CLK

VDD

CON-HD-15HM

ARED

_OUT

AGRN_O

UT

15654321 1413121110987

J6

ABLU

_OUT

REG

EN_H

S

REG

EN_V

S

05441-009

REV. 0

–12–

AN-784

Figure 10.

A1

A0

A2

VSS

SDA

SCL

WP

VCC

24LC

O4B

U16

GND6

D0

D1

D2

D3

D4

D5

D6

D7

BKPT

VCC2

PC0/RXD0PC1/TXD0PC2/INT0#PC3/INT1#PC4/T0PC5/T1PC6/WR#PC7/RD#

VCC

AVC

CXO

UT

XIN

AGND

GND4

GND3

GND2

GND1

CLK

24

GND5RESET

VCC1

VCC3DISCON#USBD+USBD–

PA5/FRD#PA4/FWR#

GND8WAKEUP#

SCLSDA

GND7

GND

AN2126SC

U14

XTAL2

XTAL1

GND;5,6USB

_A

GND

–DATA

+DATA

PWR_IN

1B4

1B3

1B2

1B1

2B1

2B2

2B3

2B4

S1S0

2OE

1A 2A GND;8

SN74CBLT

V3253

3.3V

;16

1OE

36CRPX

J1

G19

G20

G21

G22

G23

G24

G25

G26

G27

G28

G29

G30

P1P2P3P4P5P6P32

P31

EN

C1

1D1Q

2D2Q

5D6D6Q 4Q5Q7Q

7D8D8Q

3D3Q

4DEN

C1

1D1Q

2D2Q

5D6D6Q 4Q5Q7Q

7D8D8Q

3D3Q

4D

74VH

C14

74VH

C14

74VH

C14

74VH

C14

STROBE

FROMPC

3-ST

ATE

DATA

LINE

1

NOTE

:PLA

CEW1ANDW2IN

AROW

AND

ADDTH

ISTE

XTTO

THESILK

SCREE

N.

SOFT

WAREINTE

RFA

CESE

LECTIONUSINGW1-W2:

SELE

CTUSB

:STR

APS

BET

WEE

NPINS2AND3

SELE

CTPA

RALL

EL:S

TRAPS

BET

WEE

NPINS1AND2

8

U91011

U9

SCL_U

SCL_USB

21

43

R52

4.75kΩ

R17

4.75kΩ

PAR_STRB

3613

3514

3316

3217

3019

2920

2722

2623

25 24U1

LCX1

6374A

LCX1

6374A

GND;4,10,15,21,

28,34,39,45

WR_E

N

SER_D

AT_2P

C

SER_D

AT_2B

D

R46

2kΩ

R18

2kΩ

R21

2kΩ

3.3V

3.3V

R19

2kΩ

472

463

445

436

383712

48 1

811 940 41

U1

3.3V;7,18,31,42192021222324252627282930

1

[33:36]

2345632 31

[10:18]

SDA_P

AR

3.3V3.

3V

SDA_S

EL

SDA_U

SB

SCL_EE

SDA_E

E

SCL_SE

L

USB

_SDA

3.3V

3.3V

USB

_SCL

3456 10 11 12 13

214

157 91

U7

R47

24.3

Ω

USBDUSBD

USB

_DATA

USB

_DATA

R50

2.21kΩ

1 2 3 4

J2

3.3V

R16

2.21kΩ

R51

1.5k

ΩR48

24.3

Ω

C101

22pF

C102

22pF

21

X212MHz

CRYS

TAL

C11 1µF

USBRST

R49

10kΩ

2324252627282930313233

1415161718192021

1110987654321

1213

22

4443424140393837363534

AVD

D

XIN

XOUT

21 3 4678

R5

10kΩ

R10

10kΩ

11

22

R12

10kΩ

R11

10kΩ

W2

W1

SCL_USB

SCL

SCL_PAR

SCL_PA

R

SER_C

LK

SDA_PAR

SDA

SDA_USB

5

32

13

2

CEN

TRONICS36

PIN

PRINTE

RPO

RTCONNEC

TOR

SERIALINTE

RFA

CECIRCUIT U

9U9

11

22

05441-010

9

REV. 0

–13–

AN-784

Figure 11.

C4

C2

C34

C28

C36

C35

C31

C29

C30

C13

C40

C39

C43

C37

C44

C48

C45

C46

C47

C12

C42

C41

C56

C57

C58

C59

C55

C54

10µF

10µF

0.1µF

0.1µF

0.1µF

0.1µF

0.1µF

0.1µF

0.1µF

0.1µF

0.1µF

0.1µF

0.1µF

0.1µF

0.1µF

0.1µF

0.1µF

0.1µF

0.1µF

0.1µF

0.1µF

0.1µF

0.1µF

0.1µF

0.1µF

0.1µF

0.1µF

0.1µF

C76

C77

C78

C79

C80

C81

C82

C83

C84

C85

C86

C87

C88

C18

C20

C25

C89

C90

C19

0.1µF

0.1µF

0.1µF

0.1µF

0.1µF

0.1µF

0.1µF

0.1µF

0.1µF

0.1µF

0.1µF

0.1µF

0.1µF

0.1µF

0.1µF

0.1µF

0.1µF

0.1µF

0.1µF

++

2V O

UT

V IN

GND 1

3

11

11 TP

10

TP9

TP21

TP11

R53

1kΩ

D2

SMT_LE

DADDTE

XTTO

SILK

SCREE

N:"PW

RON"

C27

C16

C15

C23

C24

C22

C21

10µF

0.1µF

0.1µF

0.1µF

0.1µF

0.1µF

0.1µF

3.3V

3.3V

LM1085IT

+

U8

2V O

UT

V IN

GND 1

31.5V

ADJ

LM1086CS

U3

2 J4

+C26

10µF

C17

C61

C62

C63

C64

C60

C65

C95

0.1µF

0.1µF

0.1µF

0.1µF

0.1µF

0.1µF

0.1µF

0.1µF

C49

10µF

+

12FB

1

MHz

AVD

D

C96

C98

0.1µF

0.1µF

C50

10µF

C51

10µF

+ +

1 1

2 2

FB3

FB2

MHz

MHz

PLLV

DD

DVI_P

VCC

C69

C66

C68

C67

0.1µF

0.1µF

0.1µF

0.1µF

C99

C97

0.1µF

0.1µF

C52

10µF

C53

10µF

+ +

1 1

2 2

FB5

FB4

MHz

MHz

LVDS_

VCC

LVPL

L_VC

C

C72

C74

C71

C75

0.1µF

0.1µF

0.1µF

0.1µF

ANALO

GSU

PPLY

FORDACSAND

DVI

TRANSM

ITTE

R

C73

0.1µF

C70

0.1µF

DACPL

LSU

PPLY

DVI

PLLSU

PPLY

LVDSSU

PPLY

LVDSPL

LSU

PPLY

DACCLK

SUPP

LY

10µF

C1

CLK

VDD

3.3V

C104

0.1µF

0.1µF

C103

0.1µF

C38

0.1µF

C3

12F

B6

MHz

+

HSM

S-2814

R2

10kΩ

123

CR1

C33 1µF

LATC

H_D

EDE_

DET

ECT1

HSM

S-2814

12R1

10kΩ

123

CR2

C32 1µF

LATC

H_D

EDE_

DET

ECT2

1

GND

SRT

VCC

RST

LP3470

U4

VCC1

POWER

-ONRES

ET

SRT

RST

_PWR

21

45

3

R4

1kΩ

C14

0.1µF

S1PB

_SWR

92k

Ω

RST

3.3V

3.3V

2

05441-011

5V

R59

121Ω

R60

24.3

Ω

12

REV. 0

–14–

AN-784

Figure 12.

05441-012

REV. 0

–15–

AN-784

Figure 13.

05441-013

REV. 0

–16–

AN-784

Figure 14.

05441-014

REV. 0

–17–

AN-784

Figure 15.

05441-015

REV. 0

–18–

AN-784

Figure 16.

05441-016

REV. 0

–19–

AN-784

Figure 17.

05441-017

REV. 0

–20–

–21–

–22–

–23–

AN

0548

1–0–

4/0

5(0)

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