z. feng mtu ee480 14.1 ee4800 fall 2011 cmos digital ic design & analysis lecture 14 final exam...
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Z. Feng MTU EE480Z. Feng MTU EE48014.14.11
EE4800 Fall 2011
CMOS Digital IC Design & Analysis
Lecture 14 Final Exam ReviewZhuo Feng
Z. Feng MTU EE480Z. Feng MTU EE48014.14.22
■Final Exam Time►December 13th ►90 minutes: 13:00-14:30
■Five problems►Covers the latest five lectures
■One A4-size cheat sheet
■No lecture slides or textbooks allowed
Z. Feng MTU EE480Z. Feng MTU EE48014.14.33
■Interconnect►Wire resistance►Parasitic capacitance►Cross talk noise►Wire engineering
■Combinational Circuit►Bubble pushing►Logic effort calculation► Input order►Skewed gates►Asymmetric gate
Z. Feng MTU EE480Z. Feng MTU EE48014.14.44
■ Sequential Circuits► Flip-flop, latches► Clock period► Max-delay constraints (setup time constraints)► Min-delay constraints (hold time constraints)► Clock skew
■ 6T SRAM Cell► Read operation► Write operation► Transistor sizing► Decoder► Bitline Conditioning
■ Packaging, power distribution and clock distributions
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