voltage divider bias
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Voltage Divider Bias
ENGI 242ELEC 222
23 February 2005 ENGI 242/ELEC 222 2
BJT Biasing 3For the Voltage Divider Bias Configurations• Draw Equivalent Input circuit• Draw Equivalent Output circuit• Write necessary KVL and KCL Equations• Determine the Quiescent Operating Point
– Graphical Solution using Load lines– Computational Analysis
• Design and test design using a computer simulation
23 February 2005 ENGI 242/ELEC 222 3
Voltage-divider bias configuration
23 February 2005 ENGI 242/ELEC 222 4
Voltage Divider Input Circuit Approximate AnalysisThis method is valid only if R2 .1 RE
Under these conditions RE does not significantly load R2 and it may be ignored: IB << I1 and I2 and I1 I2 Therefore:
We may apply KVL to the input, which gives us:-VB + VBE + IE RE = 0Solving for IE we get:
2B CC
1 2
RV = VR +R
B BEE
E
V - V I = R
23 February 2005 ENGI 242/ELEC 222 5
Input Circuit Exact AnalysisThis method is always valid must be used when R2 > .1 RE
Perform Thevenin’s TheoremOpen the base lead of the transistor, and the Voltage Divider bias circuit is:
Calculate RTH
2TH CC
1 2
RV = VR +R
We may apply KVL to the input, which gives us:-VTH + IB RTH + VBE + IE RE = 0Since IE = ( + 1) IB
THTH E BE E E
TH BEE
E
THE
Solving for I we obtain
R-V + I + V + I R = 0 + 1
V - V I = R + R + 1
:
23 February 2005 ENGI 242/ELEC 222 6
Redrawing the input circuit for the network
23 February 2005 ENGI 242/ELEC 222 7
Determining VTH
2TH CC
1 2
RV = VR + R
23 February 2005 ENGI 242/ELEC 222 8
Determining RTH
1 2TH
1 2
R R R = R + R
23 February 2005 ENGI 242/ELEC 222 9
The Thévenin Equivalent Circuit
Note that VE = VB – VBE and IE = ( + 1)IB
23 February 2005 ENGI 242/ELEC 222 10
Input Circuit Exact Analysis
We may apply KVL to the input, which gives us:-VTH + IB RTH + VBE + IE RE = 0Since IE = ( + 1) IB
THTH E BE E E
TH BEE
E
THE
Solving for I we obtain
R-V + I + V + I R = 0 + 1
V - V I = R + R + 1
:
23 February 2005 ENGI 242/ELEC 222 11
Collector-Emitter Loop
23 February 2005 ENGI 242/ELEC 222 12
Collector-Emitter (Output) Loop
Applying Kirchoff’s voltage law: - VCC + IC RC + VCE + IE RE = 0
Assuming that IE IC and solving for VCE:
Solve for VE: VE = IE RE
Solve for VC: VC = VCC - IC RC or
VC = VCE + IE RE
Solve for VB: VB = VCC - IB RB or
VB = VBE + IE RE
CC CEC
C E
V - V I = R + R
23 February 2005 ENGI 242/ELEC 222 13
Voltage Divider Bias Example 1VCC = 22VR1 = 39kR2 = 3.9kRC = 10kRE = 1.5k = 140
23 February 2005 ENGI 242/ELEC 222 14
Voltage Divider Bias Example 2VCC = 18VR1 = 39kR2 = 8.2kRC = 3.3kRE = 1k = 120
23 February 2005 ENGI 242/ELEC 222 15
Voltage Divider Bias Example 3VCC = 16VR1 = 62kR2 = 9.1kRC = 3.9kRE = .68k = 80
23 February 2005 ENGI 242/ELEC 222 16
Design of CE Amplifier with Voltage Divider Bias1. Select a value for VCC
2. Determine the value of from spec sheet or family of curves3. Select a value for ICQ
4. Let VCE = ½ VCC (typical operation, 0.4 VCC ≤ VC ≤ 0.6 VCC )5. Let VE = 0.1 VCC (for good operation, 0.1 VCC ≤ VE ≤ 0.2 VCC )6. Calculate RE and RC
7. Let R2 ≤ 0.1 RE (for this calculation, use low value for )8. Calculate R1
CC B1 2
B
V - V R = RV
23 February 2005 ENGI 242/ELEC 222 17
CE Amplifier Design• Design a Common Emitter Amplifier with Voltage Divider
Bias for the following parameters:VCC = 24VIC = 5mAVE = .1VCC
VC = .55VCC
= 135
23 February 2005 ENGI 242/ELEC 222 18
23 February 2005 ENGI 242/ELEC 222 19
CE Amplifier Design
23 February 2005 ENGI 242/ELEC 222 20
CE Amplifier Design Voltage Divider Bias
Collector Feedback Bias
ENGI 242ELEC 222
23 February 2005 ENGI 242/ELEC 222 22
BJT Biasing 4For the Collector Feedback Bias Configuration:• Draw Equivalent Input circuit• Draw Equivalent Output circuit• Write necessary KVL and KCL Equations• Determine the Quiescent Operating Point
– Graphical Solution using Loadlines– Computational Analysis
• Design and test design using a computer simulation
23 February 2005 ENGI 242/ELEC 222 23
DC Bias with Collector (Voltage) Feedback
Another way to improve the stability of a bias circuit is to add a feedback path from collector to baseIn this bias circuit the Q-point is only slightly dependent on the transistor
23 February 2005 ENGI 242/ELEC 222 24
Base – Emitter Loop Solve for IB
Applying Kirchoff’s voltage law: -VCC + ICRC + IBRB + VBE + IERE = 0Note: IC = IE = IC + IB
Since IE = ( + 1) IB then: -VCC + ( + 1)IB RC + IBRB + VBE ( + 1)IBRE = 0
Simplifying and solving for IB: CC BEB
B C E
V - VI = R + (β + 1) (R + R )
23 February 2005 ENGI 242/ELEC 222 25
Applying Kirchoff’s voltage law: -VCC + IERC + IBRB + VBE + IERE = 0
Since IE = ( + 1) IB then:
Simplifying and solving for IE:
B
CC E C E BE E E
CC BEE
B C E
R-V + I R + I + V + I R = 0 ( + 1)
V - VI = R + (R + R ) (β + 1)
Base – Emitter Loop Solve for IE
23 February 2005 ENGI 242/ELEC 222 26
Collector Emitter Loop
Applying Kirchoff’s voltage law: IE RE + VCE + ICRC – VCC = 0Since IC = IE and IE = ( + 1) IB: IE(RC + RE) + VCE – VCC =0Solving for VCE: VCE = VCC – IE (RE + RC)
23 February 2005 ENGI 242/ELEC 222 27
Network Example
23 February 2005 ENGI 242/ELEC 222 28
Network Example
23 February 2005 ENGI 242/ELEC 222 29
Collector feedback with RE = 0
23 February 2005 ENGI 242/ELEC 222 30
Design of CE Amplifier with Collector Feedback Bias1. Select a value for VCC
2. Determine the value of from spec sheet or family of curves3. Select a value for IEQ
4. Let VCE = ½ VCC (typical operation, 0.4 VCC ≤ VC ≤ 0.6 VCC )5. Let VE = 0.1 VCC (for good operation, 0.1 VCC ≤ VE ≤ 0.2 VCC )6. Calculate RE, RC and RB
E CC
CC CQ CC CCC
E E
CC E C BE E EB
E
V = .1V
V - V V - .6V R = = ; I I
V - I R - V - I R R = ; I β + 1
CCE
E
CCC
E
CC E C EB
.1V R = I
.4V R = I
V - I (R + R ) - 0.7R = E
V I
β + 1
Common Emitter Bias with Dual Supplies
23 February 2005 ENGI 242/ELEC 222 32
Voltage Divider Bias with Dual Power Supply
23 February 2005 ENGI 242/ELEC 222 33
Voltage Divider Bias with Dual Power Supply
Input Circuit Find VTH and RTH
2 1
TH CC EE1 2
2TH1 CC
1
1 2
2
EE
1TH2 EE
1 2
TH
1 2TH
1
H1 TH
2
T 2
R V = V R + R
(Note V is negative) R V = - V
R + R V =
R R V = V - V R + R R + R
R R R = R +
V + V
R
23 February 2005 ENGI 242/ELEC 222 34
Voltage Divider Bias with Dual Power Supply
Output Circuit
where
CC C C CE E E EE
E C
C
CC EE CEC
C E
CC EE CEC
E C
E
V + V - V I = R +
-V + I R + V + I R - V = 0If we assume I I (when β > 100)
If we use the exact solution I = αR
V + V - V I = RR
I
β
α = β
+ α
+ 1
23 February 2005 ENGI 242/ELEC 222 35
Voltage Divider Bias with Dual Power Supply
PSpice Simulation
23 February 2005 ENGI 242/ELEC 222 37
PSpice Bias Point Simulation
23 February 2005 ENGI 242/ELEC 222 38
PSpice Simulation for DC Bias
23 February 2005 ENGI 242/ELEC 222 39
PSpice Simulation for DC Sweep
23 February 2005 ENGI 242/ELEC 222 40
PSpice Simulation for DC Sweep
The response of VCE demonstrates that it reaches a peak value near the Q point and then decreases
The response of VC demonstrates rises rapidly towards the Q Point and then increases gradually towards a maximum value
23 February 2005 ENGI 242/ELEC 222 41
PSpice Simulation for AC Sweep
23 February 2005 ENGI 242/ELEC 222 42
PSpice Simulation for AC Sweep
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