verilog - carleton universitylen/477w2003/lecturenotes/oct_15_2002.pdf · verilog, line comments...

Verilog

Presented by Jing Zhang

Based on “A Hardware Designer’s Guide to Verilog”

What is Verilog?

• Verilog is a Hardware Description Language– a textual format for describing electronic

circuits and systems. • Verilog is intended to be used for:

– verification through simulation– timing analysis– test analysis– logic synthesis.

Verilog is not VHDL

• VHDL is not an abbreviation for VerilogHDL — Verilog and VHDL are two different HDLs.

• The two languages are similar however, and one can generally do the same job as the other.

Design Flow using Verilog

• This diagram summarizes the high level design flow for an ASIC (ie. gate array, standard cell) or FPGA.

• In a typical design situation, each step is split into several smaller steps, and parts of the design flow will be iterated as errors are uncovered.

Verilog Uses …

•System-level VerificationVerilog may be used to model and simulate a complete system containing one or more ASICs. This may be a fully functional description of the system allowing the ASIC specification to be validated prior to commencing detailed design. Alternatively, this may be a partial description that abstracts certain properties of the system, such as a performance model to detect system performance bottle-necks.

… Verilog Uses …• RTL design and testbench creation

Once the overall system architecture and partitioning is stable, the detailed design of each ASIC can commence. This starts by capturing the ASIC design in Verilog at the register transfer level, and capturing a set of test cases in Verilog. These two tasks are complementary, and are sometimes performed by different design teams in isolation to ensure that the specification is correctly interpreted. The RTL Verilog should be synthesizable if automatic logic synthesis is to be used. Test case generation is a major task that requires a disciplined approach and much engineering ingenuity: the quality of the final ASIC depends on the coverage of these test cases.

… Verilog Uses …

• RTL verificationThe RTL Verilog is then simulated to validate the functionality against the specification. RTL simulation is usually one or two orders of magnitude faster than gate level simulation, and experience has shown that this speed-up is best exploited by doing more simulation, not spending less time on simulation.

• In practice it is common to spend 70-80% of the ASIC design cycle writing and simulating Verilog at and above the register transfer level, and 20-30% of the time synthesizing and verifying the gates.

… Verilog Uses …

• Look-ahead SynthesisAlthough some exploratory synthesis will be done early on in the design process, to provide accurate speed and area data to aid in the evaluation of architectural decisions and to check the engineer's understanding of how the Verilog will be synthesized, the main synthesis production run is deferred until functional simulation is complete. It is pointless to invest a lot of time and effort in synthesis until the functionality of the design is validated.

Levels of Abstraction …

• Verilog descriptions can span multiple levels of abstraction i.e. levels of detail, and can be used for different purposes at various stages in the design process.

… Levels of Abstraction • At the highest level, Verilog contains stochastical functions (queues and

random probability distributions) to support performance modelling.• Verilog supports abstract behavioural modeling, so can be used to model

the functionality of a system at a high level of abstraction. This is useful at the system analysis and partitioning stage.

• Verilog supports Register Transfer Level descriptions, which are used for the detailed design of digital circuits. Synthesis tools transform RTL descriptions to gate level.

• Verilog supports gate and switch level descriptions, used for the verification of digital designs, including gate and switch level logic simulation, static and dynamic timing analysis, testability analysis and fault grading.

• Verilog is used to describe simulation environments; test vectors, expected results, results comparison and analysis.

• Verilog can be used to control simulation e.g. setting breakpoints, taking checkpoints, restarting from time 0, tracing waveforms.

Scope of Verilog

• The diagram shows a simplified view of the electronic system design process incorporating Verilog. The central portion of the diagram shows the parts of the design process which will be impacted by Verilog.

Synthesizing Verilog

• Synthesis in the context of this course refers to generating random logic structures from Verilogdescriptions.

• There are currently three kinds of synthesis:– behavioural synthesis – high-level synthesis – RTL synthesis

An Example Design

• A design is described in Verilog using the concept of a module.

• A module can be thought of as two parts:– the port declarations– the module body.

• The port declarations represent the external interface to the module.

• The module body represents the internal description of the module - its behaviour, its structure, or a mixture of both.

An and-or-invert (AOI) gate in Verilog

• Describe an and-or-invert (AOI) gate in Verilog:

// Verilog code for AND-OR-INVERT gate

module AOI (A, B, C, D, F);

input A, B, C, D;

output F;

assign F = ~((A & B) | (C & D));

endmodule

// end of Verilog code

Understanding the Code …

• // Verilog code for AND-OR-INVERT gateSimilar to many programming languages, Verilogsupports comments. There are two types of comment in Verilog, line comments and block comments.

• Comments are not part of the Verilog design, but allow the user to make notes referring to the Verilog code, usually as an aid to understanding it.

• Two forward slashes mark the start of a line comment, which is ignored by the Verilog compiler. A line comment can be on a separate line or at the end of a line of Verilog code, but in any case stops at the end of the line.

… Understanding the Code …

• module AOI (A, B, C, D, F);The name of the module is just an arbitrary label invented by the user. It does not correspond to a name pre-defined in a Verilog component library. module is a Verilog keyword. This line defines the start of a new Verilog module definition. All of the input and output ports of the module must appear in parentheses after the module name. The ordering of ports is not important for the module definition per se, although it is conventional to specify input ports first.

… Understanding the Code …

• input A, B, C, D;output F;The port declarations must repeat the names of the ports in the module header. A port may correspond to a pin on an IC, an edge connector on a board, or any logical channel of communication with a block of hardware. Each port declaration includes the name of one or more ports ( e.g., A, B ), and the direction that information is allowed to flow through the ports (input, output or inout).

… Understanding the Code …

• endmoduleThe module definition is terminated by the Verilog keyword endmodule.

… Understanding the Code …• assign F = ~((A & B) | (C & D));

all the names referenced in this statement are the ports of the design.

• Because all of the names used in the module body are declared inthe module header and port declarations, there are no further declarations for internal elements required in the module body.

• assign is a Verilog keyword. It denotes a concurrent continuous assignment, which describes the functionality of the module. Theconcurrent assignment executes whenever one of the four ports A,B, C or D change value.

• The ~, & and | symbols represent the bit-wise not, and and oroperators respectively, which are built in to the Verilog language.

Verilog Logic Values

• Verilog Logic Values• The underlying data representation allows for any bit to

have one of four values– 1, 0, x (unknown), z (high impedance)– x — one of: 1, 0, z, or in the state of change– z — the high impedance output of a tri-state gate.

• What physical basis do these have?– 0, 1 ... For example Vdd and GND– z ... A tri-state gate drives either a zero or one on its output. If it's

not doing that, its output is high impedance (z). Tri-state gates are real devices and z is a real electrical affect.

– x ... not a real value. There is no real gate that drives an x on to a wire, x is used as a debugging aid.

“Wires” In Verilog

• A Verilog wire represents an electrical connection. A wire declaration looks like a port declaration, with a type (wire), an optional vector width and a name or list of names.

• Ports default to being wires, so the definition of wire F in the Verilog code is optional.

Example Code with Wires• // Verilog code for AND-OR-INVERT gate

• module AOI (A, B, C, D, F);• input A, B, C, D;• output F;

• wire F; // the default

• wire AB, CD, O; // necessary

• assign AB = A & B;• assign CD = C & D;• assign O = AB | CD;• assign F = ~O;

• endmodule

• // end of Verilog code

Explanation of the Codewire AB, CD, O;This is the syntax for a wire declaration. You can create separate wire declarations if you wish, for example:wire AB, CD;wire O;is an alternative way of creating wire declarations.assign AB = A & B;assign CD = C & D;assign O = AB | CD;assign F = ~O;In this module body, there are four continuous assignment statements. These statements are independent and executed concurrently. They are not necessarily executed in the order in which they are written. This does not affect the functionality of the design. Suppose B changes value. This causes assign AB = A & B; to be evaluated. If AB changes as a result then assign O = AB | CD; is evaluated. If O changes value then assign F = ~O; will be evaluated; possibly the output of the module will change due to a change on B.

Design Hierarchy

• Modules can reference other modules to form a hierarchy. Here we see a 2:1 multiplexer with an inverting data path consisting of an AOI gate and a pair of inverters.

Example of Design Hierarchy• // Verilog code for 2-input multiplexer

• module INV (A, F); // An inverter• input A; • output F; •• assign F = ~A;• endmodule

• module AOI (A, B, C, D, F);• input A, B, C, D;• output F;

• assign F = ~((A & B) | (C & D));

• endmodule

• module MUX2 (SEL, A, B, F); // 2:1 multiplexer• input SEL, A, B; • output F; •• // wires SELB and FB are implicit •• // Module instances... •• INV G1 (SEL, SELB); • AOI G2 (SELB, A, SEL, B, FB); • INV G3 (.A(FB), .F(F)); // Named mapping• endmodule

• // end of Verilog code

Invokes the modules.