verification of 1 m+ transistors mixed signal ic presentation

Verification of 1M+ transistors Mixed-Signal ICs for Cellular and Multimedia Player Applications

Session # 2

Régis Santonja

Table Of Contents

• Introduction

• IC feature set and complexity overview

• The Verification Environment

• Database Management and Version Control

• Speeding the simulations up

• Sanity checks

• Tracking the coverage

• Regression Testing

• Conclusion

• Future improvements

• The Verification Team

• High complexity of today’s Mixed-Signal Integrated Circuits (ICs)

�Functionality

• More than 1 million transistors (half analog / half digital)

• Increasing costs of wafers

�Need to find new ways to guarantee IC quality before tape-out

�Signal Integrity

�Current consumption

Introduction

IC feature set and complexity overview

• 2 multi-mode buck switchers with DVS

• 20V adaptive Boost

• 10 LDOs, 4 GPOs

• Batt/Licell charger

• 10 bits GP ADC

• Serial WLED

• RGB LED drivers

• Dual 14 bits ADC

• 14/16 bits combo DAC

• Class AB speaker handset

• Class D loudspeaker

• Mic amps (handset/headset)

• USB path audio (CEA936)

• SPI/I2C and SSI digital interfaces

• USB 2.0 PHY (OTG); ULPI and serial carkit

• 32Khz crystal oscillator and RTC

• Secure RTC supply and reference support

Chip-level Verification Environment

• Vertical reuse

– chip-level testbench is reusing resources from block-level testbenches

– Same Vector file

• SPI/I2C transactor generates the actual SPI/I2C protocol

• Full IC instantiated

• Every IC port matches its counterpart on the Stimulus/Checker block

miscellaneous

transactor

which may be

added in future

SPI /I2C

transactor

Optional

secondary

SPI/I2C

transactor

Vector file (VAMS)

contains calls to the transactors.

Also has stimulus and checkers

for remainder of test

initial begin

end // initial

always @

analog begin

end // analog

Supplies/Grounds

and other analog

Optional

secondary

transactor

(ULPI)

transactor

SPI/I2C pins

SPI map files

Environment defines

Environment Tasks

Waveforms

Stimulus/Checker (VAMS)

BCL/FS/RX/TX

Optional assertions

Stimulus and Checker module (VAMS)

• Built as soon as the pad list of the IC is defined

• Used throughout the whole project development

• Used by the whole design & verification team to exercise each block individually, at different levels

• The Verilog-AMS Stimulus/Checker module enables communication with the IC via its interfaces

– SPI, I2C, I2S, ULPI (USB) transactors

– General Purpose IOs

– Analog pins

• Assertions can be included

Vector File Example

DIGITAL SECTION

• Bring up supplies

• Wait for RESETB

• Check Interrupt pin

• Read revision ID from SPI

• End simulation and dump PASS/FAIL status to log file

ANALOG SECTION

• Generic

• Vector-specific

/********************* DIGITAL EXECUTABLE **************************/

initial begin

// Initial Condition:

BP_level = 0;

LICELL_level = 0;

SPIVCC_level = 0;

#(10*`nano_in_usec);

LICELL_level = 2.5;

#(500*`nano_in_usec);

BP_level = 3.6;

SPIVCC_level = 2.775;

COMMENT("********** WAIT FOR RESETB HIGH **********");

@(cross(V(RESETB)-SPIVCC_level/2, +1, 1n, 10u));

wdi = 1;

COMMENT("********** CHECK INT PIN IS HIGH **********");

check_digital_net_id(" INT pin high check", `IC.INT, 1'b1);

COMMENT("********** READING FIN, ICID AND REV BITS **********");

spi_icid_fld = 3'b111;

spi_rev_fld = 5'b01_000; // 1.0

spi_read_fields1(SPI_ID_REG_ADR, 24'hff_ff_ff);

COMMENT("*****READING ICID DUPLICATE **********");

spi_icid_adc3_fld = spi_icid_fld;

spi_read_fields1(fnGetAddr("spi_icid_adc3_fld"), spi_icid_adc3_mask);

COMMENT("********** ALL TESTS COMPLETED **********");

END_SIM;

/********************* ANALOG EXECUTABLE **************************/

analog begin

// Generic analog section

`include "generic_analog.v"

// vector-specific analog section

// …

Vector File Example – Generic analog section

• Contains all external components

– Capacitors

– Crystal model

– Microphone model

• Digitally controlled external supplies

• Can be VAMS syntax or “spice” netlist

//*******************************************************************

// Main Supplies

V(BP_stim) <+ transition(BP_level, 0, BP_rise, BP_fall);

I(BP, BP_stim) <+ V(BP, BP_stim)/RBP;

//*******************************************************************

// External Capacitors

I(REGULATOR1) <+ 1e-6 * ddt(V(REGULATOR1));

I(REGULATOR2) <+ 1e-6 * ddt(V(REGULATOR2));

I(BANDGAP) <+ 100e-9 * ddt(V(BANDGAP));

//*******************************************************************

// GROUNDS

V( GND1) <+ 0.0;

V( GND2) <+ 0.0;

V( GND3) <+ 0.0; // ...

Generic Vector Files

• Some generic vector files have been developed to address common tests across several ICs

– Regulators

– Audio (I2s interfaces, TX/RX paths routing, a/d & d/a converters)

• Easily plugged in any project-specific testbench

• Generic block names, pin names, controls, etc… made specific via a specific “define” file.

Log file Example

• Can trace what happened during the simulation

• PASS/FAIL statistics reported when simulation ends

% INFO @ 0 ns: ***************************************************

% INFO @ 0 ns: RUNNING SIMULATION common_topctrl_revid.vams

% INFO @ 0 ns: ***************************************************

% INFO @ 510000 ns: ********** WAIT FOR RESETB HIGH **********

% INFO @ 41229624 ns: ********** CHECK INT PIN IS HIGH **********

% PASS # 2 @ 41229624 ns: INT pin high check: correct digital value

% INFO @ 41229624 ns: ****** READING FIN, ICID AND REV BITS ********

% PASS # 3 @ 41230878 ns: PASS: SPI Reg. 7 Read Check PASS.

% INFO @ 41230878 ns: ****** READING ICID DUPLICATE******

% PASS # 4 @ 41232132 ns: PASS: SPI Reg. 46 Read Check PASS.

% INFO @ 51232132 ns: ********** ALL TESTS COMPLETED **********

% -----------------------------------------

% Simulation common_topctrl_revid.vams Completed Successfully

% END_SIM called @ Time = 51232632

% 4 Checks done

% 4 Checks successful

% 0 Checks failed

% -----------------------------------------

Database Management and Version Control

• Multi-site teams spread all over the world

• Massive mix between reuse, re-work and custom developments

• Rigorous methodology required to handle design & verification database

Block release : tagging methodology

• Reliable release of hierarchical blocks

• Despite all sub-blocks having heterogeneous revision numbers

• Tag all block’s hierarchy

• Ensures consistency of the block release : passes hierarchical ERC (“check&save”)

• The chip top-level is built as a collection of block tags.

Verification Environment

Top-cell

Topblock_X

V2.8 Topblock_Y

Topblock_Z

X_topblock_X.03

X_topblock_Y.05

X_topblock_Z.08

X_topcell.06

X_VE.12

Verification Environment release

• The Verification Environment (VE) is also tagged

• The global collection of tags is released (CCF file)

• The verification engineer creates a new consistent work area

Verification Engineer

#1 work area

Topblock_X X_topblock_X.03

Topblock_Y X_topblock_Y.05

Topblock_Z X_topblock_Z.08

Top-Cell X_topcell.06

Verification

Environment X_VE.12

CCF file

Speeding Simulations up

Ultra-amsAccuracy

Mixed-levelSpeedBig non-linear analog blocks

(audio converters, switchers,

etc…)

SpectreFull accuracySmall linear analog blocks

Simulation methodRequirementAnalog block

• Trade-off between simulation speed and accuracy

• Mixed-level simulation : mixing transistors and models together

Mixed-level Simulations – 1/2

• Allow system simulations early in the development process

• All models must be pin accurate

�Match the expected voltage levels

�Match the expected drive strength

�Etc…

• The models should be reviewed with the designers

�No essential functionality missing or badly modeled

� Improves communication between design and verification members

Mixed-level Simulations – 2/2

• Completed blocks can be selected at transistor-level

• Surrounding blocks can be left as models

• If undesired interaction are likely to occur between blocks, keep them all at transistor-level

• Stub views are empty placeholders

Digital model

RTL/GATES

VAMSVAMS

Multiple Supplies

• Typical to Power-Management ICs is to have internal supply voltages generated by an on-chip voltage regulator

• Digital runs at low voltage (i.e. 1.5 Volts)

• Some analog blocks require higher voltages (i.e. 2.8 Volts)

Switched Cap

Digital

Block_x Block_y

Block_zVCORE

Internal voltage

regulator

Internal blocks supplied off the on-

chip voltage regulator

Multiple Supplies and Connect Modules

• Cadence Block-based Discipline Resolution (BDR)

• Multiple discipline declaration in the digital domain

• Explicitly associate appropriate instances, cells, or terminals with the appropriate discipline

• Supply-sensitive connect modules not used because they require Cadence-specific syntax on digital blocks (including standard cells)

Analog

(1.5V)

Analog

(2.8V)

VAMS model

Level-shifter

Digital

digital

CM : Connect Module

Example of mixed-level simulation speed up techniques

• Phase Locked Loop (PLL)

– High frequency signals made digital

– 100x simulation

• Used with switched cap audio codec and 16 bits stereo DAC

• Tens of sine periods could be simulated, allowing SNR calculation

pllout

Divider

digital

digitalanalog

digital

Charge

Loop Filter

Phase Detector

• Non-Overlapping Clocks

– Required for all switched cap blocks

– All clock lines must be kept digital

– RTL not appropriate (delays required)

�Digital model with delays

�Gate-level + back-annotation

– 100+x simulation speed

• Switched Capacitors– Commonly used for high

performance audio converters

– 14 bits voice codec

– 16 bits stereo DAC

• Analog simulation very slow due to analog clock phases�Replace switches with AMS

�Keep clock lines digital

� 100x simulation speed

φ1 φ2

Full-transistor simulations

Tighten options for sensitive blocks .usim_opt speed=3 sim_mode=a #< cell name>

Remove standard cells’ antenna diodes.usim_opt dcut=1 #<standard cell names>

Remove small resistors.usim_optrshort=1.01 #<block name>

Disables Dynamic Paritionning.usim_opt dyn_part=0

Aggressive partitioning.usim_opt analog=0

Aggressive speed.usim_opt speed=8

Global sim_mode set to digital fast.usim_top sim_mode=df

CommentsUltrasim options

• No proof that an analog model matches the circuit behavior

• Full-transistor simulations still required

• Selected set of

functionalities tested

• Ultra-AMS used with

Ultrasim “fast-spice” solver

Full-transistor simulations – 1M+ transistors

Aggressive partitioning on digital blocks.usim_opt analog=0 #<digital cell name>

Set digital blocks to digital-accurate. A digital-fast (df) option

is functional but too loose for accurate current consumption

estimation. The global sim_mode is left to the default mixed-

signal (ms) mode.

z.usim_opt sim_mode=da #<digital cell name>

Set speed=2 on all standard cells. A speed=8 is functional but

too loose for accurate current consumption estimation. The

global speed is left to its default value=5.

.usim_opt speed=2 #<digital cell name>

Remove standard cells’ antenna diodes .usim_opt dcut=1 #<all standard cells names>

Print all cut nodes into a file..usim_opt nodecut_file=1

Print all cut elements into a file..usim_opt elemcut_file=1

Remove small inductances on both signal and power nets..usim_opt lshort=1e-3 lvshort=1e-3

Remove small resistors on both signal and power nets..usim_opt rshort=1.01 rvshort=1.01

• Seeking undesired leakages

• Global current consumption

• Replacing Stimulus/Checker Verilog-AMS with spectre view to avoid connect modules that lead to unreliable current estimations

• Be as close as possible to the application

Full-transistor simulations – 1M+ transistors

Non linear analog current and charge model for all MOSFET

devices.

.usim_opt mos_method=a

Higher voltage used for df or da models calculation..usim_opt vdd=3.0

Report the 100 most unstable nodes during DC calculation into

a .dcr file.

.usim_opt dc_rpt_num=100

The simulator extends the DC calculation until a stable

operating point is reached. This disables the default 3 hour time

limit, and the maximum DC event limit.

.usim_opr dc_prolong=1

Complete operating point calculation using pseudo-transient

algorithm.

.usim_opt dc=1

Saving voltages to waveform.probe v(<hierarchical node name>)

Saving currents to waveform.

CAUTION : current probing increases the size of the partitions.

It is preferred to run several successive simulations with a

limited number of current probes.

.probe x(<hierarchical node name>)

VR option used for internally generated supplies.usim_vr block=#<regulator cell name> node=<hierarchical

path to supply node>

• Carefully read the simulator’s log file

� Bad partitioning ?

� Remaining Verilog-A modules ?

Floating nodes

• Increasing number of mobile features (Hi-Res screens,

Bluetooth, WiFi, still and video camera,…)

• Acceptable battery life requirement

�Power gating : turning off some supplies on the IC

• Unfortunately, such techniques often result in unknown states or floating nodes

• Cannot be detected with traditional transient simulation

Floating node

�Each node impedance compared to a threshold

�Some nodes can be

voluntarily high impedance in

case of switched cap topologies

Tracking the Coverage : the Verification Matrix

• All specification items reported into an Excel matrix

• Main focus on functionality but some performance items are also tracked

• Several thousands of items for a typical Power-Management IC

• Each item associated with its test condition, priority-level, Cadence configuration and vector file and whether it is to be verified at block or chip-level

• Reviewed with designers

• Can be shared between several ICs of the same family

• Gathers each covered item into a coverage statistics page

Regression Testing

• Need to make sure the final database sent to fabrication is still compliant with previous simulation results

�Re-run all simulations just before tape-out

• Two pre-requisites for regression testing

• All tests must be self-checking

• Simulations must be able to start from the command line

• A script (wrapper) builds the appropriate option list of the ‘amsdesigner’ command

• Each simulation runs in a specific run-directory so that multiple tests can be run in parallel

• Simulations dispatched to a compute server farm

Regression log parser and automatic report

• Tens of simulations

• Each of them testing tens or hundreds of

specification items

�Need to have a quick picture of the overall results

�Automatic log parser and report

Regis submitted the regression at Wed Mar 12 18:45:34 CET 2008

Workarea used was X_top_verification.07

Logfiles can be found in $WORKAREA/top_verification/logfiles

TEST NAME CONFIG NAME BCS TYP WORST LOGFILE

----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

charger_batfet config_charger_batfet N/A NOT_RUN N/A [...]

gpadc config_gpadc N/A NCELAB N/A

gpo1 config_gpo1 N/A NOT_RUN N/A

pll config_pll N/A NOT_RUN N/A

startup config_startup N/A NOT_RUN N/A

tcled config_tcled N/A NCELAB N/A

topctrl_fsm config_topctrl N/A NOT_RUN N/A

topctrl_i2c config_topctrl N/A VNE N/A

topctrl_revid config_topctrl PASS PASS PASS

vcam config_vcam N/A NCELAB N/A

vdig config_vdig N/A FAIL N/A

viohi config_viohi N/A FAIL N/A

vpll config_vpll N/A FAIL N/A

vgen1 config_vgen1 N/A NCELAB N/A

vsd config_vsd N/A NCELAB N/A

sw1 config_sw1 N/A FAIL N/A

sw2 config_sw2 N/A FAIL N/A

backlight config_backlight N/A NCELAB N/A

N/A: The test was not in the regression for this mode

NOT_RUN: Logfile was not found.

ANE: Analog netlist error.

VNE: Verilog netlist error, check the log file for *E

NCELAB: Elaboration Error, check your config

RUNNING: Job is either still running, or it may have been terminated early

RUNERR: Job started running, but found a *E with no PASS/FAIL indication.

NOT_SC: Not self checking, simulation seemed to complete, but END_TEST was never called

NOCFG: Cadence couldn't find the config, likely caused by a machine with automount problems

UNKNOWN: Status could not be determined from log file

FAIL: Test finished with Errors

PASS: Test pass, yay!!!

Catagory Total(%) BCS(%) TYP(%) WCS(%)

---------------------------------------------------------------------------------------------------------------------------------------------

Number tests in regression 66(100.00%) 2(100.00%) 62(100.00%) 2(100.00%)

Number Tests submitted 36( 54.55%) 2(100.00%) 32( 51.61%) 2(100.00%)

NOT_RUN 30( 45.45%) 0( 0.00%) 30( 48.39%) 0( 0.00%)

ANE: 0( 0.00%) 0( 0.00%) 0( 0.00%) 0( 0.00%)

VNE: 6( 9.09%) 0( 0.00%) 6( 9.68%) 0( 0.00%)

NCELAB: 15( 22.73%) 0( 0.00%) 15( 24.19%) 0( 0.00%)

RUNNING: 0( 0.00%) 0( 0.00%) 0( 0.00%) 0( 0.00%)

RUNERR: 0( 0.00%) 0( 0.00%) 0( 0.00%) 0( 0.00%)

NOT_SC: 0( 0.00%) 0( 0.00%) 0( 0.00%) 0( 0.00%)

NOCFG: 0( 0.00%) 0( 0.00%) 0( 0.00%) 0( 0.00%)

UNKNOWN: 0( 0.00%) 0( 0.00%) 0( 0.00%) 0( 0.00%)

FAIL: 9( 13.64%) 0( 0.00%) 9( 14.52%) 0( 0.00%)

PASS: 6( 9.09%) 2(100.00%) 2( 3.23%) 2(100.00%)

Conclusion

• Since 2003, we’ve been able to successfully verify a complete Power-

Management IC family of up to 1 million transistors, and more.

• The approach described allowed us to find critical bugs before tape-out and to get a very high level of IC functionality on first silicon.

• This has been a very strong requirement for fast platform’s software

integration.

• In the mean time we also proved the effectiveness of the IC modifications

due to specification changes.

• Overall, we reduced significantly our time-to-market and development

costs.

Future Improvements

• SystemVerilog-AMS and AMS assertions

• Automatic result collection with functional coverage

• Pseudo random (constrained) stimulus generation

• Formal proof of analog models

The Verification Team

• The content of this presentation is the result of a collective work that has taken place for several years at Freescale.

• Main contributors are :

– Ana Ferreira-Noullet, Jean-Claude Mboli and Régis Santonja from the Power-Management Verification team at Freescale Toulouse (France),

– Thierry Nouguier from our Toulouse CAD support team,

– Bill Getka and Mike Doll, digital and verification engineers at Freescale Libertyville (USA).

– Cadence support

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Incisive, Invisible Specman, IP Gallery, InstallScape, Nano Encounter, NanoRoute, NC-Verilog, NeoCell, NeoCircuit, Neo Circuit-RF, NeoIP, OpenBook, OrCAD, OrCAD Capture, OrCAD Layout, Palladium, Pearl, PowerSuite, PSpice, SignalStorm, Silicon Design Chain, Silicon Ensemble, Silicon Express, SKILL,

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Advisor, Verilog, Virtuoso, VoltageStorm, and Xtreme are either registered trademarks or trademarks of Cadence Design Systems, Inc.All others are the property of their respective holders.

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