unit 14 - national chiao tung university
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UNIT 14DERIVATION OF STATE GRAPHS AND TABLES
Spring 2011
© Iris H.-R. Jiang
Derivation of State Graphs and Tables
Contents Case studies: sequence detectors Guidelines for construction of state graphs Serial data code conversion Alphanumeric state graph notation
Reading Unit 14
Derivation of state graphs & tables
2
Basic unitUnit 11: Latch & FFs
Simple sequential CktUnit 12: Registers & Counters
Complex sequential CktUnits 13-15: FSM
Put it all togetherUnit 16: Summary
© Iris H.-R. Jiang
Designing a Sequential Circuit
Given the specification of a sequential circuit Design procedure:
1. Construct a state table or state graph (Unit 14)2. Simplify (Unit 15)3. Derive FF input equations and output equations (Unit 12)
Derivation of state graphs & tables
3
Basic unitUnit 11: Latch & FFs
Simple sequential CktUnit 12: Registers & Counters
Complex sequential CktUnits 13-15: FSM
Put it all togetherUnit 16: Summary
Sequence Detectors4
Derivation of state graphs & tables
© Iris H.-R. Jiang
Case I (1/2)
Examine groups of 4 consecutive inputs & produce an output Reset after every 4 inputs
e.g., X = 0101 0010 1001 0100Z = 0001 0000 0001 0000
Observation:
Typical sequence Partial state graph
Derivation of state graphs & tables
5
01011001
DetectorX Z
Clock0/0
S0
S1
S3
1/0
S2
0/0
1/0
S4
0/0
1/1
X = 0101X = 1001
Input/output
© Iris H.-R. Jiang
Case I (2/2)
Complete state graph
Derivation of state graphs & tables
6
0/0
S0
S1
S3
1/0S2
0/0
1/0
S4
0/0
1/1
S5
0/0
S6
0/0
1/00/0 0/0
1/0
1/01/0
© Iris H.-R. Jiang
Case II (1/4)
Examine groups of 3 consecutive inputs & produce an output No reset
e.g., X = 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0Z = 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0
State graph (Mealy) S0: initial, S1: get …1, S2: get …10
Derivation of state graphs & tables
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101Detector
X Z
Clock
S0
S1
0/0
1/0
S2
1/1
0/0
S0
S1
0/0
1/0
S2
1/1
0/0
0/01/0
S0
S1
0/0
1/0
© Iris H.-R. Jiang
Case II (2/4)
State table
Derivation of state graphs & tables
8
X
A+=X'B
1
0
0
00
01
11
10
X
0
1 0
0
X
0
ABX
B+=X
1
0
0
00
01
11
10
X
0
0 1
1
X
1
ABX
Z=XA
1
0
0
00
01
11
10
X
0
0 0
0
X
1
AB
S0
S1
0/0
1/0
S2
1/1
0/0
S0
S1
0/0
1/0
S2
1/1
0/0
0/01/0
S0
S1
0/0
1/0
Present stateS0S1S2
Next stateX = 0 X = 1S0S2S0
S1S1S1
Present outputX = 0 X = 1
000
001 State maps
AB00011011
A+B+
X = 0 X = 1001000XX
010101XX
ZX = 0 X = 1
000X
001X
© Iris H.-R. Jiang
Case II (3/4)
State maps
Realize it
9
CK
A' A
D CK
B' B
D
Clock
X
Z
X
A+=X'B
1
0
0
00
01
11
10
X
0
1 0
0
X
0
ABX
B+=X
1
0
0
00
01
11
10
X
0
0 1
1
X
1
ABX
Z=XA
1
0
0
00
01
11
10
X
0
0 0
0
X
1
AB
Derivation of state graphs & tables
Q: Check by yourselfX = 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0Z = 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 ??
© Iris H.-R. Jiang
Case II (4/4)
Moore? S0: initial, S1: get …1, S2: get …10, S3: get …101
Derivation of state graphs & tables
10
0
1
0
S00
S10
S20
S31
1
0
1
0
S00
S10
S20
S31
1
1
0
1 0
0
1
0
S00
S10
S20
Present stateS0S1S2S3
Next stateX = 0 X = 1S0S2S0S2
S1S1S3S1
Presentoutput
0001
AB00011011
A+B+
X = 0 X = 100100010
01011101
Z0001
© Iris H.-R. Jiang
Case III (1/2)
010 & 1001 detector e.g., X = 0 0 1 0 1 0 0 1 0 0 0 1 0 0 1 1
a b c d e fZ = 0 0 0 1 0 1 0 1 1 0 0 0 1 0 1 0
State assignment
Derivation of state graphs & tables
11 0101001
DetectorX Z
Clock
State for “1001” Complete State for “010”
© Iris H.-R. Jiang
Case III (2/2)
Derivation of state graphs & tables
12
0/0
S0
S1
S3S2
1/00/1
1/0
S4
0/0
1/0b
c
S5
d 0/01/1e
?
0/0
S0
S1
S3S2
1/00/1
1/0a
0/0
S0
S1
S3S2
1/00/1
1/0
S4
0/0
1/0b
c
S5
g
0/01/1
f
1/0
e
h
1/00/0
i
0/0
State for “1001” Complete State for “010”
© Iris H.-R. Jiang
Case IV (1/2)
Specifications Z = 1 if total # of 1’s is odd
andat least two consecutive 0’s have been received
e.g., X = 1 0 1 1 0 0 1 1Z =(0) 0 0 0 0 0 1 0 1
State assignment Initial state and state for 1’s
State for 0’s
Derivation of state graphs & tables
13
Reset or even 1’s
1S00
S101
Odd 1’s
© Iris H.-R. Jiang
Case IV (2/2)
State graph14
Reset or even 1’s
1S00
S101
Odd 1’s
1S00
S101
S30
S41
S20
1
1a
0
0
1S00
S101
S30
S41
S20
1
1
b
0
0
S50
0
0
c g
de
f
Even 1’s Odd 1’s
0 0
11
Initial state and state for 1’s
Derivation of state graphs & tables
Guidelines for State Graph Construction15
Derivation of state graphs & tables
© Iris H.-R. Jiang
Guidelines for State Graphs Construction
Steps1. Construct sample sequences to help you understand the
problem2. Determine under what conditions it should reset3. If only one or two sequences leads to a nonzero output,
construct a partial state graph Another way, determine what sequences or groups of
sequences must be remembered by the circuit and set up states accordingly
4. Each time you add an arrow to the state graph, determine whether it can go to one of the previously defined states or whether a new state must added
5. Check your graph to make sure there is one and only one path leaving each state for each combination of values of the input variables
6. When your graph is complete, verify it by applying the input sequences formulated in step 1
Derivation of state graphs & tables
16
Serial Data Code Conversion17
Derivation of state graphs & tables
© Iris H.-R. Jiang
Serial Data Transmission
Coding schemes
Derivation of state graphs & tables
18
Receiver
Serial Data
Clock
Clock Recovery
Circuit
Transmitter Receiver
Serial Data
Clock
Bit Sequence
NRZ
NRZI
RZ
Manchester
Clock
0 1 1 1 0 0 1 0
1 bittime
Use 2 cables (not good)
NRZ: Non-return-to-zeroNRZI: Non-return-to-zero-invertedRZ: Return-to-zero
0 ⇒ 0; 1⇒ 1
0 ⇒ d-; 1⇒ ~d-
0 ⇒ 0; 1⇒ 10
0 ⇒ 01; 1⇒ 10
Transmitter
© Iris H.-R. Jiang
Mealy?
Mealy: Output depends on Current state (synchronous) Input (maybe asynchronous)
Fewer states
Derivation of state graphs & tables
19
ConversionNetwork
ZManchester data
NRZ data
Clock2
X
S0
S1S2
1/1
1/0 0/1
0/0
Present stateS0S1S2
Next stateX = 0 X = 1S1S0-
S2-S0
output (Z)X = 0 X = 1
01-
1-0
NRZ (X)
Manchester(ideal)
Clock2
State
Z (Actual)
1 clock period
S0 S1 S0 S2 S0 S2 S0 S2 S0 S1 S0 S1 S0 S2 S0 S1
0 1 1 0 1 0 1 0 0 1 0 1 1 0 0 1
0 0 1 1 1 1 1 1 0 0 0 0 1 1 0 0
Glitch: false output
Bit sequence 0 1 1 1 0 0 1 0
NRZ: combintaion of double 0’s & double 1’sStarting state: S0
© Iris H.-R. Jiang
Moore?
Moore: Output only depends on Current state (synchronous)
More states (in general) 1 clock period delay
Derivation of state graphs & tables
20
Clock2
State
Z
X (NRZ)
1 clock period
S0 S1 S2 S3 S0 S3 S0 S3 S0 S1 S2 S1 S2 S3 S0 S1
0 0 1 1 1 1 1 1 0 0 0 0 1 1 0 0
0 0 1 1 0 1 0 1 0 0 1 0 1 1 0 0
S31
S21
S00
0
1
1
S10
1 0 0
Present stateS0S1S2S3
Next stateX = 0 X = 1S1S2S1-
S3-S3S0
Presentoutput (Z)
0011
ConversionNetwork
ZManchester data
NRZ data
Clock2
X
Starting states: S0, S2
Alphanumeric State Graph Notation21
Derivation of state graphs & tables
© Iris H.-R. Jiang
Alphanumeric State Graph Notation
When a sequential circuit has several inputs, label the state graph arcs with alphanumeric input variable names instead of 0’s and 1’s e.g., 2 inputs: F: forward, R: reverse Decide priority. E.g. F has higher priority
than R
Derivation of state graphs & tables
22
S0Z1
R
S2Z3
S1Z2
R
R
F
FF
Incomplete
S0Z1
F'R
S2Z3
S1Z2
F'R
F'R
F
FF
F'R'F'R'
F'R'
Present stateS0S1S2
Next stateFR = 00 01 10 11
S0 S2 S1 S1S1 S0 S2 S2S2 S1 S0 S0
OutputZ1Z2Z3
1 0 00 1 00 0 1
© Iris H.-R. Jiang
Complete?
Completely specified state graph OR together all input labels on arcs emanating from a state, the
result can reduce to 1 Cover all conditions: F + F'R +F'R' = F + F' = 1
AND together any pair of input labels on arcs emanating from a state, the result can reduce to 0 Only one arc is valid: F·F'R = 0, F·F'R' = 0, F'R·F'R' = 0
Notation in state graph X1X'4/Z2Z3 ≡ 1--0/0110 -/Z1 ≡ ----/1000 For any combination of input values…
Derivation of state graphs & tables
23
S0Z1
F'R
S2Z3
S1Z2
F'R
F'R
F
FF
F'R'F'R'
F'R'
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