towards a sub-2.5v, 100-gb/s serial transceiversorinv/papers/sv_cicc07_slides.pdfsorin voinigescu et...
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Sorin Voinigescu et al., CICC-2007, September 18th, 2007 1
Towards a sub-2.5V, 100-Gb/s Serial TransceiverTowards a sub-2.5V, 100-Gb/s Serial Transceiver
S.P. Voinigescu1, R. Aroca1, T.O. Dickson1, S.T. Nicolson1, T. Chalvatzis1, P. Chevalier2 , P. Garcia2 , C. Garnier2 , and
B. Sautreuil2
1) University of Toronto, 2) STMicroelectronics
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 2
OutlineOutline
100GE fundamentals
Design methodology
Schematic level approach
Layout
90-Gb/s half-rate transceiver
100-Gb/s full-rate transceiver blocks
Round-up
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 4
Network traffic growth (Network traffic growth (from IEEE802.3 HSSGfrom IEEE802.3 HSSG))
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 5
Network traffic growth (Network traffic growth (from IEEE802.3 HSSGfrom IEEE802.3 HSSG))
Technological breakthrough demands a leap in serial data rate
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 6
What are the applications?What are the applications?
Those that have demonstrated the need for bandwidth beyond existing
capabilities:
High performance computing
Video-on-demand delivery
Data center
Internet exchanges
Metro: over 40km of SMF
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 7
What are the applications?What are the applications?
Those that have demonstrated the need for bandwidth beyond existing
capabilities:
High performance computing
Video-on-demand delivery
Data center
Internet exchanges
Metro: over 40km of SMF
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 8
Possible system architectures Possible system architectures (R.H. Derksen et al. CSICS-07) (R.H. Derksen et al. CSICS-07)
107Gb/s serial OOK
Optical modulator not available
OK now over 10m of coaxial cable
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 9
Possible system architectures Possible system architectures (R.H. Derksen et al. CSICS-07) (R.H. Derksen et al. CSICS-07)
107Gb/s serial OOK
Optical modulator not available
OK now over 10m of coaxial cable
54GBaud/s= 2*54Gb/s RZ-DQPSK
More power, still fast electronics
Optics OK
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 10
Possible system architectures Possible system architectures (R.H. Derksen et al. CSICS-07) (R.H. Derksen et al. CSICS-07)
107Gb/s serial OOK
Optical modulator not available
OK now over 10m of coaxial cable
54GBaud/s= 2*54Gb/s RZ-DQPSK
More power, still fast electronics
Optics OK
27GBaud/s = 4*(27Gb/s) Polarization
Multiplex QPSK
4x 5-6bit, 54GS/s ADCs and DSP
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 11
100-Gb/s Serial Transceiver100-Gb/s Serial Transceiver
should consume lesspower and cost less than100 Gb/s 5 x 10 Gb/s
2 x 40 Gb/s
10-GE CMOS transceiver
0.8W from 1.2 V and < $50
3W, $250
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 12
100-Gb/s Serial Transceiver100-Gb/s Serial Transceiver
should consume lesspower and cost less than100 Gb/s 5 x 10 Gb/s
2 x 40 Gb/s
10-GE CMOS transceiver
0.8W from 1.2 V and < $50
40+ Gb/s SiGe-HBT ICs too power
hungry and 3.3V supply
3W, $250
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 13
100-Gb/s Serial Transceiver100-Gb/s Serial Transceiver
should consume lesspower and cost less than100 Gb/s 5 x 10 Gb/s
2 x 40 Gb/s
10-GE CMOS transceiver
0.8W from 1.2 V and < $50
40+ Gb/s SiGe-HBT ICs too power
hungry and 3.3V supply
Need lower supply logic with fewer
and lower tail currents per gate
3W, $250
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 14
What are the options?What are the options?
Low-voltage (sub-2.5V) BiCMOS logic with 300-GHz HBTs
1.2V 45-nm GP CMOS CML logic without current source
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 15
65-nm LP n-MOS vs. SiGe HBT65-nm LP n-MOS vs. SiGe HBT
Comparable high frequency performanceOnly difference: g
m/I (Gain/I), V
swing => HBT wins in
dynamic range = length of data link
[P. Chevalier et al. CSICS-2006]
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 16
GP vs. LP 65-nm CMOSGP vs. LP 65-nm CMOS
GP 30% faster than LP and
300mV lower VGS => lower
power!
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 17
GP vs. LP 65-nm CMOSGP vs. LP 65-nm CMOS
GP 30% faster than LP and
300mV lower VGS => lower
power!
Peak fT at 0.3 to 0.35mA/µm
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 18
GP vs. LP 65-nm CMOSGP vs. LP 65-nm CMOS
GP 30% faster than LP and
300mV lower VGS => lower
power!
Peak fT at 0.3 to 0.35mA/µm
VT variation is large but
mostly irrelevant
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 19
GP vs. LP 65-nm CMOSGP vs. LP 65-nm CMOS
GP 30% faster than LP and
300mV lower VGS => lower
power!
Peak fT at 0.3 to 0.35mA/µm
VT variation is large but
mostly irrelevant
fT and f
MAX increase with V
DS
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 20
FET/HBT small-signal circuit including degenerationFET/HBT small-signal circuit including degeneration
Rs(RE) included in RG(B), gmeff, goeff, fT and Cgseff/Cbeeff
Zin≅ Rg+Rs – jfT/(fgmeff); gmeff = g
m/(1+g
mR
S)
In 300-GHz SiGe HBTs gmR
E = 3.5 => built-in feedback, stable over T
gmeff
VIN V
IN C
gs(be)eff
Cgd(bc)
Cdb(cs)
RG(B)
goeff
G(B)
S(E)
D(C)
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 21
2-MOSFET stack topologies 2-MOSFET stack topologies (S. Voinigescu et al. CICC-05)(S. Voinigescu et al. CICC-05)
Need VDS
> 0.5 V to operate at 40+ Gb/s => remove current source
CLK_P
VDD
(1.5V)
CLK_N
VG
OUT_P
OUT_N
DATA_P
DATA_N
M1 M2
M3 M6M4 M5
ITAIL
0.2V
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 22
2-MOSFET stack topologies 2-MOSFET stack topologies (S. Voinigescu et al. CICC-05)(S. Voinigescu et al. CICC-05)
Need VDS
> 0.5 V to operate at 40+ Gb/s => remove current source
VGS
of data FETs determines VDS
of clock FETs => LVT + HVT
CLK_P
VDD
(1.5V)
CLK_N
VG
OUT_P
OUT_N
DATA_P
DATA_N
M1 M2
M3 M6M4 M5
ITAIL
0.2V
DATA_P
CLK_P
DATA_N
CLK_N
OUT_N
OUT_P
IBIAS
IBIAS
30x1μmLVT
30x1μmLVT
30x1μmHVT
30x1μmHVT
40Ω
100pH
M1 M2
M3 M6M4 M5
X Y
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 23
High-speed, low-power BiCMOS latch High-speed, low-power BiCMOS latch (E. Laskin JSSC-Oct. 06)(E. Laskin JSSC-Oct. 06)
HBT ECL
INP
CLKP
INN
VCC
(3.3V)
CLKN
VG
OUTP
OUTN
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 24
0.3 mA/µm
High-speed, low-power BiCMOS latch High-speed, low-power BiCMOS latch (E. Laskin JSSC-Oct. 06)(E. Laskin JSSC-Oct. 06)
HBT ECL to BiCMOS CML
3.3 V to 2.5 V and reduced number of tails
INP
CLKP
INN
VCC
(3.3V)
CLKN
VG
OUTP
OUTN
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 25
0.3 mA/µm
0.15 mA/µm
High-speed, low-power BiCMOS latch High-speed, low-power BiCMOS latch (E. Laskin JSSC-Oct. 06)(E. Laskin JSSC-Oct. 06)
HBT ECL to BiCMOS CML
3.3 V to 2.5 V and reduced number of tails
1.8 V (lower power) at same speed
INP
CLKP
INN
VCC
(3.3V)
CLKN
VG
OUTP
OUTN
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 26
0.3 mA/µm
0.15 mA/µm
High-speed, low-power BiCMOS latch High-speed, low-power BiCMOS latch (E. Laskin JSSC-Oct. 06)(E. Laskin JSSC-Oct. 06)
HBT ECL to BiCMOS CML
3.3 V to 2.5 V and reduced number of tails
1.8 V (lower power) at same speed
Inductive peaking to increase speed
INP
CLKP
INN
VCC
(3.3V)
CLKN
VG
OUTP
OUTN
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 27
OutlineOutline
100GE fundamentals
Design methodology
90-Gb/s half-rate transceiver
100-Gb/s full-rate transceiver blocks
Round-up
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 28
GP 65-nm CMOS scales as expected GP 65-nm CMOS scales as expected
Future node performance is easy to
predict from Dennard's 1974 constant-
field scaling eqns.
All MOSFETs (from all foundries) are
practically the same.
0.15mA/m to 0.45mA/m is the
recommended bias range
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 29
Scaling of inductors to 100+GHz Scaling of inductors to 100+GHz
f -> fS, S = scaling factor, f = operation frequency
W -> W/S, W= stripe width
l -> l/S, l = total length of inductor winding
d -> d/S, d = inductor external diameter
davg
-> davg
/S, d = inductor average diameter
h -> h/S, h = dielectric thickness
t = constant, t = metal thickness
d
davg
h
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 30
Frequency scaling equations of inductor Frequency scaling equations of inductor ππ-model-model
L≈60n2 davg
2
11 d−7davg
LS≈
60 n2[ davg
S ]2
11 dS−7
davg
S
Cox=12
l Wox
h
Cox
S=1
2lS
WS
ox
hS
Cp=n W2 ox
hM9−M8
Cp
S=nWS
2 ox
hM9−M8
S
SRF≈ 12LCOXCp
S× SRF= 1
2 LS
COX
S
Cp
S
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 31
Scaling of inductors to 100+GHz (ii)Scaling of inductors to 100+GHz (ii)
Outcome
Inductors/transformers can be as small and inexpensive as transistors
As in MOSFETs, series resistance does not scale
The peak Q value remains the same,
with PQF at f×S
RDC= lW t
RDC= l
SWS
t
RAC= l
S
WS[1−exp−t
]= 1 f
Q=×S
LS
RDCRAC
=L
RDCRAC
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 32
metal 6 + alucap
Inductor and interconnect modeling Inductor and interconnect modeling (E. Laskin RFIC-07)(E. Laskin RFIC-07)
44-pH inductor for the oscillator tank
Shunted metals for low loss
Designed using ASITIC, SRF > 400 GHz
metal 5
P1 P2P1 P2P1 P2P1 P2
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 33
Inductor model verification through 94 GHzInductor model verification through 94 GHz
R
2-pi model
Q
measuredasitic
LR
2-pi model
Q
measuredasitic
L
0
10
20
30
40
50
60
70
0 50 100 150 200Frequency (GHz)
L (
pH
), Q
eff
0
2
4
6
8
10
12
14
R (
Oh
m)
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 34
Key design methodology ideasKey design methodology ideas
Bias at constant current density to minimize PVT in nanoscale CMOS
Avoid stacked-FET topologies to reduce impact of VT variation.
Trade off bias current with inductive peaking to minimize tail currents
Use analytical equations for 1st. cut design of all circuits
Add gate resistance to digital CMOS model
Layout in nanoscale CMOS is >> important than schematic
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 35
Example: Hierarchical design and breakout of cell for Example: Hierarchical design and breakout of cell for parasitic extractionparasitic extraction
Minimize footprint by merging transistors in diff. pairs, latching quads
VDD
(1.2V)
DATA_P
CLK_P
DATA_N
CLK_N
OUT_N
OUT_P
IBIAS
IBIAS
30x1μmLVT
30x1μmLVT
30x1μmHVT
30x1μmHVT
40Ω
100pH
M1 M2
M3 M6M4 M5
X Y
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 36
Hierarchical breakout of cell for parasitic extraction (ii)Hierarchical breakout of cell for parasitic extraction (ii)
Extract RC parasitics at cell level without inductors
DATA_P
CLK_P
DATA_N
CLK_N
OUT_N
OUT_P
IBIAS IBIAS
30x1μmLVT
30x1μmLVT
30x1μmHVT
30x1μmHVT
40Ω
100pH
M1 M2
M3 M6M4 M5
X Y
VDD
(1.2V)
DATA_P
CLK_P
DATA_N
CLK_N
OUT_N
OUT_P
IBIAS
IBIAS
30x1μmLVT
30x1μmLVT
30x1μmHVT
30x1μmHVT
40Ω
100pH
M1 M2
M3 M6M4 M5
X Y
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 37
Hierarchical breakout of cell for parasitic extraction (iii)Hierarchical breakout of cell for parasitic extraction (iii)
Extract RC parasitics at cell level without inductors
Model inductors and long interconnect as 2-π circuit with ASITIC
VDD
(1.2V)
DATA_P
CLK_P
DATA_N
CLK_N
OUT_N
OUT_P
IBIAS
IBIAS
30x1μmLVT
30x1μmLVT
30x1μmHVT
30x1μmHVT
40Ω
100pH
M1 M2
M3 M6M4 M5
X Y
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 38
Fself-osc = 14.5 GHzFmaximum = 35 GHz
Fself-osc = 22 GHzFmaximum = 51 GHz45% improvement
60µm
25µm
80µm
40µm
Version 1 (v1)
Version 2 (v2)
Impact of layout on 65-nmImpact of layout on 65-nm LP CMOS static frequency divider LP CMOS static frequency divider
© Sean Nicolson, BCTM 2006© Sean Nicolson, BCTM 2006© Sean Nicolson, 2007
Modeling power/bias/GND distributionModeling power/bias/GND distribution(S. Nicolson et al., IMS-2007)(S. Nicolson et al., IMS-2007)
Wide lines in metal mesh planes (max C, min. L and R) Surround bias/signal lines with GND-ed Faraday cageIsolate regions of the chip (grounded p-taps and DNW)Provide local de-coupling (< 0.5pF for 80 GHz)
© Sean Nicolson, BCTM 2006© Sean Nicolson, BCTM 2006© Sean Nicolson, 2007
Example: Bias/GND mesh satisfying metal density rulesExample: Bias/GND mesh satisfying metal density rules Substrate contact
(active + CON)
GND: odd (1,3,5) metals in blue
VDD
:even (2,4,6) metals
in redVIAs shunting odd metals
and SUB contact
VIAs shunting even metalsand DNW isolation
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 41
OutlineOutline
100GE system architectures
Design methodology
90-Gb/s half-rate transceiver
100-Gb/s full-rate transceiver blocks
Round-up
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 42
2.5-V, 1.4-W, 90-Gb/sTransmitter 2.5-V, 1.4-W, 90-Gb/sTransmitter (T.Dickson et al. CSICS-06)(T.Dickson et al. CSICS-06)
8:1 MUX
Output Driver
On-chipPRBS for
BIST
40-GHz PLL
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 43
2.5-V, 90-Gb/s BiCMOS Selector2.5-V, 90-Gb/s BiCMOS Selector
EF for higher bandwidth
SF for voltage headroom
90-Gb/s selector consumes 60mW
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 44
Measured results with external clock: 80 Gb/sMeasured results with external clock: 80 Gb/s
Running for more than 1 hour continuously in the lab.
Jitter: 560 fs (rms) , Rise/fall time: 4-5 ps, Amplitude: 300 mVpp
per side
80 Gb/s OUT40GHz CLOCK OUT
40GHz CLCK IN2.5GHz REF IN
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 45
Verification of correct multiplexingVerification of correct multiplexing
Using pattern capture capabilities of the Agilent 86100C DCA
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 46
90 Gb/s: amplitude control (new spin)90 Gb/s: amplitude control (new spin)
Little degradation in eye quality as amplitude varies from 150 mV to 300 mV per side
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 48
ComparisonComparison
1.36 W2.5 V90 Gb/s (half-rate)MOS: 85/90 GHz
HBT: 170/200 GHz130-nm SiGe
BiCMOS
2.3 W-3.6 V43 Gb/s (full-rate)HBT: 120/100 GHz180-nm SiGe
BiCMOS
1.6 W-3.6 V43 Gb/s (half-rate)HBT: 120/100 GHz180-nm SiGe
BiCMOS
3.6 W-3.6/ -5.2 V43 Gb/s (full-rate)150/150 GHzInP HBT
2.7 W1.5 V40 Gb/s (half-rate)85/90 GHz130-nm CMOS
PowerSupply Voltage
Data RatefT/fMAXTechnology
130-nm CMOS+170-GHz SiGe HBT = 2×speed + ½ power of 130-nm CMOS
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 49
OutlineOutline
100GE system architectures
Design methodology
90-Gb/s half-rate transceiver
100-Gb/s full-rate transceiver blocks
Round-up
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 50
Critical 100-Gb/s full-rate circuit blocksCritical 100-Gb/s full-rate circuit blocks
100-GHz flip-flop
100-GHz static frequency divider
100-GHz clock distribution network
100-GHz low-phase noise VCO
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 51
Divide-by-2 block diagram and latch schematicsDivide-by-2 block diagram and latch schematics
EXTERNALCLOCK
DRIVER
Master Latch Slave Latch
OUTPUT
VBIAS
VDD=1.2V
20
20 20
16
50 Ohm 50 Ohm
DATA
CLOCK
OUT
8mA latch
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 52
Divider layout (20 x 16 Divider layout (20 x 16 µµmm22))
22µm
26µm
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 53
90-GHz, 65-nm GP CMOS static divider: 2% variation 90-GHz, 65-nm GP CMOS static divider: 2% variation
Power = 19.6mW per divider + 22.4mW for output buffer
Average Self-Oscillation Frequency (SOF) =39.5GHz (@ the output)
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 54
PVT performance of 65-nm GP CMOS dividerPVT performance of 65-nm GP CMOS divider
Operates up to 78.5 GHz at 100 0C from 1.1V supply and at 80 GHz at 125 0C
from 1.4 V
Does not divide below 57GHz
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 55
65-nm GP/LP CMOS vs. SiGe HBT and BiCMOS 65-nm GP/LP CMOS vs. SiGe HBT and BiCMOS dividers dividers
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 56
Comparison with published 80+GHz static dividersComparison with published 80+GHz static dividers
ReferenceSelf-Oscillation
Freq.Max. Divider
Freq.Power Consumption Technology
This work 45 GHz 51 GHz 42mW(1.5V) 65nm LP-CMOSThis work 80 GHz 91 GHz 20 mW (1.2V) 65nm GP-CMOS PlouchartISCC-07 92 GHz 102 GHz 52.4mW(2.2V) 65nm HP SOI CMOS
TrottaCSICS-05
65 GHz 110 GHz 1.35 W (-5.2V) 225-GHz fT SiGe HBT
HitkoCSICS-04
95 GHz 143.6 GHz 90 mW 400-GHz fT InP
RylyakovCSICS-04
71 GHz 96 GHz 770 mW (-5.0V) 210-GHz fT SiGe HBT
LaskinBCTM-07 77 GHz >100 GHz 122 mW (3.3-3.6V) 230-GHz fT SiGe HBT
NicolsonIMS-07
81 GHz >105 GHz 75 mW (2.5V) 230-GHz fT SiGe HBT
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 57
Comparison with published 80+GHz static dividersComparison with published 80+GHz static dividers
ReferenceSelf-Oscillation
Freq.Max. Divider
Freq.Power Consumption Technology
This work 45 GHz 51 GHz 42mW(1.5V) 65nm LP-CMOSThis work 80 GHz 91 GHz 20 mW (1.2V) 65nm GP-CMOS PlouchartISCC-07 92 GHz 102 GHz 52.4mW(2.2V) 65nm HP SOI CMOS
TrottaCSICS-05
65 GHz 110 GHz 1.35 W (-5.2V) 225-GHz fT SiGe HBT
HitkoCSICS-04
95 GHz 143.6 GHz 90 mW 400-GHz fT InP
RylyakovCSICS-04
71 GHz 96 GHz 770 mW (-5.0V) 210-GHz fT SiGe HBT
LaskinBCTM-07 77 GHz >100 GHz 122 mW (3.3-3.6V) 230-GHz fT SiGe HBT
NicolsonIMS-07
81 GHz >105 GHz 75 mW (2.5V) 230-GHz fT SiGe HBT
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 58
70-100 GHz 65-nm LP CMOS vs. SiGe HBT LNAs as 70-100 GHz 65-nm LP CMOS vs. SiGe HBT LNAs as clock buffers clock buffers (S. Nicolson et al. IMS-07)(S. Nicolson et al. IMS-07)
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 59
105-GHz SiGe HBT Colpitts VCO Schematics105-GHz SiGe HBT Colpitts VCO Schematics
104 GHz, PDC
= 120 mW, 2.5V
Die size: 0.4mmx0.5mm
CPAD
32fF
LPAD
VO+
VCC
= 2.5V
VO-
LPAD
CPAD
32fF
C4
C4
LC
LC
LB
LB
C1
C1
CVAR
CVAR
LEE
LEEC
EER
EE
RB1
RB2
VBB
= 2.5V50Ω line C
3C
3
VTUNE+
VTUNE-
RT
RT
AMOS varactorsW
G = 4 × 18 × 1µm
LG = 0.13µm
HBTsL
E = 4 × 5µm
WE = 0.13µm
IC
VTUNE-
RT
VTUNE+
RT
RB
Cπ
C1
C
E
B
T1
50Ω lineT
1
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 60
104-GHz VCO phase noise: -101 dBc/Hz @ 1MHz104-GHz VCO phase noise: -101 dBc/Hz @ 1MHz
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 61
SummarySummary
Need simpler topologies with fewer transistors for higher speed
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 62
SummarySummary
Need simpler topologies with fewer transistors for higher speed
GP MOSFET scaling is predictable and desired for high-speed
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 63
SummarySummary
Need simpler topologies with fewer transistors for higher speed
GP MOSFET scaling is predictable and desired for high-speed
Layout critical in nanoscale CMOS for 100-GHz applications
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 64
SummarySummary
Need simpler topologies with fewer transistors for higher speed
GP MOSFET scaling is predictable and desired for high-speed
Layout critical in nanoscale CMOS for 100-GHz applications
1.4W, 90-Gb/s half-rate transmitter in 170-GHz SiGe BiCMOS
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 65
SummarySummary
Need simpler topologies with fewer transistors for higher speed
GP MOSFET scaling is predictable and desired for high-speed
Layout critical in nanoscale CMOS for 100-GHz applications
1.4W, 90-Gb/s half-rate transmitter in 170-GHz SiGe BiCMOS
Full-rate 100-Gb/s circuits in 65-nm CMOS and SiGe HBT technologies
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 66
SummarySummary
Need simpler topologies with fewer transistors for higher speed
GP MOSFET scaling is predictable and desired for high-speed
Layout critical in nanoscale CMOS for 100-GHz applications
1.4W, 90-Gb/s half-rate transmitter in 170-GHz SiGe BiCMOS
Full-rate 100-Gb/s circuits in 65-nm CMOS and SiGe HBT technologies
A 3W, 100-Gb/s half-rate serial transceiver is feasible in 300-GHz SiGe
BiCMOS technology now
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 67
SummarySummary
Need simpler topologies with fewer transistors for higher speed
GP MOSFET scaling is predictable and desired for high-speed
Layout critical in nanoscale CMOS for 100-GHz applications
1.4W, 90-Gb/s half-rate transmitter in 170-GHz SiGe BiCMOS
Full-rate 100-Gb/s circuits in 65-nm CMOS and SiGe HBT technologies
A 3W, 100-Gb/s half-rate serial transceiver is feasible in 300-GHz SiGe
BiCMOS technology now
At least 45-nm GP CMOS is needed for half-rate 100-Gb/s transceiver
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 68
AcknowledgmentsAcknowledgments
Jaro Pristupa and CMC for CAD support
OIT, CFI, ECTI for equipment
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 70
Phase frequency detectorPhase frequency detector
CLK
VBIAS
D
RL
Q2Q1 Q4Q3
M2M1
VCC (2.5V)
RESET
Q
Q6Q5 Q7
M4M3
RL RL RL
Phase Frequency Detector
D Q
D Q
REF
DIV
'1'
'1'
RESET
UP
DOWN
AsynchronousResettableLatch
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 71
36-43 GHz Colpitts VCO36-43 GHz Colpitts VCO
SiGe HBTs used as negative resistance generators.
Differential tuning to reject common-mode noise.
Maximize tank swing, bias HBTs at NFMIN for low phase noise
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 72
VCO Phase NoiseVCO Phase Noise
-103 dBc/Hz @ 1-MHz offset
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 73
PLL measurements PLL measurements (T. Chalvatzis et al., VLSI-07)(T. Chalvatzis et al., VLSI-07)
Locking range: 38-42 GHz
RMS jitter: σt = 496 fs
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 74
90nm CMOS retiming DFF 90nm CMOS retiming DFF (T. Chalvatzis et al. JSSC July 07)(T. Chalvatzis et al. JSSC July 07)
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 75
Clock must fully switch M1/M2
VDS,M7/8 swings as low as VT
(M1/M2)
Use high-VT for M1/M2
Clock-path biasing schemeClock-path biasing scheme
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 76
Measurements at 40Gb/s and 1.2VMeasurements at 40Gb/s and 1.2V
Error-free 508-bit patternInput (top), output (bottom)
10.8mW1.2V 40Gb/s120-GHz CMOSThis work
20mW2.5V43.5Gb/s150-GHz SiGe BiCMOS[Dickson,CSICS2006]
20mW1.5V50Gb/s150-GHz InP HBT[Amamiya,JSSC2005]
N/A5.7V80Gb/s245-GHz InP HEMT[Suzuki,JSSC2004]
PLATCHSupplyRateTechnologyReference
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 77
CMOS vs. HBT amplifiers (useful as clock buffers)CMOS vs. HBT amplifiers (useful as clock buffers)
20×1.5μmtwo-sided gate
contact
65nm LP CMOS(55 mW, 13.5 dB)
290-GHz SiGe HBT (52 mW, 25 dB)
[S.T. Nicolson et al. IMS-07, CSICS-06]
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 78
Sims before and after extraction of transistor layoutSims before and after extraction of transistor layout
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 79
SOF Variation for 65nm LP Divider (v2): <4%SOF Variation for 65nm LP Divider (v2): <4%
Mapping of 10 dies across the wafer shows < 4% variation in SOF
Average SOF = 22 GHz
Power = 24mW / latch
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 80
v2v1
Measured sensitivity curves vs. temperature @ VMeasured sensitivity curves vs. temperature @ VDDDD=1.5V=1.5V
1.7V
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 81
Phase Noise and Jitter Performance of 65nm LP Divider (v2) – 38GHz Input
18.5GHz divided down output
Output power = -8.2 dBm
-110 dBc/Hz @ 100kHz offset
19GHz divided down output
Output swing = 200mVpp
~200fs of RMS jitter
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 82
Phase Noise and Jitter Performance of 65nm LP Divider (v2) – 50GHz Input
25GHz divided down output
Output power = -12.2 dBm
-108 dBc/Hz @ 100kHz offset
25GHz divided down output
Output swing = 150mVpp
~217fs of RMS jitter
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 83
Latch layout (12 x 6 Latch layout (12 x 6 µµmm22))
M3, M6 M4, M5
M1 M2
12um
Sorin Voinigescu et al., CICC-2007, September 18th, 2007 84
65nm GP CMOS time domain measurements65nm GP CMOS time domain measurements
76 GHz divided down output signal showing low timing jitter
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