tms320c6xx dr. naim dahnoun, bristol university, (c) texas instruments 2004 tms320 c6xx instruction...
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TMS320TMS320C6xxC6xxDr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
TMS320 C6xx
Instruction SetInstruction Set
2
'C'C6xx6xx Instruction Set - Instruction Set - OperandsOperands
ADD .L1 A0, A1, A2ADD .L1 A0, A1, A2
ADD .L2 ADD .L2 -5-5, B3, B4, B3, B4
ADD .L1 A2, A3, ADD .L1 A2, A3, A5:A4A5:A4
ADD .L1 A2, ADD .L1 A2, A5:A4A5:A4, , A5:A4A5:A4
ADD .L2ADD .L2 3 3,, B9:B8 B9:B8,, B9:B8 B9:B8
3
'C'C6xx6xx Instruction Set - Instruction Set - Cross Cross PathPath
ADD .L2x A0,A1,B2 MPY .M1x A0,B6,A9 SUB .S1x A8,B2,A8 ADD .L1x A0,B0,A2
ADD .L2x A0,A1,B2 MPY .M1x A0,B6,A9 SUB .S1x A8,B2,A8 ADD .L1x A0,B0,A2
LDW .D1T2 *A0,B5 STW .D2T1 A5,*B0
LDW .D1T2 *A0,B5 STW .D2T1 A5,*B0
TMS320 C67x
4
'C'C6xx6xx Instruction SetInstruction Set Parallel OperationParallel Operation
ADD .L2x A0,A1,B2
| | MPY .M1x A0,B6,A9 SUB .S1x A8,B2,A8 ADD .L1x A0,B0,A2
ADD .L2x A0,A1,B2
| | MPY .M1x A0,B6,A9 SUB .S1x A8,B2,A8 ADD .L1x A0,B0,A2
LDW .D1T2 *A0,B5|| STW .D2T1 A5,*B0
LDW .D1T2 *A0,B5|| STW .D2T1 A5,*B0
L1 S1 M1 D1 L2 S2 M2 D2
TMS320TMS320C6xxC6xxDr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
TMS320 C62x
Instruction SetInstruction Set
6
ArithmeticArithmeticABSABSADDADDADDADDAAADDADDKKADDADD22MPYMPYMPYMPYHHNEGNEGSSMPYMPYSSMPYMPYHHSSADDADDSATSATSSSUBSUBSUBSUBSUBSUBAASUBSUBCCSUBSUB22ZEROZERO
Program CtrlProgram CtrlBBIDLEIDLENOPNOP
LogicalLogicalANDANDCMPCMPEQ EQ (=)(=)CMPCMPGT GT (>)(>)CMPCMPLT LT (<)(<)NOTNOTORORSHSHL L (<<)(<<)SHSHR R (>>)(>>)SSSHSHLLXORXOR
Data MgmtData Mgmt
LDLDBB//HH//WWMVMVMVMVCCMVMVKKMVMVKLKLMVMVKHKHMVMVKLHKLHSTSTBB//HH//WW
Bit MgmtBit MgmtCLRCLREXTEXTLMBDLMBDNORMNORMSETSET
Note: Refer to the 'C6000 CPU Reference Guide for more details.Note: Refer to the 'C6000 CPU Reference Guide for more details.
'C'C62x62x Instruction Set (by Instruction Set (by categorycategory))
Aritmetica di saturazioneAritmetica di saturazioneSe utilizzo la classica aritmetica di arrotondamento in un procedimento di incremento di colore allora se dovessi
giungere al limite di rappresentazione di un dato un ulteriore incremento determinerebbe un overflow (il numero
raggiungerebbe erroneamente il limite opposto).Quando io sommo invece ad esempio due valori a 32 bit
che raggiungono un valore che eccede i limiti di rappresentazione, in un procedimento di incremento di
colore, avrei semplicemente bisogno di indicare che ho raggiunto il valore massimo rappresentabile. Questo è un
evento particolarmente frequente in applicazioni multimediali (ad esempio nei valori di colore dei pixel) e
l’aritmetica di saturazione serve appunto a questo.
Integer AdditionUsing Signed 16-Bit Constant
Integer AdditionUsing Addressing Mode
Two 16-Bit Integer Adds onUpper and Lower Register Halves
if (cond){((lsb16(src1) + lsb16(src2)) and FFFFh) or((msb16(src1) + msb16(src2)) << 16) -> dst}
else nop
Conditional Integer Subtract and ShiftUsed for Division
if (cond){if (src1 – src2 >= 0) ( (src1–src2) << 1) + 1 -> dst
else src1 << 1 -> dst}else nop
Signed or Unsigned Integer Multiply16 lsb x 16 lsbSigned or Unsigned Integer Multiply16 msb x 16 msb
7
'C'C62x62x Instruction Set (by Instruction Set (by unitunit))
.S Unit.S Unit
MVKLHMVKLHNEGNEGNOT NOT ORORSETSETSHLSHLSHRSHRSSHLSSHLSUBSUBSUB2SUB2XORXORZEROZERO
ADDADDADDKADDKADD2ADD2ANDANDBBCLRCLREXTEXTMVMVMVCMVCMVKMVKMVKLMVKLMVKHMVKH
.M Unit.M Unit
SMPYSMPYSMPYHSMPYH
MPYMPYMPYHMPYH
.L .L UnitUnit NOTNOT
ORORSADDSADDSATSATSSUBSSUBSUBSUBSUBCSUBCXORXORZEROZERO
ABSABSADDADDANDANDCMPECMPEQQCMPGCMPGTTCMPLTCMPLTLMBDLMBDMVMVNEGNEGNORMNORM.D Unit.D Unit
STB/H/WSTB/H/WSUBSUBSUBASUBAZEROZERO
ADDADDADDAADDALDB/H/WLDB/H/WMVMVNEGNEG
OtherOther
IDLEIDLENOPNOPNote: Refer to the 'C6000 CPU Note: Refer to the 'C6000 CPU Reference Guide for more details. Reference Guide for more details.
TMS320C62x/C64x/C67xFixed-Point Instruction Set
TMS320TMS320C6xxC6xxDr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
TMS320 C67x
Instruction SetInstruction Set
9
' ' CC67x67x: Superset of : Superset of Floating-Floating-PointPoint
No Unit UsedIDLENOP
.S UnitNEGNOT ORSETSHLSHRSSHLSUBSUB2XORZERO
ADDADDKADD2ANDBCLREXTMVMVCMVKMVKLMVKH
ABSSPABSDPCMPGTSPCMPEQSPCMPLTSPCMPGTDPCMPEQDPCMPLTDPRCPSPRCPDPRSQRSPRSQRDPSPDP
.L UnitNOTORSADDSATSSUBSUBSUBCXORZERO
ABSADDANDCMPEQCMPGTCMPLTLMBDMVNEGNORM
ADDSPADDDPSUBSPSUBDPINTSPINTDPSPINTDPINTSPTRUNCDPTRUNCDPSP
.M UnitSMPYSMPYH
MPYMPYHMPYLHMPYHL
MPYSPMPYDPMPYIMPYIMPYIDMPYID
.D Unit
NEGSTB (B/H/W) SUBSUBAB (B/H/W) ZERO
ADDADDAB (B/H/W)ADDADLDB (B/H/W)LDDWMV Note: Refer to the 'C6000 CPU Reference Guide for more details.Note: Refer to the 'C6000 CPU Reference Guide for more details.
(by (by unitunit))
32-Bit Integer Multiply – Result Is Lower 32 Bits
32-Bit Integer Multiply – Result Is Lower 64 Bits
10 ‘C62x: Dual 32-Bit Load/Store ‘C64x: Dual 64-Bit Load/Store ‘C67x: Dual 64-Bit Load/32-Bit Store
Instruction Decode
Instruction Dispatch
Instruction Fetch Control Registers Interru
pt
Co
ntro
l
Emulation
Registers (B0 - B15)
D2+
M2
X
S2++
L2+
Registers (A0 - A15)
D1+
M1
X
S1++
L1+
Advanced Instruction Packing Advanced
Emulation
Registers (B16 - B31)Registers (A16 - A31)
+xxxxX +
+
+++
+xxxx X+
+
+++
Superset of Floating-PointSuperset of Floating-Point
TMS320TMS320C6xxC6xxDr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
TMS320 C64x
Instruction SetInstruction Set
12
'C'C64x64x:: Superset Fixed-Point of Superset Fixed-Point of ‘C62x‘C62x
Data Pack/UnPACK2PACKH2PACKLH2PACKHL2PACKH4PACKL4UNPKHU4UNPKLU4SWAP2/4
Dual/Quad ArithABS2ADD2ADD4MAXMINSUB2SUB4SUBABS4
Bitwise LogicalANDN
Shift & MergeSHLMBSHRMB
Load ConstantMVK (5-bit)
.L .L
.D .D
.S .S
.M .M
Bit OperationsBITC4BITRDEALSHFL
MoveMVD
AverageAVG2AVG4
ShiftsROTLSSHVLSSHVR
MultipliesMPYHIMPYLIMPYHIRMPYLIRMPY2SMPY2DOTP2DOTPN2DOTPRSU2DOTPNRSU2DOTPU4DOTPSU4GMPY4XPND2/4
Mem AccessLDDWLDNWLDNDWSTDWSTNWSTNDW
Load ConstantMVK (5-bit)
Dual ArithmeticADD2SUB2
Bitwise LogicalANDANDNORXOR
Address Calc.ADDAD
Data Pack/UnPACK2PACKH2PACKLH2PACKHL2UNPKHU4UNPKLU4SWAP2SPACK2SPACKU4
Dual/Quad ArithSADD2SADDUS2SADD4
Bitwise LogicalANDN
Shifts & MergeSHR2SHRU2SHLMBSHRMB
ComparesCMPEQ2CMPEQ4CMPGT2CMPGT4
Branches/PCBDECBPOSBNOPADDKPC
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