thesis l leyssenne - november 27th 2009 - part1
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Design of Reconfigurable
Radiofrequency Power
Amplifiers
for Wireless Applications
Laurent Leyssenne
Director: Eric Kerhervé
Co-director: Yann Deval
IMS Laboratory – Bordeaux – France
Design group
Microwave Circuits & Systems team
November 27th 2009
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Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1
ConclusionGate Bias Envelope TrackingPA discretized reconfigurabilityIntro..
I. Introduction
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Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1
Present trends in modern standards (a)
Increased throughput in 3G/4G standards.
More complex modulation scheme
Increased Peak-to-Average Power Ratio (P.A.P.R.)
Wider channel bandwidth
Still high power / range
E.g.:
WiMAX: OFDMA, 10MHz channel, 23dBm output power, 12dB PAPR
LTE: SC-FDMA, 20MHz channel, 24dBm output power, 7/8dB PAPR
Linearity/Efficiency trade-off
Battery life-time
ConclusionGate Bias Envelope TrackingPA discretized reconfigurabilityIntro..
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Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1
Present trends in modern standards (b)
ConclusionGate Bias Envelope TrackingPA discretized reconfigurabilityIntro..
Source: Chris Rudell - Intel
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Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1
Issues related to handset PA design (a)
Demand of high efficiency.
Low Bill-Of-Material
Low die area
Many stringent requirements in terms of linearity
Spectral/time masks
Adjacent Channel Leakage Ratio
Error Vector Magnitude (max, RMS)
Max and/or RMS phase error, max. phase steps …
ConclusionGate Bias Envelope TrackingPA discretized reconfigurabilityIntro..
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Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1
Issues related to handset PA design (b)
ConclusionGate Bias Envelope TrackingPA discretized reconfigurabilityIntro..
Main and adjacent channels
for a 3.84Mcps HPSK signal (WCDMA)
and ACLR automated computation
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Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1
Issues related to handset PA design (c)
ConclusionGate Bias Envelope TrackingPA discretized reconfigurabilityIntro..
HPSK illustration and EVM automated computation
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Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1
Fundamental goal of this thesis
Developing novel smart and compact adaptive PA
architectures on silicon to save battery life-time.
Low silicon area
Adaptive mechanisms over wide power dynamic range,
and over wide channel bandwith
Two adaptive families:
Discretized PA
Adaptive bias PA
Put stress on « low power » integrated analog signal
processing.
ConclusionGate Bias Envelope TrackingPA discretized reconfigurabilityIntro..
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Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1
ConclusionIntro. Gate Bias Envelope TrackingPA discretized reconfigurability
II. Power Amplifier discretized
reconfigurability
PA architectures developed in the frame of projects
Medea+ UpperMost and RNRT Asturies.
Reconfigurable PA for WiFi (802.11n), WiMAX
(802.16e) and WCDMA applications.
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Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1
PA architectures based on Switched power cells
ConclusionIntro. Gate Bias Envelope TrackingPA discretized reconfigurability
Stage bypass: non constant–gain technique
AGC loop is required
Severe phase hopping must be avoided
Slow reconfiguration rate (~kHz)
Parallelized switched power cells: « quasi » constant
gain technique
Fast reconfiguration rate allowed
Interpolation allowed over a wide power range.
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Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1
Power stage Bypass architecture (a)
ConclusionIntro. Gate Bias Envelope TrackingPA discretized reconfigurability
Bypass/drive
r stage
Power stage
Power stage bypass synoptic
p phase shifter
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Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1
Power stage Bypass architecture (b)
ConclusionIntro. Gate Bias Envelope TrackingPA discretized reconfigurability
2.312.38mm2 BiCMOS
Layout demonstrator
Test Board on Epoxy
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Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1
Power stage Bypass architecture (c)
ConclusionIntro. Gate Bias Envelope TrackingPA discretized reconfigurability
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Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1
PA architecture based on Parallelized Switched power
cells (a)
ConclusionIntro. Gate Bias Envelope TrackingPA discretized reconfigurability
Discretized power stage
AM/AM
Reduced averaged interpolated AM/AM
AM/AM « analogous » to ADC response
Quantization magnitude noise results in
distortion
white noise over the bandwidth
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Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1
PA architecture based on Parallelized Switched power
cells (b)
ConclusionIntro. Gate Bias Envelope TrackingPA discretized reconfigurability
Discretized power stage
Reduced averaged interpolated AM/PM
Quantization phase noise results in
distortion
pink noise in the carriers’ vicinity
AM/PM
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Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1
PA architecture based on Parallelized Switched
power cells (c)
ConclusionIntro. Gate Bias Envelope TrackingPA discretized reconfigurability
Discrete adaptive reconfigurability
Control bits = digitalized image of envelope/EVM
Volterra kernels are dynamically modulated by control
bits
!! Quantization noise is upconverted to RF band
Importance of Over-Sampling Ratio, and resolution
+ Delta-Sigma technique
n
ININ
ININ
jj,1j qXX
XXΔggg
min_max_
min_
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Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1
PA architecture based on Parallelized Switched
power cells (d)
ConclusionIntro. Gate Bias Envelope TrackingPA discretized reconfigurability
w1 w2 2w2-w12w1-w2
w1 w2
2w2-w12w1-w2
w1 w2
2w2-w12w1-w2
IMD3 level for a class A PA
IMD3 level for
a reconfigurable PA
Quantization noise level for a reconfig. PA
controlled by a DS modulated envelope
Quantization noise level
for a basic reconfigurable PA
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Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1
PA architecture based on Parallelized Switched
power cells (e)
ConclusionIntro. Gate Bias Envelope TrackingPA discretized reconfigurability
Band-Pass filter:
• Bandwidth fixed by standard
• Selectivity can be increased
at cost of higher in-band losses
Decimator channel filter:
• Operates in base-band domain
• Bandwidth can be optimized
(>Bwchannel)
• Selectivity/order can be
increased
at cost of higher latency (>2TS)
• Higher complexity
Digital
filter
Clk
Control
word
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Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1
PA architecture based on Parallelized Switched
power cells (f)
ConclusionIntro. Gate Bias Envelope TrackingPA discretized reconfigurability
Two approaches were considered
Open-loop topology:
a Delta-Sigma Built-In Current Sensor probes 2nd order non-linear
currents at PA input
Modular approach
Closed-loop topology:
Reconfigurable PA is inserted in a loop.
Instantaneous EVM is probed and fed-back to PA.
Delta-Sigma-like topology
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Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1
ConclusionIntro. Gate Bias Envelope TrackingPA discretized reconfigurability 1.
Schematic
First Approach: PA control via DS-BICS
Envelope detection
law (IENV)
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Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1
ConclusionIntro. Gate Bias Envelope TrackingPA discretized reconfigurability 1.
IENV
Envelope detection lawSchemati
c
Built-In Current
Sensor schematic
First Approach: PA control via DS-BICS (a)
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Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1
ConclusionIntro. Gate Bias Envelope TrackingPA discretized reconfigurability 1.
IENV
Envelope detection lawSchemati
c
Built-In Current
Sensor schematic
First Approach: PA control via DS-BICS (b)
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Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1
ConclusionIntro. Gate Bias Envelope TrackingPA discretized reconfigurability 1.
IENVIENV
Envelope detection lawSchemati
c
First Approach: PA control via DS-BICS (c)
Built-In Current
Sensor schematic
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Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1
Base-band Synoptic & BICS theoretical response
ConclusionIntro. Gate Bias Envelope TrackingPA discretized reconfigurability 1.
D
min_max_,2min_2
0
min_1,20,
1 ININNININ
ININwn
BICS
XXYXXYFS
H
XXYHqV
pp
p
VBICS vs. XIN response
is analogous to ADC
but linearity degraded
Linearization by non-uniform
current DACs
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Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1
Architecture response for a WLAN transmitter (a)
ConclusionIntro. Gate Bias Envelope TrackingPA discretized reconfigurability 1.
PA output spectrum
(RF domain)
Chronograms
BICS output spectrum
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Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1
Architecture response for a WLAN transmitter (b)
ConclusionIntro. Gate Bias Envelope TrackingPA discretized reconfigurability 1.
PA output spectrum
(RF domain)
BICS output spectrum
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Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1
Conclusion on first discrete approach
ConclusionIntro. Gate Bias Envelope TrackingPA discretized reconfigurability 1.
Significant efficiency improvement compared with
classA
Spectral mask requirements are respected in the
channel vicinity …
…but issues @40MHz from carrier
Wider BICS bandwidth
Decimator filter insertion prior to PA
EVM degradation in the bottom reconfiguration power
corner.
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Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1
Second approach: PA embedded in an
EVM-cancellation closed-loop
ConclusionIntro. Gate Bias Envelope TrackingPA discretized reconfigurability 2.
Non linear Delta-Sigma loop in base-band domain
PA core + power detector = DAC-like block
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Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1
Architecture response for a
WLAN transmitter
ConclusionIntro. Gate Bias Envelope TrackingPA discretized reconfigurability 2.
Impact of Resolution on
spectral performances
ACLR control over
targeted power range
Improved EVM
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Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1
Conclusion on Second discrete approach
ConclusionIntro. Gate Bias Envelope TrackingPA discretized reconfigurability 1.
Significant efficiency improvement compared with
classA
Spectral mask requirements are respected in the
channel vicinity …
…but still issues @40MHz from carrier
Wider loop bandwidth is necessary
Decimator filter cannot be considered
EVM degradation in the bottom reconfiguration power
corner is properly handled.
High VSWR sensitivity:
Slow control loop is necessary to adjust the average
feedback envelope magnitude and avoid EVM over-estimation.
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Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1
PA discretized reconfigurability
III. Envelope tracking based on
reconfigurable depth adaptive gate Bias
ConclusionIntro. Gate Bias Envelope Tracking
PA architecture developed in the frame of FP6
MOBILIS European project
A multi-band Transmitter for DCS/EDGE/WCDMA
applications
Wide-band differential-to-single PA Module:
Targeted band: [1710MHz,1980MHz]
Adaptive bias functionality
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Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1
PA discretized reconfigurability
MOBILIS transceiver architecture
ConclusionIntro. Gate Bias Envelope Tracking
Overall
demonstrator
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Laurent Leyssenne – November 27th 2009 – Bordeaux – Part 1
PA discretized reconfigurability
MOBILIS transceiver architecture
ConclusionIntro. Gate Bias Envelope Tracking
Unit demonstrator
Silicon to IPD
wire-bonded connexion
• Very low-Z node!
• Inter-chip gap sensitive
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