system overview of the phase 1 pixel upgrade
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System Overview of the Phase 1 Pixel Upgrade
CMS Upgrade WorkshopCERN
14. May 2009
R. Horisberger
Paul Scherrer Institut
• BPIX 3 Layer 4 Layers
• FPIX 2x2 Disk 3x2 Disk
• CO2 cooling based Ultra Light Mechanics
• Shift material budget out of tracking eta - region
• Modify PSI46 ROC for 160MHz digital readout & Increase depth of ROC buffers
• Serialized binary optical readout at 320 MHz to modified px-FED (new piggy cards)
• Rebuilt new AOH lasers 320MHz binary transmission
• Same FEC’s , identical TTC & ROC programming
• Use existing fibres & cables
• Keep LV-power supply & push more current through cables
Pixel Upgrade Phase 1 (2014)
Current Pixel System with Supply Tubes / Cylinders
10
0
20
20 40 60 80 100
FPIX service cylinder
BPIX supply tube
DOH & AOH mother board+ AOH’s
Power board endflange printsLayer 3 & 1+2
Shift Material out of tracking Volume
new BPIX modules with long pigtails (~1.2m) ( micro-twisted pairs)
10
0
20
20 40 60 80 100
FPIX service cylinder
DOH & AOH mother board+ AOH’s
power board Move DOH & AOH boards
back by 50-60cm
BPIX/FPIX Envelope Definition for 4 Layer Pixel System
Various iterations forth and back by R.H. / Silvan Steuli / Kirk Arndt
no further changes since 2.12.2008 !
All barrel layers 4 module long small eta hole of ~ 0.08 at =1.288
• 7 module geometries
• 168 modules per disk
Total 4x1080 = 4320 ROC
• 72 outer & 44 inner radius modules
• 1 module geometry• 116 modules per disk 1856 ROCsTotal 6x1856 = 11’1136 ROC
R 144.6 mm
R 58.7 mm
R 161 mm
R 39 mm
FPIX Conceptual Layout
Present FPIX 2x2 Disk2014 FPIX 2x3 Disk
Each half shell has 10 cooling loops
Each supply tube feeds 5 cooling loops
Angle bend (~30) during insertion taken by carbon fibre hinge
Stainless steel tubesdiameter = 1.8mmwall thickness = 100μm
Carbon fiber hinge
Inertion of BPIX – Supplytube System with new CO2 Cooling
New axis of rotation (~3 degrees) during pixel insertion
− 10 −Design Status BPIX Mechanics - April 2009 Silvan Streuli PSI Villigen
Prototype Fabrication Layer 1
100 bar pressure testedTubes, 50 wall thickness
Weight Layer1 42g + 7g CO2
− 11 −Design Status BPIX Mechanics - May 2009 Silvan Streuli PSI Villigen
Stainless steel facets used as heater resistors to simulate the power consumption of the sensor modules. Daisy chained connected (blue cable).
Cooling tubes are electrically isolated to the stainless steel facets
Thermal isolation material.
Top lid not shown.
Test of long CO2 cooling loop ( as in Layer 1)
px-AOH
px-DOH PLLDelay25
px-FED
px-FEC
crt
, 4
0M
Hz
fas
t I2 C
40 MHz analog out
trk-FECCCU
I2C
I2C
CMS Pixel Read Out System
40MHzanalogoptical
Current System: 0-suppressed analog coded data readout at 40MHz
AB
New Phase 1 System:0-suppressed serial binary data readout at 320MHz, same data structure
320 MHz binary
320 MHzbinaryoptical
•Analog readout (40MHz)•serial (1 or 2 channels)•Double columns in ROC blocked until read out
controlled by serial readout token: TBM-ROC1-…-16-TBM
analog multiplexer and line-driver in TBM
BPIX module 4 x 4 ROC TBM AOH pxFED
A - channelB - channel
skip
ROC ROC ROC ROC ROC ROC ROC ROC
ROCROCROCROC ROCROCROCROC
TBManalog summing amplifiers
analog summing amplifiers A fibre
B fibre
Current Pixel Module Readout
Layer 1& 2 2 Fibre A & BLayer 3 1 Fibre A
ROC TBM : 40 MHz analog readout
TBM pxFED : 40 MHz analog readout
40 MHz
Pixel uses analog coded digital pixel readout
Pixel address 5 x 3 bit
Pulse height 1 x 8 bit
total 23 bits/ pixel hit in 6 clock cycles
chipheader
1 pixel hit
ub b 3rd
c1 c2 r1 r2 r3 ph
160 Mbits/sec link speed resp. 1300 pJ/bit
8 le
vels
= 3
bits
Present analog coded data transfer of pixel system
ROC ROC ROC ROC ROC ROC ROC ROC
ROCROCROCROC ROCROCROCROC
TBManalog summing amplifiers
analog summing amplifiers
New Serialized Binary Pixel Module Readout
Layer 1 - 4 1 Fibre/module
ROC TBM : 160 MHz digital readout
TBM pxFED : 320 MHz digital readout
160 MHz
320 MHz
New serial binary data transfer of pixel system
time
25ns40 MHz LHC Clock
1111 1111 XXXX 1010 1011 1001 1011 0001 1011
pulse heightrow/column address
1 pixel hit 150nsec long 24 bits with 160 MHz
ROC header12 bit long
New ROC serial bit clock is 160MHz 4 bits / LHC clock cycle
160 MHz clock to be generated in each ROC by 40 MHz 160 MHz PLL circuit
See talk H-C. Kästli
Pixel ROC26 dcol
160 pix/each
TBM-chip
4 x 4 ROC
160 MHz serial binary
320 MHz
serial binary
pxFED
replace present ADC plug-in card with deserializer card
deserializerplug in card
New TBM purely digital chipno x-tra data bufferingMultiplex 2 token passages
Core of ROC chip unchanged but modified I/O periphery:1) address DAC removed2) 1 ADC for pulse height added3) 40MHz 160MHz PLL added
160 MHz PLL1x ADC (8-bit)
160/ 320 MHz PLL
Changes for 160/320 MHz serial binary readout
Changes
ADC
PLL
40MHz
• Core of chip untouched !
• Only changes to periphery
column periphery
Pixel cell
Implications for the ROC
• Remove DAC
• Add PLL 40 MHz 160 MHz
• Add 160MHz bit serializer
• Replace analog driver with digital driver
Pixel FED HEPHY, ViennaM.PernickaH. SteiningerM. Friedl
3x 12 channels with 9 piggy-back ADC cards
Replace ADC cards with new deserializer piggy-back cards
Opto-Rx Measurementsfor Pixel Upgrade
What? Why? How?
• Digital optical 320 Mb/s transmission is intended for pixel phase 1 upgrade
• Recycling of existing optical links possible?
– Sender side appears OK
– Most severe bandwidth limitation in12-way receiver (ARx12) ~100 MHz
• Comparative test of digital transmission at 320 Mb/s between existing ARx12 and Zarlink engineering sample
• Each mounted on test board (clean environment)
• ARx12 with external fast, self-biased,LVDS-output comparators (ADCMP604)
ARx12
Zarlink
Comp.
Opto-Rx Measurementsfor Pixel Upgrade
Sender / Receiver Setup
Agilent 8110Apulse/patterngenerator
AOH (TOB type)
AOH test setup
Tektronix DSA70804 Scope
Receiverboards
Opto-Rx Measurementsfor Pixel Upgrade
Test A – Unbalanced Periodal Signals
• 40 MHz with variable duty cycle (Ton/Tperiod)
• Considerable distortions up to misinterpretation due to threshold imbalance
• Bad result. However: This is a very unrealistic situation…
0 1 1 0 0 0 0 0 0 1 1 0
Example: 25% duty cyclerepresents repetitive unbalanced 1100 0000 code
Ton Tperiod
Code SenderOpt_Head(analog) ARx12 Zarlink
1111 0000 50.0% 49.8% 47.3% 50.1%
1100 0000 25.0% 25.6% 32.7% 35.3%
1000 0000 12.5% 12.4% 27.0% ---
Receiver
Opto-Rx Measurementsfor Pixel Upgrade
Test B – Balanced PRBS @ 320Mb/s with Sequence of 0s or 1s
• 15000 words of programmable pattern filled with PRBS14 (=balanced)
• Programming 1s (or 0s) from the beginning of the pattern until remaining PRBS bits become corrupted
• Amazing result:
– Zarlink tolerates ~700 consecutive 1s (or 0s) without effect on subsequent pattern
– With more than ~700 same symbols, subsequent single bits deteriorate or vanish completely (symmetric behavior)
– ARx12 even tolerates ~3000 consecutive 1s
• Perfectly suitable for pixel system, where even 20 consecutive 1s or 0s are extremely unlikely
Opto-Rx Measurementsfor Pixel Upgrade
Test C – Eye Diagram @ 320Mb/s (1)
• Optical Head (analog)
• Limited rise time (mostly due to pattern generator)
• Stable timing
• Solid eye opening
Opto-Rx Measurementsfor Pixel Upgrade
Test C – Eye Diagram @ 320Mb/s (2)
• Zarlink (digital)
• Perfectly fine
• High bandwidth(Zarlink can do 1.6Gb/s)
Opto-Rx Measurementsfor Pixel Upgrade
Test C – Eye Diagram @ 320Mb/s (3)
• ARx12+comparator (digital)
• Narrow opening withbest settings of pulse generator (amplitude),AOH (offset) and Rx12(offset)
• Unusable with non-optimal settings(where Zarlink still works perfectly well)
Opto-Rx Measurementsfor Pixel Upgrade
Test Conclusions
• ARx12 performance is marginal – even on a lab test bench in a noise-free environment
• Needs careful tuning of parameters in order to work
• Hence we don’t recommend its use in a production system
• Zarlink works very well – but is not a commercial product
• Normally 850nm, this engineering sample has 1310nm photodiode
• Francois is in contact with manufacturer to see if we can get 200 pcs. of 1310nm wavelength version
• H. Steininger has proposal to recover the phase for the 320MHz digital data stream at deserializer board on pxFED
Opto-Rx Measurementsfor Pixel Upgrade
Modification of Pixel-FED (1)
New daughter board(instead of 3 ADC cards)including Zarlink receiver
• Don’t need to remove current ARx12 allowseasy swapping betweenold and new systems
• Need new front panelin any case
• Keep single slot size
• Keep VME base board
Opto-Rx Measurementsfor Pixel Upgrade
Modification of Pixel-FED (2)
Old ADC card
New daughter board
Zarlink (mountedon daughter board)
Front panel
VME board
Need higher connectors than nowAvailable from different vendor (samples ordered for compatibility tests)
OLD
NEW
ARx12
ARx12
CMS Upgrade Workshop @ CERNMay 14, 2009
W. Bertl PSI
• Situation at present• 32 cables → layers 1+2
(192 ROCs)• 32 cables → layer 3 (128
to 192 ROCs)
• New Proposed Layout• 32 cables → layers 1+4
(320 ROCs)• 32 cables → layers 2+3
(256 to 320 ROCs)
Required
Current / cable
Iana Idig
A A
Max 4.88 8.51
Min 3.25 4.35
average 4.57 6.96
st.dev.[%] 12.47 20.39
(calculated for luminosity = 1034)
Required
Current / cable
Iana Idig
A A
Max 8.13 11.59
Min 6.50 9.05
average 7.72 10.99
st.dev.[%] 9.19 9.42
Power for BPix Phase-1Number of Power cables won’t change!
CMS Upgrade Workshop @ CERNMay 14, 2009
W. Bertl PSI
Bpix Operation Parameters
BPix 2008 | BPix 2013Luminosity 1 x 1034 1 x 1034 2 x 1034 5 x 1034
Power Dissipation 1612 W | 2598 2919 3883 W
Analog Voltage 1.7 V | 1.7 V
Digital Voltage 2.5 V | 2.5 V
Analog Current 293 A | 494 494 494 A
Digital Current 446 A | 703 832 1217 A
CMS Upgrade Workshop @ CERNMay 14, 2009
W. Bertl PSI
CAEN A4603 Power Supplies
Present Limitations
Voltage: Set Point (max.) Full Range Output
Analog 2.3 V 5.7 V
Digital 3.0 V 6.9 V
Current:
Analog 6 A ~ 6 A
Digital 15 A ~ 15 A
Power (single PSU): each line individually both lines loaded
Analog 33 W 28 W
Digital 99 W 88 W
116 W
CMS Upgrade Workshop @ CERNMay 14, 2009
W. Bertl PSI
Required (max.)* Possible at present
(1034 luminosity)
Full Voltage: Analog 7.5 V 5.7 V
Digital 7.5 V 6.9 V
Current: Analog 9 A 6 A
Digital 13 A 14.5 A
Power: Analog < 68 W 28 W
Digital < 98 W 88 W
166 W !!! 116 W
* < 10% contingency included
8 modules in a crate exceed 48V supply capacity by 30% !
Total Power needed: 7.1kW
Power loss in cables: 4.5 kW
A4603 Requirements
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