suppression of cosix induced leakage current using novel capping process … · 2002. 10. 4. · a...

Suppression of Suppression of CoSix CoSix Induced Leakage Induced Leakage Current using Novel Capping Process for Current using Novel Capping Process for SubSub--0.100.10µµm node SRAM Cell technologym node SRAM Cell technology

Hyung-Shin. Kwon, et al.

Advanced Technology DevelopmentSamsung Electronics Co. Ltd.

Contents Contents

Introduction

Experimental

Electrical Characteristics

Conclusion

Key Issues in High Speed SRAMKey Issues in High Speed SRAM

• Low Resistance Characteristics

• Low Junction Leakage Current

• Ultra-shallow Junction

Stable & Optimal Stable & Optimal CoSixCoSix Process Process is Strongly Required !!is Strongly Required !!

CoSixCoSix btw. Gate Patterns btw. Gate Patterns at Subat Sub--100nm Node100nm Node

• CoSix Local thinning in ~80nm space

• Poor step coverage of stop layer for contact etch

Induce Induce CoSixCoSix pitting at the bottom pitting at the bottom of contact.of contact.

Fabrication Process FlowFabrication Process Flow• STI• Gate Oxide (Oxynitride, Tgox=2.0nm)• Gate Poly: 200nm• Sidewall Spacer: 60nm• N+/P Junction Formation (As+, 40KeV)• Activation (1000ºC, 30sec)• Co Deposition : Co 8nm & TiN 10nm• 1st RTS & Selective wet strip• Capping layer Deposition as contact etch stopper• 2nd RTS & ILD CMP• Contact lithography and W-Plug• Local interconnect W-damascene• Contact and Metal

Experimental Split ConditionExperimental Split Condition

ILD

1st RTSSelective Wet strip

ILD

PE-SiOxNy Stacked layer TiN capping No capping

PE-SiOxNy30nm

LP-Si3N4 15nm

ILD

Selective Wet strip

ILD

PE-SiOxNy15nm

Sputtered TiN 10nm

No Capping

2nd RTS

LP-Si3N4 30nm

LP-Si3N4 30nm

Capping layer Characteristics Capping layer Characteristics

Film PECVD-SiOxNy

Sputtered TiN

LPCVD-Si3N4

Thickness(Å) 300 100 300

Deposition Chemical Gas

SiH4/N2O /NH3/N2

Ti rich TiN

SiCl2H2/NH3

Deposition Rate (Å /min) ~3185 ~60 6~6.5

Deposition Temperature(°C) 400 100 680

Uniformity (%) 1~1.5% < 5% < 1%

Step Coverage at A/R=1.25 68.5% 86% 98%

Junction Leakage (area)Junction Leakage (area)

10-16 10-15 10-14 10-131

5

20406080

95

99

N+/P junction

Cum

ulat

ive

Prob

abili

ty(%

)

Leakage Current(A/um2)

PECVD SiOxNy Stacked layer TiN Capping No capping layer

ILKG is independent on Capping layers.

Junction Leakage (peripheral)Junction Leakage (peripheral)

10-16 10-15 10-14 10-131

5

20406080

95

99

N+/P junction

No capping layer

Capping layer

Leakage Current(A/um2)

Cum

ulat

ive

Prob

abili

ty(%

)

ILKG depends on the presence of Capping layers.

No capping layer after 2No capping layer after 2ndnd RTS RTS

Pitting

Pitting = rough interfaces CoSix/Si-Sub → ILKG

““Capping layer Capping layer →→ good morphologygood morphologydue to reduced surface energydue to reduced surface energy””

SRAM Cell StructureSRAM Cell Structure

Contact (B/L, Vss)

Pitting

– B/L & Vss Contact is located in the narrowedspace between gate patterns

Co Co Silicide Silicide Pitting ModelPitting Model

(a)PE-SiOxNy (b)Stacked layer

Contact hole etch

PE-SiON 30nm

After 2nd silicidation

After 1st silicidation CoSix thinning

Stacked Layer

A/R(a/b)=1.25

a

b

Stacked Layer TEM ViewStacked Layer TEM View

PECVD-SiOxNy

LPCVD-Si3N4

100nm

Borderless Contact LeakageBorderless Contact Leakage

-0.04 -0.02 0.00 0.02 0.04 0.0610-15

10-14

10-13

10-12

10-11

Borderless ContactContact in N+ active

Le

akag

e C

urre

nt(A

/con

tact

)

Contacts Overlap Field(um)

PECVD SiOxNy Stacked layer TiN Capping No capping layer

No Capping > TiN > SiON > Stacked Layer

Cell B/L Contact Leakage CurrentCell B/L Contact Leakage Current

10-14 10-13 10-12 10-11 10-10 10-9 10-8 10-725

20406080

95

99

PE-SiOxNy

Capping

Stacked layer

Area:0.10¡¿0.10um 2

TiN

No capping

C

umul

ativ

e Pr

obab

ility

(%)

B/L Contact Leakage Current(A/contact)

SiON >> Stacked Layer, TiN > No Capping

No Capping No Capping vs TiNvs TiN Capping Capping layer Sheet Resistancelayer Sheet Resistance

5.5 5.6 5.7 5.8 5.9 6.0 6.1 6.2 6.3 6.4 6.51

5

20406080

95

99

(removal after 2nd RTS) TiN Capping

No capping layer

Cum

ulat

ive

Prob

abili

ty(%

)

Sheet resistance(§Ù/¡à)

Additional selective wet strip →CoSi2thickness loss

∴ Rs ↑

Cell Bit Line Contact ResistanceCell Bit Line Contact Resistance

– Rc is independent on the stopping layers.

0 10 20 30 40 50 60 70 80 90 1001

5

20406080

95

99Area=0.10¡¿0.10um2

B/L Contact Resistance (§Ù)

C

umul

ativ

e Pr

obab

ility

(%)

PECVD SiOxNy Stacked layer TiN Capping No capping layer

A Novel Capping Process For A Novel Capping Process For SubSub--100nm node SRAM100nm node SRAM

• Suppression of Co silicide Pittings

• Low Junction Leakage Current

• Enhancement of etch process window

- A good step coverage of LPCVD Si3N4

- Capping Effect of PECVD SiOXNY