string instructions of 8086

MOV AX,5000 H MOV DS,AXMOV SI,2500HMOV AX,6000HMOV ES,AXMOV DI,2500HCLDMOV CX,0004HREPNE CMPSB DS:[SI] - ES:[DI] and increment DI and SI (REPNE) HLT

MEMORY SOURCE

CONTENT MEMORYDEST

CONTENT

52500 42 62500 98

52501 45 62501 34

52502 34 62502 34

52503 23 62503 23

(CX=0004h) (DS=5000h)(SI=2500h)(DI=2500h)(ES=6000h)• 1st time REPNE CMPSB

DS:[SI] - ES:[DI] i.e. [52500]-[62500] i.e. 42-98(NE) SI =2501 and DI = 2501

CX=0003h(this is cos of REP prefix)• 2ND time REP CMPSB DS:[SI] - ES:[DI] i.e. [52501]-[62501] i.e. 45-34(NE) SI =2502 and DI = 2502

CX=0002h(this is cos of REP prefix)• 3rd Time REPNE CMPSBDS:[SI] - ES:[DI] i.e. [52502]-[62502] i.e. 34-34(E) SI =2503 and DI = 2503

CX=0001h(this is cos of REP prefix)• 4TH Time REPNE CMPSB will not happen cos locations are no

longer NE

STOSB AL=>ES:[DI] After string opr, if DF = 0, then DI is Incremented by 1and viceversa

STOSW AX=>ES:[DI]TO BE SPECIFICAL=>ES:[DI]AH=>ES:[DI+1]IF DF = 0, then DI is incremented by ??2If DF = 1, then DI is decremented by 2

BYTE WISE STRING INSTRUCTION WORD WISE STRING INSTRUCTION

STOSB STOSW

LODSB LODSW

MOVSB MOVSW

SCASB SCASW

CMPSB CMPSW

REP String instructions can handle at a time one byte or one word, but tohandle large block of data, REP prefix is used with CX as a counter

TypesREPdec CX by 1 and repeat that stringinstruction if CX is non zero. Otherwise control continues sequentially

REPNE/REPNZdec CX by 1 and repeat that string instruction if CX is non zero AND if that string inst.Produced non – zero result. Otherwise control continues sequentially

REPE/REPZdec CX by 1 and repeat that string instruction if CX is non zero AND if that string inst.Produced zero result. Otherwise control continues sequentially

LOOP It is used to execute series of instructions for a given number of times and thatnumber of times is stored in CXTypesLOOP AGAINdec CX by 1 and transfer control to the instruction having label AGAIN if CX is non zero.Otherwise control continues sequentially

LOOPNE/LOOPNZdec CX by 1 and transfer control to the instruction having label AGAIN if CX is non zeroAND if previous instruction produced non zero result. Otherwise control continuessequentially

LOOPE/LOOPZdec CX by 1 and transfer control to the instruction having label AGAIN if CX is non zeroAND if previous instruction produced zero result. Otherwise control continuessequentially

Addressing mode Mnemonic Segment for memory access

Symbolic representation

IMMEDIATE

Addressing mode Mnemonic Segment for memory access

Symbolic representation

IMMEDIATE MOV AX,1000

Addressing mode Mnemonic Segment for memory access

Symbolic representation

IMMEDIATE MOV AX,1000 CODE

Addressing mode Mnemonic Segment for memory access

Symbolic representation

IMMEDIATE MOV AX,1000 CODE AH<=10, AL<=00

Addressing mode Mnemonic Segment for memory access

Symbolic representation

IMMEDIATE MOV AX,1000 CODE AH<=10, AL<=00

REGISTER

Addressing mode Mnemonic Segment for memory access

Symbolic representation

IMMEDIATE MOV AX,1000 CODE AH<=10, AL<=00

REGISTER MOV DX,CX

Addressing mode Mnemonic Segment for memory access

Symbolic representation

IMMEDIATE MOV AX,1000 CODE AH<=10, AL<=00

REGISTER MOV DX,CX WITHIN THE CPU

Addressing mode Mnemonic Segment for memory access

Symbolic representation

IMMEDIATE MOV AX,1000 CODE AH<=10, AL<=00

REGISTER MOV DX,CX WITHIN THE CPU

DX<=CX

Addressing mode Mnemonic Segment for memory access

Symbolic representation

IMMEDIATE MOV AX,1000 CODE AH<=10, AL<=00

REGISTER MOV DX,CX WITHIN THE CPU

DX<=CX

DIRECT

Addressing mode Mnemonic Segment for memory access

Symbolic representation

IMMEDIATE MOV AX,1000 CODE AH<=10, AL<=00

REGISTER MOV DX,CX WITHIN THE CPU

DX<=CX

DIRECT MOV AL,[2000]

Addressing mode Mnemonic Segment for memory access

Symbolic representation

IMMEDIATE MOV AX,1000 CODE AH<=10, AL<=00

REGISTER MOV DX,CX WITHIN THE CPU

DX<=CX

DIRECT MOV AL,[2000] DATA

Addressing mode Mnemonic Segment for memory access

Symbolic representation

IMMEDIATE MOV AX,1000 CODE AH<=10, AL<=00

REGISTER MOV DX,CX WITHIN THE CPU

DX<=CX

DIRECT MOV AL,[2000] DATA AL<=[2000]

Addressing mode Mnemonic Segment for memory access

Symbolic representation

IMMEDIATE MOV AX,1000 CODE AH<=10, AL<=00

REGISTER MOV DX,CX WITHIN THE CPU

DX<=CX

DIRECT MOV AL,[2000] DATA AL<=[2000]

REGISTER INDIRECT

Addressing mode Mnemonic Segment for memory access

Symbolic representation

IMMEDIATE MOV AX,1000 CODE AH<=10, AL<=00

REGISTER MOV DX,CX WITHIN THE CPU

DX<=CX

DIRECT MOV AL,[2000] DATA AL<=[2000]

REGISTER INDIRECT

MOV AX,[SI]

JMP [DI]

INC BYTEPTR[BP]

DEC WORDPTR[BX]

Addressing mode Mnemonic Segment for memory access

Symbolic representation

IMMEDIATE MOV AX,1000 CODE AH<=10, AL<=00

REGISTER MOV DX,CX WITHIN THE CPU

DX<=CX

DIRECT MOV AL,[2000] DATA AL<=[2000]

REGISTER INDIRECT

MOV AX,[SI] DATA

JMP [DI] DATA

INC BYTEPTR[BP] STACK

DEC WORDPTR[BX] DATA

Addressing mode Mnemonic Segment for memory access

Symbolic representation

IMMEDIATE MOV AX,1000 CODE AH<=10, AL<=00

REGISTER MOV DX,CX WITHIN THE CPU

DX<=CX

DIRECT MOV AL,[2000] DATA AL<=[2000]

REGISTER INDIRECT

MOV AX,[SI] DATA AL<=[SI]AH<=[SI+1]

JMP [DI] DATA

INC BYTEPTR[BP] STACK

DEC WORDPTR[BX] DATA

Addressing mode Mnemonic Segment for memory access

Symbolic representation

IMMEDIATE MOV AX,1000 CODE AH<=10, AL<=00

REGISTER MOV DX,CX WITHIN THE CPU

DX<=CX

DIRECT MOV AL,[2000] DATA AL<=[2000]

REGISTER INDIRECT

MOV AX,[SI] DATA AL<=[SI]AH<=[SI+1]

JMP [DI] DATA IP <={[DI+1] [DI]}

INC BYTEPTR[BP] STACK

DEC WORDPTR[BX] DATA

Addressing mode Mnemonic Segment for memory access

Symbolic representation

IMMEDIATE MOV AX,1000 CODE AH<=10, AL<=00

REGISTER MOV DX,CX WITHIN THE CPU

DX<=CX

DIRECT MOV AL,[2000] DATA AL<=[2000]

REGISTER INDIRECT

MOV AX,[SI] DATA AL<=[SI]AH<=[SI+1]

JMP [DI] DATA IP <={[DI+1] [DI]}

INC BYTEPTR[BP] STACK [BP]<=[BP]+1

DEC WORDPTR[BX] DATA

Addressing mode Mnemonic Segment for memory access

Symbolic representation

IMMEDIATE MOV AX,1000 CODE AH<=10, AL<=00

REGISTER MOV DX,CX WITHIN THE CPU

DX<=CX

DIRECT MOV AL,[2000] DATA AL<=[2000]

REGISTER INDIRECT

MOV AX,[SI] DATA AL<=[SI]AH<=[SI+1]

JMP [DI] DATA IP <={[DI+1] [DI]}

INC BYTEPTR[BP] STACK [BP]<=[BP]+1

DEC WORDPTR[BX] DATA {[BX+1][BX]}<={[BX+1][BX]} – 1

Addressing mode Mnemonic Segment for memory access

Symbolic representation

RELATIVE INDEXED(RELATIVE REGISTER INDIRECT)

MOV AX,[SI+6]

JMP [DI+6]

RELATIVE BASED(RELATIVE REGISTER INDIRECT)

MOV AX,[BP+2]

JMP [BX+2]

Addressing mode Mnemonic Segment for memory access

Symbolic representation

RELATIVE INDEXED(RELATIVE REGISTER INDIRECT)

MOV AX,[SI+6] DATA

JMP [DI+6] DATA

RELATIVE BASED(RELATIVE REGISTER INDIRECT)

MOV AX,[BP+2] STACK

JMP [BX+2] DATA

Addressing mode Mnemonic Segment for memory access

Symbolic representation

RELATIVE INDEXED(RELATIVE REGISTER INDIRECT)

MOV AX,[SI+6] DATA AL<=[SI+6], AH<=[SI+7]

JMP [DI+6] DATA

RELATIVE BASED(RELATIVE REGISTER INDIRECT)

MOV AX,[BP+2] STACK

JMP [BX+2] DATA

Addressing mode Mnemonic Segment for memory access

Symbolic representation

RELATIVE INDEXED(RELATIVE REGISTER INDIRECT)

MOV AX,[SI+6] DATA AL<=[SI+6], AH<=[SI+7]

JMP [DI+6] DATA IP <={[DI+7] [DI+6]}

RELATIVE BASED(RELATIVE REGISTER INDIRECT)

MOV AX,[BP+2] STACK

JMP [BX+2] DATA

Addressing mode Mnemonic Segment for memory access

Symbolic representation

RELATIVE INDEXED(RELATIVE REGISTER INDIRECT)

MOV AX,[SI+6] DATA AL<=[SI+6], AH<=[SI+7]

JMP [DI+6] DATA IP <={[DI+7] [DI+6]}

RELATIVE BASED(RELATIVE REGISTER INDIRECT)

MOV AX,[BP+2] STACK AL<=[BP+2], AH<=[BP+3]

JMP [BX+2] DATA

Addressing mode Mnemonic Segment for memory access

Symbolic representation

RELATIVE INDEXED(RELATIVE REGISTER INDIRECT)

MOV AX,[SI+6] DATA AL<=[SI+6], AH<=[SI+7]

JMP [DI+6] DATA IP <={[DI+7] [DI+6]}

RELATIVE BASED(RELATIVE REGISTER INDIRECT)

MOV AX,[BP+2] STACK AL<=[BP+2], AH<=[BP+3]

JMP [BX+2] DATA IP <={[BP+3] [BP+2]}

Addressing mode Mnemonic Segment for memory access

Symbolic representation

BASED AND INDEXED

MOV AX,[BX+SI]

JMP [BX+DI]

INC BYTEPTR[BP+SI]

DEC WORDPTR[BP+DI]

Addressing mode Mnemonic Segment for memory access

Symbolic representation

BASED AND INDEXED

MOV AX,[BX+SI] DATA

JMP [BX+DI] DATA

INC BYTEPTR[BP+SI] STACK

DEC WORDPTR[BP+DI]

STACK

Addressing mode Mnemonic Segment for memory access

Symbolic representation

BASED AND INDEXED

MOV AX,[BX+SI] DATA AL<=[BX+SI], AH<=[BX+SI+1]

JMP [BX+DI] DATA

INC BYTEPTR[BP+SI] STACK

DEC WORDPTR[BP+DI]

STACK

Addressing mode Mnemonic Segment for memory access

Symbolic representation

BASED AND INDEXED

MOV AX,[BX+SI] DATA AL<=[BX+SI], AH<=[BX+SI+1]

JMP [BX+DI] DATA IP <={[BX+DI+1] [BX+DI]}

INC BYTEPTR[BP+SI] STACK

DEC WORDPTR[BP+DI]

STACK

Addressing mode Mnemonic Segment for memory access

Symbolic representation

BASED AND INDEXED

MOV AX,[BX+SI] DATA AL<=[BX+SI], AH<=[BX+SI+1]

JMP [BX+DI] DATA IP <={[BX+DI+1] [BX+DI]}

INC BYTEPTR[BP+SI] STACK [BP+SI]<=[BP+SI]+1

DEC WORDPTR[BP+DI]

STACK

Addressing mode Mnemonic Segment for memory access

Symbolic representation

BASED AND INDEXED

MOV AX,[BX+SI] DATA AL<=[BX+SI], AH<=[BX+SI+1]

JMP [BX+DI] DATA IP <={[BX+DI+1] [BX+DI]}

INC BYTEPTR[BP+SI] STACK [BP+SI]<=[BP+SI]+1

DEC WORDPTR[BP+DI]

STACK {[BP+DI+1][BP+DI]} <={[BP+DI+1][BP+DI]} - 1

Addressing mode Mnemonic Segment for memory access

Symbolic representation

BASED AND INDEXED WITH DISPLACEMENT (RELATIVE BASED AND INDEXED]

MOV AX,[BX+SI+5]

JMP [BX+DI+5]

INC BYTEPTR[BP+SI+5]

DEC WORDPTR[BP+DI+5]

Addressing mode Mnemonic Segment for memory access

Symbolic representation

BASED AND INDEXED WITH DISPLACEMENT (RELATIVE BASED AND INDEXED]

MOV AX,[BX+SI+5] DATA

JMP [BX+DI+5] DATA

INC BYTEPTR[BP+SI+5]

STACK

DEC WORDPTR[BP+DI+5]

STACK

Addressing mode Mnemonic Segment for memory access

Symbolic representation

BASED AND INDEXED WITH DISPLACEMENT (RELATIVE BASED AND INDEXED]

MOV AX,[BX+SI+5] DATA AL<=[BX+SI+5], AH<=[BX+SI+6]

JMP [BX+DI+5] DATA

INC BYTEPTR[BP+SI+5]

STACK

DEC WORDPTR[BP+DI+5]

STACK

Addressing mode Mnemonic Segment for memory access

Symbolic representation

BASED AND INDEXED WITH DISPLACEMENT (RELATIVE BASED AND INDEXED]

MOV AX,[BX+SI+5] DATA AL<=[BX+SI+5], AH<=[BX+SI+6]

JMP [BX+DI+5] DATA IP <={[BX+DI+6] [BX+DI+5]}

INC BYTEPTR[BP+SI+5]

STACK

DEC WORDPTR[BP+DI+5]

STACK

Addressing mode Mnemonic Segment for memory access

Symbolic representation

BASED AND INDEXED WITH DISPLACEMENT (RELATIVE BASED AND INDEXED]

MOV AX,[BX+SI+5] DATA AL<=[BX+SI+5], AH<=[BX+SI+6]

JMP [BX+DI+5] DATA IP <={[BX+DI+6] [BX+DI+5]}

INC BYTEPTR[BP+SI+5]

STACK [BP+SI+5]<=[BP+SI+5]+1

DEC WORDPTR[BP+DI+5]

STACK

Addressing mode Mnemonic Segment for memory access

Symbolic representation

BASED AND INDEXED WITH DISPLACEMENT (RELATIVE BASED AND INDEXED]

MOV AX,[BX+SI+5] DATA AL<=[BX+SI+5], AH<=[BX+SI+6]

JMP [BX+DI+5] DATA IP <={[BX+DI+6] [BX+DI+5]}

INC BYTEPTR[BP+SI+5]

STACK [BP+SI+5]<=[BP+SI+5]+1

DEC WORDPTR[BP+DI+5]

STACK {[BP+DI+6][BP+DI+5]} <={[BP+DI+6][BP+DI+5]} - 1

Addressing mode Mnemonic Segment for memory access

Symbolic representation

STRING MOVSB

IMPLICIT CLD

Addressing mode Mnemonic Segment for memory access

Symbolic representation

STRING MOVSB EXTRA, DATA

IMPLICIT CLD WITHIN THE CPU

Addressing mode Mnemonic Segment for memory access

Symbolic representation

STRING MOVSB EXTRA, DATA ES:[DI]<=DS:[SI]IF DF=0, INCREMENT SI AND DI BY 1IF DF =1, DECREMENT SI AND DI BY 1

IMPLICIT CLD WITHIN THE CPU

DF = 0

IDENTIFY THE ADDRESSING MODE

MOV AH,47MOV AH,[BP+2]MOV AL,[BP+SI]STDMOV AH,BLMOV DX,[2002]