soi detector r&d
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Snowmass 2005
SOI detector R&D
Massimo Caccia, Antonio BulgheroniUniv. dell’Insubria / INFN Milano (Italy)
M. Jastrzab, M. Koziel, W. Kucewicz, H. Niemiec*, M. SaporAGH – University of Science and Technology – Krakow – Poland
P. Grabiec, K. Kucharski, J. Marczewski, D. TomaszewskiInstitute of Electron Technology – Warsaw – Poland
*Scholarship holder of the Foundation for Polish Science
Antonio Bulgheroni on behalf of the SOI workgroup
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Principle of SOI Monolithic detector
Integration of a fully depleted p+-n junction matrix and the readout
electronics in a wafer bonded SOI substrate
Detector Handle wafer
High resistive (> 4 kcm, FZ)
400 µm thick
conventional p+-n matrix
Electronics Device layer
Low resistive (9-13 cm, CZ)
1.5 µm thick
Standard CMOS technology
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SOI pros and contra
PROS Monolithic: no need of any
hydridization and consequent thickness reduction
Fully depleted: high SNR, high sensitivity
Standard CMOS electronics: both type of transistors
Custom technology: will never become obsolete
CONTRA Non standard technology:
requires dedicated process in non standard foundries
Thermal budget: high temperature processes for the electronics parts clash against the low thermal budget required for high quality p+-n junctions.
Low availability of SOI substrate: with detector grade handle wafer
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SOI development
Phase 1: Technology definition
Phase 2: Small area prototype
Phase 3: Full area fully functional sensor
2005200420032002
Developed by the SUCIMA collaboration within a EC project for medical applications. US Patent Application no. PCT/IT2002/000700
•Electronics design by the AGH team•Technological implementation at IET on a 3µm production line
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Phase 1: technology definition
Two steps procedure:
1. Definition of the technology file test structure
2. Readout electronics functionality AMS 0.6 multi-project run
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SOI test structures / 1
Structure for technological parameter extraction
Structure for electronics circuit characterization Detector
prototypes (8x8 pixels) w/ and w/o charge injection pad.
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SOI test structures / 2
gds 428 nS @ VGS=2.3 V for W/L = 20/10
gds 196 nS @ VGS=2.3 V for W/L = 40/20
0,00E+00
5,00E-05
1,00E-04
1,50E-04
2,00E-04
2,50E-04
3,00E-04
3,50E-04
4,00E-04
0,00 0,50 1,00 1,50 2,00 2,50 3,00 3,50 4,00 4,50 5,00VG [V]
ID
[A]
VDS=3.8V 20/10 VDS=3.8V 40/20 VDS=1.7V 20/10 VDS=1.7V 40/20
VDS=1V 20/10 VDS=1V 40/20 VDS=0.3V 20/10 VDS=0.3V 40/20
Comperison of output characteristics of transistors with W/L=20/10 and 40/20
0,00E+00
5,00E-05
1,00E-04
1,50E-04
2,00E-04
2,50E-04
3,00E-04
0,00 1,00 2,00 3,00 4,00 5,00
VDS [V]
ID
[A]
VG=4,3V 20/10 VG=4,3V 40/20 VG=3,3V 20/10 VG=3,3V 40/20
VG=2,3V 20/10 VG=2,3V 40/20 VG=1,3V 20/10 VG=1,3V 40/20
Transfer and output characteristics of NMOS with W/L=20/10 and 40/20
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Electronics functionality assessment / 1
Readout electronics part in AMS 0.6 2 fully functional matrices 16x16
pixels with different pixel addressing circuitries
1 smaller 5x5 matrix with only the analog part
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Measured noise ~ 1.78 mV
20 mV signal injected every fourth pixel
Test of the CDS processing with 5 threshold.
Electronics functionality assessment / 2
1.66
1.68
1.7 After reset
[V]
1.65
1.7
1.75 After integration time
[V]
0.020.030.04
[V]
After CDS processing
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 150
0.02
0.04After supression of signals below threshold
Column
[V]
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Phase 2: small area prototype / 1
Basic 3 trans. architecture only slightly modified with PMOS Single cell dimensions are 140 x
122 m2.
Matrix dimensions: 1120 m x 976 m
Not surrounded by guardring
VDET
VSS
VDD
IN
RES
ROW_SEL
COL
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Phase 2: small area prototype / 2
Charged particle sensitivity with radioactive sources
Linearity and dynamic range with infrared laser
90Sr
Linearity
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Phase 3: full area sensor design
No dead area, preserved
pitch
Functionally independent quarter of the
detector
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Sensor characteristics
Detector cavity
Input protectio
n
Input MOSFET Guard
128 x 128 pixels on 2.4 x 2.4 cm2 sensitive area
Dimensions: 150x150 m2
Input capacitance similar to test structures similar signals levels
Larger PMOS in transmission gate improved linearity
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Preliminary results
Sensor sensitivity observed with laser pointer and α particles.
Dynamic range up to 100 MIP Charge to voltage gain 3.6 mV/fC Problems with production yield: only
¾ of the best chip fully functional Readout frequency up to 4 MHz
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Future plans / 1
Proof of principle accomplished taking advantage of IET.
Full cost 650 k€ (of which for personnel 200 k€)
Partner foundry with a primitive 3µm production line
Looking for another partner (device company) with a more advanced technology
Contacts positively established with Hamamatsu 1 year ago
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Next formal meeting with Hamamatsu during Pixel 2005 conference in September with the definition of a development plan
Interests from many groups: INFN, AGH, KEK, BONN
Future plans / 2
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Silicon on Insulator technology
90Sr
CMOS electronics High resistivity fully depleted sensitive
volume Not standard process Development started off 3 years ago Proof of principle accomplished ILC dedicated development being
defined with a partner company
INSUBRIA + INFN (ITALY), IET + AGH (POLAND)
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