slaac systems level applications of adaptive computing delivering acs technology to applications...

SLAACSystems Level Applications of

Adaptive ComputingDelivering ACS Technology to Applications

DARPA/ITO Adaptive Computing Systems PI Meeting

San Juan, Puerto Rico

October 6-8, 1999

Project Lead: Bob Parker

Presented by: Steve CragoInformation Sciences Institute

Steve CragoUSC INFORMATION SCIENCES INSTITUTE Page 2

Outline

Overview Hardware Status “Customer” Applications

Electronic Countermeasures Analysis (ECMA) Sonar Beamforming

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SLAAC Objectives

Define a system-level open, distributed heterogeneous adaptive computing architecture

Design, develop and evolve scalable reference platforms implementing the adaptive systems architecture

Validate the approach by deploying reference platforms in multiple defense application domains SAR ATR Sonar Beamforming ECMA Others

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Team Members: USC/ISI (Lead), BYU, UCLA, VT, Sandia National Labs, LANL, LM-GES

Significant reduction in power, weight, volume,and cost for several challenging DoD embeddedapplications

•Demonstrate 500x reduction in system volume on SAR/ATR ACS challenge•Demonstrate First forward looking, 50,000 beam towed array on ACS sonar challenge

Utilizing Three Phases of Adaptive Computing Components Large Current Generation FPGAs

Rapid Reconfigurable and/or Fine Grain FPGAsHybrid FPGAs

Integrating Multiple Constituent Technologies

Gigabit/Sec NetworkingModular Adaptive Compute ModulesNetwork Based Runtime Control SoftwareAlgorithm Analysis/ CompilationTools

Developing Reference PlatformsFlight Worthy Deployable SystemLow Cost Researchers Kit

‘97 ‘98 ‘99

Lab Demo of an ACS implemented SAR ATR algorithm

Embedded SAR ATR Demo of ACS HW (Clear, 1Mpixel/s, 6TT)First Generation of Reference Platforms

‘01

Embedded SAR ATR Demo (CC&D, 1Mpixel/s, 6TT)

‘00

Embedded SAR ATR Demo(CC&D, 10Mpixel/s, 6TT)

System Level Applications of Adaptive Computing

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SLAAC Affiliates

ACSResearch

Community

BYU

SandiaUCLA

ISI

SandiaSAR/ATR

NVL

IRATR

NUWC

SonarBeamforming

LANL

Ultra Wide- Band Coherent RF

LANL Multi-

dimensional

ImageProcessing

Lockheed

Martin

App

licat

ions

Electronic

Counter-

measures

VT

LANL

LM-GES

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SLAAC Technologies

SLAACSLAAC

ApplicationApplicationMappingMapping

ModuleModuleGeneratorsGenerators

RuntimeRuntimeSystemSystemHardwareHardware

Hosts

Nodes

Network

T72

T72SLAAC is delivering ACS technology!SLAAC is delivering ACS technology!

- SLAAC, WILDFORCE, WILD-ONE, ...- SLAAC, WILDFORCE, WILD-ONE, ...

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Technology Integration

ACS technology is targeting SLAAC!ACS technology is targeting SLAAC!

SLAACSLAAC

JHDLJHDL(CDs available)(CDs available)

DebuggerDebuggerEnvironmentsEnvironments(Boardscope)(Boardscope)

ModuleModuleGeneratorsGenerators

(FOA compiler,(FOA compiler,DEFACTO)DEFACTO)

JBitsJBits

NewNewChipsChips

(Virtex,(Virtex,ACS chips)ACS chips)

RuntimeRuntimeExtensionsExtensions

(Debug,(Debug,DynamicDynamic

Reconfiguration)Reconfiguration)

DesignDesignEnvironmentsEnvironments

(Adapters,(Adapters,Cameron,Cameron,Matlab)Matlab)

I/OI/O(QC-64,(QC-64,Myrinet)Myrinet)

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SLAAC Node Architecture

VHDL model available Model Technologies Synopsys

JHDL port coming soon…

X0

IF

X1 X2

SRAMSRAM

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SLAAC-1 Board

Simulation Environment Drivers

Windows NT driver runningLinux driver coming soon…

Runtime systemSLAAC API (http://www.ccm.ece.vt.edu/slaac/)

SynthesisSynplicitySynopsys

X0

IF

X1 X2

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SLAAC-1 Status

Working hardware! Transitioned to university labs Designs running in all FPGAs

Order from

Order from

lcarter@east.isi.edu

lcarter@east.isi.edu

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SLAAC-2 Board

PowerPC Bus A

X0

IF

X1 X2

PowerPC Bus B

X0

IF

X1 X2

72/

72/

40/

40/

Simulation Environment Drivers

VxWorks

Runtime systemSLAAC API

SynthesisSynplicitySynopsys

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SLAAC-2 Status

Working hardware! Delivered to Lockheed Martin-GES Designs running in all FPGAs

Order from

Order from

lcarter@east.isi.edu

lcarter@east.isi.edu