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SIMULATION OF NANOCLUSTER CARBON THIN FILM TRANSISTOR (TFT)
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CHAPTER 7
SIMULATION OF NANOCLUSTER CARBON THIN
FILM TRANSISTOR (TFT)
7.1 Introduction
The objective of this chapter is to simulate the thin–film transistor
using nanocluster carbon (NC) thin film as an active channel layer. This
involves the generation of the nanocluster carbon (NC) thin film based
TFT structures using TCAD software SILVACO. Simulations of the same
to obtain the electrical characteristics and hence the extraction of
electrical parameters like threshold voltage, mobility and ON/OFF ratio
will enable in determining the operational characteristics of the device.
7.2 TFT structures
The usual TFT structures are shown in figure 7.1 and hydrogenated
amorphous silicon (a–Si: H) is the initial sample [240]. It comprises the a–
Si: H channel, a gate dielectric, and source, drain, and gate contacts. Since
the semiconductor layer is formed by deposition, more defects and
crystalline imperfections in the layer than in the corresponding single
crystal semiconductor are expected complicating the transport processes in
the TFT.
Concept of thin film transistors is very similar to crystalline MOS
devices. The conductivity between drain and source terminals is
modulated by an applied gate voltage. Gate voltage controls band bending
and Fermi level at the semiconductor insulator interface (increases
amount of Fermi energy level). Positive voltage at the gate causes
accumulation of electrons at front interface and formation of the high
conductivity channel [241].
Unlike crystalline silicon MOSFET’s, there are many different
device geometries possible for thin film transistors. Top gate, bottom gate
(also known as “inverted”) is two classes of devices. The latter has its gate
electrode and gate dielectric below a–Si: H or nc–Si: H active layer and the
SIMULATION OF NANOCLUSTER CARBON THIN FILM TRANSISTOR (TFT)
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former has above the active layer. These two cases subdivided into
coplanar and staggered devices, giving a total of four types of basic
structures illustrated in Figure 7.1.The term coplanar/staggered describes
the location of source and drain contacts relative to the gate. In coplanar
case, the source and drain contacts are on the same side of the active
region as the gate contact while the source and drain contacts are on the
opposite side of the gate contact in staggered case. The most popular
configuration for a–Si: H is inverted staggered. The bottom–gate, or
inverted staggered, is a widely used process for a–Si: H TFTs, and it is the
best TFT structure to adopt nc–Si: H TFT for most of current a–Si: H TFT
applications without modification of production lines.
FIGURE.7.1 Different structures of TFT [224].
7.3 Basic characteristic of TFT
The transfer characteristic of a TFT is illustrated in Figure 7.2 as
drain current versus gate bias characteristic. It can be seen that there are
three regions of operation. For small gate voltages, the Fermi level lies in
SIMULATION OF NANOCLUSTER CARBON THIN FILM TRANSISTOR (TFT)
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the deep states and it can be assumed that the energy bands are close to
flat band condition. By increasing the positive gate bias, band bending
close to the gate dielectric interface occurs, meaning the Fermi level moves
up through the deep states and towards the band tail states [243,244]. In
this state, most of induced electrons are trapped in deep defect states, a
small but negligible amount of electrons may occupy tail states yield a
small amount of drain current. This operation region is called the sub
threshold region shown in figure 7.2. The sub–threshold region continues
until the deep states are filled up with electrons and the concentration of
electrons in tail states exceeds that of trapped electrons in deep states. As
the gate bias continues to increase, it finally exceeds a threshold voltage
(Vth) which implies the Fermi level now lies in the tail states [243,244].
.
FIGURE 7.2 Basic characteristic of a TFT [242].
For gate–source bias (Vgs) higher than Vth, the TFT is operating in
the above threshold regime, i.e. ON state. To simplify characterization, the
square root equation which is used for MOSFET characterization can be
adopted. In linear region, where the source–drain bias (Vds) is equal or
lower than Vgs – Vth, the source–drain current (Ids) is linearly proportional
to Vds, which can be expressed as:
SIMULATION OF NANOCLUSTER CARBON THIN FILM TRANSISTOR (TFT)
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(7.1)
where W, L and Cgate are the TFT channel width, length and gate
capacitance, respectively. When Vds = Vgs – Vth, the accumulation channel
is pinched off near the drain and drain current saturates and becomes
independent from Vds. For Vds≥ Vgs – Vth, TFTs operate in saturation
regime. The Ids in the saturation regime is written by
(7.2)
7.4 Electrical parameter extraction
Extraction of performance factors from experimental data is
demonstrated in this section. The field effect mobility, threshold voltage,
sub–threshold slope, on/off ratio and transconductance can be obtained
from the TFT transfer characteristics as shown in Figure 7.3.
To extract field effect mobility and threshold voltage, a linear fit on
square root of the linear scale data is required as shown in figure 7.3. The
threshold voltage can be determined by extrapolating the linear fit down
to the x–intercept. To obtain the field effect mobility, first, the slope of the
linear fit must be drawn from the most accurate linear fit data. The slope
can be interpreted analytically and given by
(7.3)
2
2
dsdsthgsgateEFds
VVVV
L
WCI
2
thgsgateEFds VVL
WCI
2/1
2
1
L
WC
Vd
Idslope gateEF
gs
ds
SIMULATION OF NANOCLUSTER CARBON THIN FILM TRANSISTOR (TFT)
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FIGURE 7.3 Linear fit on square root of transfer characteristics of a TFT [228].
Thus, the field effect mobility can be determined by
(7.4)
7.5 Defect states modeling
Defect states of the nanocluster carbon thin films have been
simulated using ATLAS package in SILVACO TCAD[245]. In ATLAS
module of SILVACO package, the material parameter which defines
properties of amorphous or polycrystalline silicon is the defect density of
defect states (DOS) in the silicon material [245].Figure 7.4 illustrates a
typical density of defect states (DOS) distribution for a–Si:H, poly–Si and
nc–Si:H [241] . Here, each half of the gap is broken into two sections: deep
and tail states. Again, states in the upper half of the band gap are
acceptor–like (i.e., positive when unoccupied and neutral when occupied by
electrons), and states in the lower half of the gap are donor–like (i.e.,
neutral when unoccupied and negative when occupied by electrons) [241].
gate
EFWC
Lslope
22
SIMULATION OF NANOCLUSTER CARBON THIN FILM TRANSISTOR (TFT)
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FIGURE 7.4 Illustration of the density of defect states within the band gap of
disordered materials such as amorphous, polycrystalline, and nano crystalline
silicon [241].
To accurately describe behavior of the TFTs made of the disordered
materials, two deep states are modeled using a gaussian distribution
expressed by,
(7.5)
(7.6)
where E is the trap energy and the subscripts G, A, and D stand for
gaussian, acceptor, and donor states, respectively. For gaussian
distributions, the density of defect states is described by its total density of
states (NGA and NGD), its characteristic decay energy (WGA and WGD),
and its peak energy/peak distribution (EGA and EGD) [245]. Two tail
states are modeled using an exponential distribution, in which,
2
expGA
GA
GAGAw
EEnEg
2
expGD
GD
GDGDw
EEnEg
SIMULATION OF NANOCLUSTER CARBON THIN FILM TRANSISTOR (TFT)
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(7.7)
(7.8)
where the subscript T stands for tail states, EC is the conduction band
energy, and EV is the valence band energy. For exponential tail
distributions, the density of defect states is described by its conduction
and valence band edge intercept densities (NTA and NTD), and by its
characteristic decay energy (WTA and WTD) [244,245]. Therefore, the
total density of defect states in the band gap is given by
g(E)=gTA(E)+gTD(E)+gGA(E)+gGD(E) (7.9)
7.6 Results and discussion
Various characteristic and parameters extracted from the
simulation of nanocluster carbon thin film TFT have been discussed.
Variations in characteristics and parameters have been observed in the
simulation.
7.6.1 Generation of TFT structure using SILVACO TCAD
In the first part ATHENA [245] module is used to construct the
geometry and doping of a TFT device. The starting substrate is defined as
silicon dioxide to emulate the flat panel display glass. The transistor is
simulated with a metal gate on the bottom and a gate insulator made from
oxide and nitride. A nanocluster carbon thin film layer is deposited to act
as the channel region. A heavily doped layer is placed on top to become the
source/drain regions. Single crystal silicon or poly silicon could be used
equally well at this stage. However, the important electrical properties of
the material are set in ATLAS. Metal for the source/drain contacts is then
applied. Some of the lightly doped silicon layer is also removed. This final
TA
C
TATAw
EEnEg exp
TD
V
TDTDw
EEnEg exp
SIMULATION OF NANOCLUSTER CARBON THIN FILM TRANSISTOR (TFT)
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etch separates the source and drain. The final stage in ATHENA is to
define the electrodes for use in ATLAS. The ATLAS part of this file is used
to simulate the gate voltage bias with fixed drain bias. Before the biasing
is applied it is first necessary to set all the relevant material parameters.
In the 2–D ATLAS device simulator[245], the semiconductor
parameters are defaulted for silicon which uses a drift diffusion model. We
need to specify the required parameters of nanocluster carbon thin film as
an active channel layer in a bottom gate TFT structure for nanocluster
carbon based TFT simulation. Following dimensions are used for 2–D
simulation using ATLAS software. This structure corresponds to
experimentally studied sample [246] for nc–Si:H TFT. Dimensions are
channel length L = 4µm, channel width W = 8 µm, active channel layer
thickness, NC=100 nm and gate insulator thickness =200nm of a TFT
structure for two–dimensional (2D) device. Silicon dioxide is used as a
dielectric. Other dimensions considered have been stated. Bottom gate
simulated structure is shown in Figure 7.5.
FIGURE 7.5 Structure used for two dimensional simulation of bottom gate TFT
using SILVACO TCAD.
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7.6.2 Output characteristics of simulated TFTs
Figure 7.6 represents the output characteristics for different values
of gate bias. The drain current reaches a saturation value after a certain
drain bias which is in accordance with the square root model. The drain
current increases with increase in gate to source voltage. The drain
current reaches a saturation value at different Vds for different Vgs.
0 5 10 15 20 25 30
0.0
2.0x10-4
4.0x10-4
6.0x10-4
8.0x10-4
1.0x10-3
Vgs=5V
Vgs=10V
Vgs=15V
Vgs=20V
Vgs=25V
VDS(V)
IDS
(A)
FIGURE 7.6 Simulated drains characteristics for different values of gate to
source bias.
7.6.3 Transfer characteristic of simulated TFT
In a TFT, as gate bias is increased the carriers induced in the
inversion get trapped in the defect sates and potential barrier increases in
height. As the gate bias is increased, the traps become full and the
additional carriers will now reduce the depletion width on either side.
Therefore, a threshold voltage is required to overcome the potential
barrier created due to defect states and to drive the thin film transistor in
ON state. Figure 7.7 represents the transfer curves of a nanocluster
SIMULATION OF NANOCLUSTER CARBON THIN FILM TRANSISTOR (TFT)
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carbon TFT. Standard FET theory has been used to extract the channel
threshold voltage. The threshold voltages calculated are 1.5V,4V,5V,12V
and 15V for the defect densities of 1016 cm-3 eV-1 ,1017 cm-3 eV-1, 1018 cm-3
eV-1,1019 cm-3 eV-1 and 1020 cm-3 eV-1, respectively. The transfer
characteristics revealed an ON/OFF ratio varies from 104 to 108 for a
nanocluster carbon thin film transistor. ON/OFF ratio is quite good
because of presence of low defects as compared to the a–si: H. These
values are quite comparable to a–si: H, a–C: H values [10, 247, 248]. The
drain current is clearly modulated by the applied gate bias.
-10 0 10 20 30
10-12
10-11
10-10
10-9
10-8
10-7
10-6
10-5
10-4
10-3
DOS=1e16
DOS=1e17
DOS=1e18
DOS=1e19
DOS=1e20
IDS
(A)
VGS(V)
FIGURE 7.7 Transfer characteristic of nanocluster carbon thin film TFT.
The nanocluster carbon thin film transistor operates by
accumulation in the channel enhancement mode. The observed increase in
the drain current as the gate voltage is ramped positively is therefore
consistent with field induced movement of the Fermi level closer to the
conduction band in the upper surface of the nanocluster carbon film layer.
As the hopping conductivity is sensitive to the density of localized states,
the observed increase in the drain current for positive applied gate
SIMULATION OF NANOCLUSTER CARBON THIN FILM TRANSISTOR (TFT)
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voltages can be attributed to the movement of the Fermi level from
conduction band tail states towards extended states.
TABLE 7.1 Threshold voltage, ON/OFF ratio, saturation mobility and sub–
threshold slope values of nanocluster carbon thin films TFT under
different DOS values with silicon dioxide dielectric
DOS=1x1020 DOS=1x1019 DOS=1x1018 DOS=1x1017 DOS=1x1016
Threshold
Voltage(V) ~15 ~12 ~5 4 1.5
ON/OFF ratio ~104 ~107 ~108 ~108 ~108
Saturation
Mobility(cm2/V-
sec)
2.9x10-6 6.6x10-3 0.04655 0.0384 0.0477
Sub-threshold
slope(V/decade) 0.44 0.40 0.36 0.33 0.23
Unit of DOS is in cm-3 eV-1 . Vds=10 V.
7.7 Nanocluster carbon thin film TFT with silicon nitride (SiN) as an
dielectric
Nanocluster carbon thin film with silicon dielectric has been
simulated keeping the same geometry as discussed earlier in section the
structure discussed in section 7.6.1. Only dielectric has been changed to
SiN. The defect densities of the films have been varied from 1x1016 to
1x1020 cm-3 eV-1 and obtained from SCLC measurements. The Transfer
characteristic and plot of square root of Ids vs Vgs is shown in Figure 7.8.
SIMULATION OF NANOCLUSTER CARBON THIN FILM TRANSISTOR (TFT)
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(a)
(b)
FIGURE7.8 (a) Transfer characteristic and (b) plot of square root of Ids vs
Vgs of nanocluster carbon thin films.
Threshold voltage varies from 3.6 to 10 V and maximum for
maximum density of states. More defects means more states has to be
filled, increasing the threshold voltage requirements. The ON/OFF ratio
found to be varying 109 to 1011 which are four to six orders higher.
Mobilities of the films varies from 3.2 x 10–3 cm2 V-1 s-1 to 12.2 x 10–2 cm2
SIMULATION OF NANOCLUSTER CARBON THIN FILM TRANSISTOR (TFT)
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V-1 s-1 .This value is maximum for minimum density of the film 1x1016 cm-3
eV-1 and found to nearly constant for DOS values of 1x1016,1x1017 and
1x1018 cm-3 eV-1.
Table 7.2 Threshold voltage, ON/OFF ratio, saturation mobility and sub–
threshold slope values of nanocluster carbon thin films TFT under
different DOS values with silicon nitride dielectric
DOS=1x1020 DOS=1x1019 DOS=1x1018 DOS=1x1017 DOS=1x1016
Threshold
Voltage(V) ~10 ~6 ~4 3.8 3.6
ON/OFF ratio ~109 ~1010 ~1010 ~1011 ~1011
Saturation
Mobility(cm2/V-
sec)x 10–2
0.32 10.6 11.8 12.1 12.2
Sub-threshold
slope(V/decade) ~1 ~0.67 0.61 0.60 ~0.6
Unit of DOS is in cm-3 eV-1 . Vds=10 V.
Sub–threshold value varies from 0.6 V/decade to 1 V/decade. A
device characterized by steep sub–threshold slope exhibits a faster
transition between off (low current) and on (high current) states. All these
values are enumerated in Table 7.2. All these values have to be
corroborated with experimental values, which is a part of future work.
7.8 Summary
The semiconducting nature of nanocluster carbon thin film makes it
good alternative material for active channel layer for TFT applications.
Nanocluster carbon based TFT has been simulated successfully using
SILVACO TCAD software. In transfer characteristics it revealed a
performance factors–threshold voltage varies from 1.5V to 15 V and
maximum ON/OFF ratio of 108. With SiN dielectric, device performance
increases like ON/OFF ratio increases to ~9 to ~ 11 orders. Similarly,
threshold voltage decreases from 10 V to 3.6 V as DOS decreases in the
nanocluster carbon thin films.
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