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Si7155DPwww.vishay.com Vishay Siliconix
S17-1810-Rev. A, 11-Dec-17 1 Document Number: 75769For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENTARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
P-Channel 40 V (D-S) MOSFETFEATURES• TrenchFET® Gen III p-channel power MOSFET
• Industry leadership RDS(on) specifications(as of November 2017)
• 100 % Rg and UIS tested
• Material categorization:for definitions of compliance please see www.vishay.com/doc?99912
APPLICATIONS• Adapter and charger switch
• Load switch
• Motor drive control
• DC/DC converter
• Power supplies
• Battery management
Notesa. Package limitedb. Surface mounted on 1" x 1" FR4 boardc. t = 10 sd. See solder profile (www.vishay.com/doc?73257). The PowerPAK 1212-8 is a leadless package. The end of the lead terminal is exposed
copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection
e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless componentsf. Maximum under steady state conditions is 54 °C/Wg. TC = 25 °C
PRODUCT SUMMARYVDS (V) -40RDS(on) max. () at VGS = 10 V 0.0036RDS(on) max. () at VGS = 4.5 V 0.0046Qg typ. (nC) 107ID (A) -100 a, g
Configuration Single
PowerPAK® SO-8 Single
Top View
1
6.15 mm
5.15 mm
Bottom View
4G
3S
2S
1S
D8
D6
D7
D5
S
G
D
P-Channel MOSFET
ORDERING INFORMATIONPackage PowerPAK SO-8Lead (Pb)-free and halogen-free Si7155DP-T1-GE3
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)PARAMETER SYMBOL LIMIT UNITDrain-source voltage VDS -40
VGate-source voltage VGS ± 20
Continuous drain current (TJ = 150 °C)
TC = 25 °C
ID
-100 a
A
TC = 70 °C -100 a
TA = 25 °C -31 b, c
TA = 70 °C -24.8 b, c
Pulsed drain current (t = 100 μs) IDM -200
Continuous source-drain diode currentTC = 25 °C
IS-94.5
TA = 25 °C -5.6 b, c
Single pulse avalanche currentL = 0.1 mH
IAS -50Single pulse avalanche energy EAS 125 mJ
Maximum power dissipation
TC = 25 °C
PD
104
WTC = 70 °C 66.6TA = 25 °C 6.25 b, c
TA = 70 °C 4 b, c
Operating junction and storage temperature range TJ, Tstg -55 to +150°C
Soldering recommendations (peak temperature) c 260
THERMAL RESISTANCE RATINGSPARAMETER SYMBOL TYPICAL MAXIMUM UNIT
Maximum junction-to-ambient b t 10 s RthJA 15 20°C/W
Maximum junction-to-case (drain) Steady state RthJC 0.9 1.2
Si7155DPwww.vishay.com Vishay Siliconix
S17-1810-Rev. A, 11-Dec-17 2 Document Number: 75769For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENTARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Notesa. Pulse test; pulse width 300 μs, duty cycle 2 %b. Guaranteed by design, not subject to production testingStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Static
Drain-source breakdown voltage VDS VGS = 0 V, ID = -250 μA -40 - - V
VDS temperature coefficient VDS/TJ ID = -10 mA - -43 -mV/°C
VGS(th) temperature coefficient VGS(th)/TJ ID = -250 μA - 5 -
Gate-source threshold voltage VGS(th) VDS = VGS, ID = -250 μA -1 - -2.3 V
Gate-source leakage IGSS VDS = 0 V, VGS = ± 20 V - - 100 nA
Zero gate voltage drain current IDSSVDS = -40 V, VGS = 0 V - - -1
μAVDS = -40 V, VGS = 0 V, TJ = 70 °C - - -15
On-state drain current a ID(on) VDS -10 V, VGS = -10 V -40 - - A
Drain-source on-state resistance a RDS(on)VGS = -10 V, ID = -20 A - 0.0030 0.0036
VGS = -4.5 V, ID = -20 A - 0.0038 0.0046
Forward transconductance a gfs VDS = -15 V, ID = -20 A - 95 - S
Dynamic b
Input capacitance Ciss
VDS = -20 V, VGS = 0 V, f = 1 MHz
- 12 900 -
pFOutput capacitance Coss - 930 -
Reverse transfer capacitance Crss - 1370 -
Total gate charge QgVDS = -20 V, VGS = -10 V, ID = -20 A - 220 330
nCVDS = -20 V, VGS = -4.5 V, ID = -20 A
- 107 161
Gate-source charge Qgs - 23.7 -
Gate-drain charge Qgd - 37.2 -
Gate resistance Rg f = 1 MHz 0.8 2 3.5
Turn-on delay time td(on)
VDD = -20 V, RL = 1 , ID -20 A,VGEN = -10 V, Rg = 1
- 15 30
ns
Rise time tr - 43 86
Turn-off delay time td(off) - 125 250
Fall time tf - 85 170
Turn-on delay time td(on)
VDD = -20 V, RL = 1 , ID -20 A,VGEN = -4.5 V, Rg = 1
- 55 110
Rise time tr - 185 370
Turn-off delay time td(off) - 130 260
Fall time tf - 117 235
Drain-Source Body Diode Characteristics
Continuous source-drain diode current IS TC = 25 °C - - -94.5A
Pulse diode forward current ISM - - -200
Body diode voltage VSD IS = -5 A, VGS = 0 V - -0.73 -1.1 V
Body diode reverse recovery time trr
IF = -20 A, di/dt = 100 A/μs,TJ = 25 °C
- 41 82 ns
Body diode reverse recovery charge Qrr - 39 78 nC
Reverse recovery fall time ta - 22 -ns
Reverse recovery rise time tb - 19 -
Si7155DPwww.vishay.com Vishay Siliconix
S17-1810-Rev. A, 11-Dec-17 3 Document Number: 75769For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENTARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Output Characteristics
On-Resistance vs. Drain Current and Gate Voltage
Gate Charge
Transfer Characteristics
Capacitance
On-Resistance vs. Junction Temperature
0
20
40
60
80
100
0 1 2 3 4 5
2nd
line
I D-D
rain
Cur
rent
(A)
VDS - Drain-to-Source Voltage (V)2nd line
VGS = 10 V thru 4 V
VGS = 3 V
VGS = 2 V
10
100
1000
10000
0.0020
0.0026
0.0032
0.0038
0.0044
0.0050
0 16 32 48 64 80
Axis Title
1st l
ine
2nd
line
2nd
line
RD
S(o
n)-O
n-R
esis
tanc
e (Ω
)
ID - Drain Current (A)2nd line
VGS = 10 V
VGS = 4.5 V
10
100
1000
10000
0
2
4
6
8
10
0 50 100 150 200 250
Axis Title
1st l
ine
2nd
line
2nd
line
VG
S-G
ate-
to-S
ourc
e V
olta
ge (V
)
Qg - Total Gate Charge (nC)2nd line
VDS = 10 V, 20 V, 30 V
ID = 20 A
0
30
60
90
120
150
0 1 2 3 4 5
2nd
line
I D-D
rain
Cur
rent
(A)
VGS - Gate-to-Source Voltage (V)2nd line
TC = 25 °C
TC = -55 °C
TC = 125 °C
10
100
1000
10000
0
3400
6800
10 200
13 600
17 000
0 5 10 15 20 25
Axis Title
1st l
ine
2nd
line
2nd
line
C-C
apac
itanc
e (p
F)
VDS - Drain-to-Source Voltage (V)2nd line
Crss
Coss
Ciss
10
100
1000
10000
0.6
0.8
1.0
1.2
1.4
1.6
1.8
-50 -25 0 25 50 75 100 125 150
Axis Title1s
t lin
e2n
d lin
e
2nd
line
RD
S(o
n)-O
n-R
esis
tanc
e (N
orm
aliz
ed)
TJ - Junction Temperature (°C)2nd line
ID = 20 A
VGS = 4.5 V
VGS = 10 V
Si7155DPwww.vishay.com Vishay Siliconix
S17-1810-Rev. A, 11-Dec-17 4 Document Number: 75769For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENTARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Source-Drain Diode Forward Voltage
On-Resistance vs. Gate-to-Source Voltage
Threshold Voltage
Single Pulse Power, Junction-to-Ambient
Safe Operating Area, Junction-to-Ambient
10
100
1000
10000
0.01
0.1
1
10
100
0 0.2 0.4 0.6 0.8 1.0
Axis Title
1st l
ine
2nd
line
2nd
line
I S-S
ourc
e C
urre
nt (A
)
VSD - Source-to-Drain Voltage (V)2nd line
TJ = 150 °C TJ = 25 °C
10
100
1000
10000
0
0.004
0.008
0.012
0.016
0.020
0 2 4 6 8 10
Axis Title
1st l
ine
2nd
line
2nd
line
RD
S(o
n)-O
n-R
esis
tanc
e (Ω
)
VGS - Gate-to-Source Voltage (V)2nd line
TJ = 25 °C
ID = 20 A
TJ = 125 °C
10
100
1000
10000
-0.5
-0.2
0.1
0.4
0.7
1.0
-50 -25 0 25 50 75 100 125 150
Axis Title
1st l
ine
2nd
line
2nd
line
VG
S(th
)- V
aria
nce
(V)
TJ - Temperature (°C)2nd line
ID = 250 μA
ID = 5 mA
10
100
1000
10000
0
100
200
300
400
500
0.001 0.01 0.1 1 10
Axis Title
1st l
ine
2nd
line
2nd
line
Pow
er (W
)
Time (s)2nd line
10
100
1000
10000
0.01
0.1
1
10
100
1000
0.01 0.1 1 10 100
Axis Title
1st l
ine
2nd
line
2nd
line
I D-D
rain
Cur
rent
(A)
VDS - Drain-to-Source Voltage (V)(1) VGS > minimum VGS at which RDS(on) is specified
IDM limited
Limited by RDS(on)
(1)
TA = 25 °CSingle pulse BVDSS limited
100 ms
10 ms
1 ms
100 μs
10 s
DC
1 s
ID limited
Si7155DPwww.vishay.com Vishay Siliconix
S17-1810-Rev. A, 11-Dec-17 5 Document Number: 75769For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENTARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Current Derating a
Power, Junction-to-Case Power, Junction-to-Ambient
Notea. The power dissipation PD is based on TJ max. = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package limit
10
100
1000
10000
0
30
60
90
120
150
0 25 50 75 100 125 150
Axis Title
1st l
ine
2nd
line
2nd
line
I D-D
rain
Cur
rent
(A)
TC - Case Temperature (°C)2nd line
Limited by Package
10
100
1000
10000
0
25
50
75
100
125
0 25 50 75 100 125 150
Axis Title
1st l
ine
2nd
line
2nd
line
Pow
er (W
)
TC - Case Temperature (°C)2nd line
10
100
1000
10000
0
0.6
1.2
1.8
2.4
3.0
0 25 50 75 100 125 150
Axis Title
1st l
ine
2nd
line
2nd
line
Pow
er (W
)
TA - Ambient Temperature (°C)2nd line
Si7155DPwww.vishay.com Vishay Siliconix
S17-1810-Rev. A, 11-Dec-17 6 Document Number: 75769For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENTARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Normalized Thermal Transient Impedance, Junction-to-Ambient
Normalized Thermal Transient Impedance, Junction-to-Case
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and reliability data, see www.vishay.com/ppg?75769.
10
100
1000
10000
0.01
0.1
1
0.0001 0.001 0.01 0.1 1 10 100 1000
Axis Title
1st l
ine
2nd
line
Nor
mal
ized
Effe
ctiv
e Tr
ansi
ent
Ther
mal
Impe
danc
e
Square Wave Pulse Duration (s)2nd line
0.1
0.05
0.02Single pulse
Duty Cycle = 0.5
0.2
PDM
t1t2
1. Duty cycle, D = 2. Per unit base = RthJA = 54 °C/W3. TJM - TA = PDMZthJA
(t)
4. Surface mounted
t1t2
Notes:
10
100
1000
10000
0.01
0.1
1
0.0001 0.001 0.01 0.1 1 10
Axis Title
1st l
ine
2nd
line
Nor
mal
ized
Effe
ctiv
e Tr
ansi
ent
Ther
mal
Impe
danc
e
Square Wave Pulse Duration (s)2nd line
0.10.05
0.02
Single pulse
Duty Cycle = 0.5
0.2
Package Informationwww.vishay.com Vishay Siliconix
Revison: 13-Feb-17 1 Document Number: 71655
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENTARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
PowerPAK® SO-8, (Single/Dual)
DIM.MILLIMETERS INCHES
MIN. NOM. MAX. MIN. NOM. MAX.
A 0.97 1.04 1.12 0.038 0.041 0.044A1 - 0.05 0 - 0.002b 0.33 0.41 0.51 0.013 0.016 0.020c 0.23 0.28 0.33 0.009 0.011 0.013D 5.05 5.15 5.26 0.199 0.203 0.207
D1 4.80 4.90 5.00 0.189 0.193 0.197D2 3.56 3.76 3.91 0.140 0.148 0.154D3 1.32 1.50 1.68 0.052 0.059 0.066D4 0.57 typ. 0.0225 typ.D5 3.98 typ. 0.157 typ.E 6.05 6.15 6.25 0.238 0.242 0.246
E1 5.79 5.89 5.99 0.228 0.232 0.236E2 3.48 3.66 3.84 0.137 0.144 0.151E3 3.68 3.78 3.91 0.145 0.149 0.154 E4 0.75 typ. 0.030 typ.e 1.27 BSC 0.050 BSCK 1.27 typ. 0.050 typ.
K1 0.56 - - 0.022 - -H 0.51 0.61 0.71 0.020 0.024 0.028L 0.51 0.61 0.71 0.020 0.024 0.028
L1 0.06 0.13 0.20 0.002 0.005 0.008 0° - 12° 0° - 12°W 0.15 0.25 0.36 0.006 0.010 0.014M 0.125 typ. 0.005 typ.
ECN: S17-0173-Rev. L, 13-Feb-17DWG: 5881
3. Dimensions exclusive of mold flash and cutting burrs.
1.Notes
2Inch will govern.Dimensions exclusive of mold gate burrs.
Backside View of Single Pad
Backside View of Dual Pad
Detail Z
D
D1
D2
c
θA
θ
E1θ
D1
E2
D2e
b
1
2
3
4
H
4
3
2
1
θ1
2
3
4 b
L
D2
D3
(2x)
Z
A1
K1
K
D
E
W
L1
D5
E3
D4
E4
E4K
LHE2
D4
D5
M
E3
2
2
V I S H A Y S I L I C O N I X
Power MOSFETs Application Note AN821
PowerPAK® SO-8 Mounting and Thermal Considerations
AP
PL
ICA
TIO
N N
OT
E
Revision: 16-Mai-13 1 Document Number: 71622
For technical questions, contact: powermosfettechsupport@vishay.comTHIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
www.vishay.com
by Wharton McDanielMOSFETs for switching applications are now available withdie on resistances around 1 m and with the capability tohandle 85 A. While these die capabilities represent a majoradvance over what was available just a few years ago, it isimportant for power MOSFET packaging technology to keeppace. It should be obvious that degradation of a highperformance die by the package is undesirable. PowerPAKis a new package technology that addresses these issues.In this application note, PowerPAK’s construction isdescribed. Following this mounting information is presentedincluding land patterns and soldering profiles for maximumreliability. Finally, thermal and electrical performance isdiscussed.
THE PowerPAK PACKAGEThe PowerPAK package was developed around the SO-8package (figure 1). The PowerPAK SO-8 utilizes the samefootprint and the same pin-outs as the standard SO-8. Thisallows PowerPAK to be substituted directly for a standardSO-8 package. Being a leadless package, PowerPAK SO-8utilizes the entire SO-8 footprint, freeing space normallyoccupied by the leads, and thus allowing it to hold a largerdie than a standard SO-8. In fact, this larger die is slightlylarger than a full sized DPAK die. The bottom of the dieattach pad is exposed for the purpose of providing a direct,low resistance thermal path to the substrate the device ismounted on. Finally, the package height is lower than thestandard SO-8, making it an excellent choice forapplications with space constraints.
Fig. 1 PowerPAK 1212 Devices
PowerPAK SO-8 SINGLE MOUNTINGThe PowerPAK single is simple to use. The pin arrangement(drain, source, gate pins) and the pin dimensions are thesame as standard SO-8 devices (see figure 2). Therefore, thePowerPAK connection pads match directly to those of theSO-8. The only difference is the extended drain connectionarea. To take immediate advantage of the PowerPAK SO-8single devices, they can be mounted to existing SO-8 landpatterns.
Fig. 2
The minimum land pattern recommended to take fulladvantage of the PowerPAK thermal performance seeApplication Note 826, Recommended Minimum PadPatterns With Outline Drawing Access for Vishay SiliconixMOSFETs. Click on the PowerPAK SO-8 single in the indexof this document.
In this figure, the drain land pattern is given to make fullcontact to the drain pad on the PowerPAK package.
This land pattern can be extended to the left, right, and topof the drawn pattern. This extension will serve to increasethe heat dissipation by decreasing the thermal resistancefrom the foot of the PowerPAK to the PC board andtherefore to the ambient. Note that increasing the drain landarea beyond a certain point will yield little decreasein foot-to-board and foot-to-ambient thermal resistance.Under specific conditions of board configuration, copperweight and layer stack, experiments have found thatmore than about 0.25 in2 to 0.5 in2 of additional copper(in addition to the drain land) will yield little improvement inthermal performance.
Standard SO-8 PowerPAK SO-8
PowerPAK® SO-8 Mounting and Thermal Considerations
AP
PL
ICA
TIO
N N
OT
EApplication Note AN821
www.vishay.com Vishay Siliconix
Revision: 16-Mai-13 2 Document Number: 71622
For technical questions, contact: powermosfettechsupport@vishay.comTHIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
PowerPAK SO-8 DUALThe pin arrangement (drain, source, gate pins) and the pindimensions of the PowerPAK SO-8 dual are the same asstandard SO-8 dual devices. Therefore, the PowerPAKdevice connection pads match directly to those of the SO-8.As in the single-channel package, the only exception is theextended drain connection area. Manufacturers can likewisetake immediate advantage of the PowerPAK SO-8 dualdevices by mounting them to existing SO-8 dual landpatterns.
To take the advantage of the dual PowerPAK SO-8’sthermal performance, the minimum recommended landpattern can be found in Application Note 826,Recommended Minimum Pad Patterns With OutlineDrawing Access for Vishay Siliconix MOSFETs. Click on thePowerPAK 1212-8 dual in the index of this document.
The gap between the two drain pads is 24 mils. Thismatches the spacing of the two drain pads on thePowerPAK SO-8 dual package.
REFLOW SOLDERINGVishay Siliconix surface-mount packages meet solder reflowreliability requirements. Devices are subjected to solderreflow as a test preconditioning and are thenreliability-tested using temperature cycle, bias humidity,HAST, or pressure pot. The solder reflow temperature profileused, and the temperatures and time duration, are shown infigures 3 and 4.
For the lead (Pb)-free solder profile, seewww.vishay.com/doc?73257.
Fig. 3 Solder Reflow Temperature Profile
Fig. 4 Solder Reflow Temperatures and Time Durations
Ramp-Up Rate + 3 °C /s max.
Temperature at 150 - 200 °C 120 s max.
Temperature Above 217 °C 60 - 150 s
Maximum Temperature 255 + 5/- 0 °C
Time at MaximumTemperature 30 s
Ramp-Down Rate + 6 °C/s max.
260 °C
3 °C(max) 6 ° C/s (max.)
30 s
217 °C
150 s (max.)
Reflow Zone 60 s (min.)
Pre-Heating Zone
150 - 200 °C
Maximum peak temperature at 240 °C is allowed.
PowerPAK® SO-8 Mounting and Thermal Considerations
AP
PL
ICA
TIO
N N
OT
EApplication Note AN821
www.vishay.com Vishay Siliconix
Revision: 16-Mai-13 3 Document Number: 71622
For technical questions, contact: powermosfettechsupport@vishay.comTHIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
THERMAL PERFORMANCE
Introduction
A basic measure of a device’s thermal performanceis the junction-to-case thermal resistance, RthJC, or thejunction-to-foot thermal resistance, RthJF This parameter ismeasured for the device mounted to an infinite heat sink andis therefore a characterization of the device only, in otherwords, independent of the properties of the object to whichthe device is mounted. Table 1 shows a comparison ofthe DPAK, PowerPAK SO-8, and standard SO-8. ThePowerPAK has thermal performance equivalent to theDPAK, while having an order of magnitude better thermalperformance over the SO-8.
Thermal Performance on Standard SO-8 Pad Pattern
Because of the common footprint, a PowerPAK SO-8can be mounted on an existing standard SO-8 pad pattern.The question then arises as to the thermal performanceof the PowerPAK device under these conditions. Acharacterization was made comparing a standard SO-8 anda PowerPAK device on a board with a trough cut outunderneath the PowerPAK drain pad. This configurationrestricted the heat flow to the SO-8 land pads. The resultsare shown in figure 5.
Fig. 5 PowerPAK SO-8 and Standard SO-0 Land Pad Thermal Path
Because of the presence of the trough, this result suggestsa minimum performance improvement of 10 °C/W by usinga PowerPAK SO-8 in a standard SO-8 PC board mount.
The only concern when mounting a PowerPAK on astandard SO-8 pad pattern is that there should be no tracesrunning between the body of the MOSFET. Where thestandard SO-8 body is spaced away from the pc board,allowing traces to run underneath, the PowerPAK sitsdirectly on the pc board.
Thermal Performance - Spreading Copper
Designers may add additional copper, spreading copper, tothe drain pad to aid in conducting heat from a device. It ishelpful to have some information about the thermalperformance for a given area of spreading copper.
Figure 6 shows the thermal resistance of a PowerPAK SO-8device mounted on a 2-in. 2-in., four-layer FR-4 PC board.The two internal layers and the backside layer are solidcopper. The internal layers were chosen as solid copper tomodel the large power and ground planes common in manyapplications. The top layer was cut back to a smaller areaand at each step junction-to-ambient thermal resistancemeasurements were taken. The results indicate that an areaabove 0.3 to 0.4 square inches of spreading copper gives noadditional thermal performance improvement. Asubsequent experiment was run where the copper on theback-side was reduced, first to 50 % in stripes to mimiccircuit traces, and then totally removed. No significant effectwas observed.
Fig. 6 Spreading Copper Junction-to-Ambient Performance
TABLE 1 - DPAK AND POWERPAK SO-8EQUIVALENT STEADY STATE PERFORMANCE
DPAK PowerPAKSO-8
StandardSO-8
Thermal Resistance RthJC
1.2 °C/W 1 °C/W 16 °C/W
Si4874DY vs. Si7446DP PPAK on a 4-Layer BoardSO-8 Pattern, Trough Under Drain
Pulse Duration (sec)
)sttaw/
C( e cnadepmI
0.0001
0
1
50
60
10
100000.01
40
20
Si4874DY
Si7446DP
100
30
Rth vs. Spreading Copper(0 %, 50 %, 100 % Back Copper)
Spreading Copper (sq in)
)sttaw/
C( ecnadepmI
0.00
56
51
46
41
36
0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
0 %
50 %
100 %
PowerPAK® SO-8 Mounting and Thermal Considerations
AP
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www.vishay.com Vishay Siliconix
Revision: 16-Mai-13 4 Document Number: 71622
For technical questions, contact: powermosfettechsupport@vishay.comTHIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SYSTEM AND ELECTRICAL IMPACT OFPowerPAK SO-8In any design, one must take into account the change inMOSFET RDS(on) with temperature (figure 7).
Fig. 7 MOSFET RDS(on) vs. Temperature
A MOSFET generates internal heat due to the currentpassing through the channel. This self-heating raises thejunction temperature of the device above that of the PCboard to which it is mounted, causing increased powerdissipation in the device. A major source of this problem liesin the large values of the junction-to-foot thermal resistanceof the SO-8 package.
PowerPAK SO-8 minimizes the junction-to-board thermalresistance to where the MOSFET die temperature is veryclose to the temperature of the PC board. Consider twodevices mounted on a PC board heated to 105 °C by othercomponents on the board (figure 8).
Fig. 8 Temperature of Devices on a PC Board
Suppose each device is dissipating 2.7 W. Using thejunction-to-foot thermal resistance characteristics of thePowerPAK SO-8 and the standard SO-8, the dietemperature is determined to be 107 °C for the PowerPAK(and for DPAK) and 148 °C for the standard SO-8. This is a2 °C rise above the board temperature for the PowerPAKand a 43 °C rise for the standard SO-8. Referring to figure 7,a 2 °C difference has minimal effect on RDS(on) whereas a43 °C difference has a significant effect on RDS(on).
Minimizing the thermal rise above the board temperature byusing PowerPAK has not only eased the thermal design butit has allowed the device to run cooler, keep rDS(on) low, andpermits the device to handle more current than the sameMOSFET die in the standard SO-8 package.
CONCLUSIONSPowerPAK SO-8 has been shown to have the same thermalperformance as the DPAK package while having the samefootprint as the standard SO-8 package. The PowerPAKSO-8 can hold larger die approximately equal in size to themaximum that the DPAK can accommodate implying nosacrifice in performance because of package limitations.
Recommended PowerPAK SO-8 land patterns are providedto aid in PC board layout for designs using this newpackage.
Thermal considerations have indicated that significantadvantages can be gained by using PowerPAK SO-8devices in designs where the PC board was laid out forthe standard SO-8. Applications experimental data gavethermal performance data showing minimum andtypical thermal performance in a SO-8 environment, plusinformation on the optimum thermal performanceobtainable including spreading copper. This furtheremphasized the DPAK equivalency.
PowerPAK SO-8 therefore has the desired small sizecharacteristics of the SO-8 combined with the attractivethermal characteristics of the DPAK package.
0.6
0.8
1.0
1.2
1.4
1.6
1.8
-50 -25 0 25 50 75 100 125 150
V GS = 10 V I D = 23 A
On-Resistance vs. Junction Temperature
T J - Junction Temperature (°C)
)dezilamro
N(( ecnatsise
R-nO -
R)no(
SD
)
0.8 °C/W
107 °C
PowerPAK SO-8
16 C/W
148 °C
Standard SO-8
PC Board at 105 °C
Application Note 826Vishay Siliconix
Document Number: 72599 www.vishay.comRevision: 21-Jan-08 15
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RECOMMENDED MINIMUM PADS FOR PowerPAK® SO-8 Single
0.17
4
(4.4
2)
Recommended Minimum PadsDimensions in Inches/(mm)
0.260
(6.61)
0.024(0.61)
0.15
4
(3.9
1)
0.150
(3.81)
0.05
0
(1.2
7)
0.050
(1.27)
0.032
(0.82)
0.040
(1.02)
0.026(0.66)
Return to IndexReturn to Index
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Revision: 08-Feb-17 1 Document Number: 91000
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