sequential logic circuit optimization
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Ashis Kumar ChandaMS (2014-15), Roll 343
Department of Computer Science and EngineeringUniversity of Dhaka
Submitted to:Prof. Hafiz Md. Hasan Babu
Logical Circuits Sequential Logical Circuits Finite State Machine Minimization Methods Applications Summary
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• We use a bit (binary digit), 0 or 1, to represent the state
0 (00)
1 (01)
2 (10)
3 (11)
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Combinational Logical Circuitso The logic level at the output depends on the
combination of logic levels present at the inputso It has no memory characteristic
Sequential Logical Circuitso The output follows a predetermined stateso It has memory characteristic
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The word “Sequential” means that things happen in a “sequence”
Why is it important?
Need to follow synchronous process using clock signal
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Output is dependent on the input and the record of the input or state
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What is Finite State Diagrams?o The behavioral view of sequential circuits at
logic level
Why will we express a circuit in Finite State Diagrams?o state diagrams encapsulate the traces that the
corresponding circuit can accept and produce
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oA set of primary input patterns, XoA set of primary output patterns, YoA set of states, SoA state transition functionoAn output transition function (Mealy
model, Moore model)
For a Mealy machine, each arc (transition) is labeled with an output value.
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The information in the state is typically written as q1q0 / Z
q1q0 indicates the inputs, Z indicates output
Ex: 01/1
A single input single output network that produces 1 if three consecutive 1's appear in the inputs.
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S1
S2 S3
S4
1
1
1
0
0 0
0, 1
For a Moore machine, each node (state) is labeled with an output value;
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Present state Next State for input 0,output
Next state for input 1, output
S1 S1 S0
S0 S0 S2
S2 S1 S0
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NOR
D FF
rr
xx
zz
Input Current State
Next State Output
0 S1 S2 1
0 S2 S1 0
1 S1 S1 0
1 S2 S1 0
r x Z
0 0 1
0 1 0
1 0 0
1 1 0
S1 S2
r/zr/z
r/zr/z
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NOR
D FF
rr
xx
zz
Input Current State
Next State Output
0 S1 S2 1
0 S2 S1 0
1 S1 S1 0
1 S2 S1 0
r x Z
0 0 1
0 1 0
1 0 0
1 1 0
S1 S2
0/10/1
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NOR
D FF
rr
xx
zz
r x Z
0 0 1
0 1 0
1 0 0
1 1 0
S1 S2
1/01/00/10/1
Input Current State
Next State Output
0 S1 S2 1
0 S2 S1 0
1 S1 S1 0
1 S2 S1 0
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NOR
D FF
rr
xx
zz
r x Z
0 0 1
0 1 0
1 0 0
1 1 0
S1 S2
1/01/00/10/1
0/00/0
Input Current State
Next State Output
0 S1 S2 1
0 S2 S1 0
1 S1 S1 0
1 S2 S1 0
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NOR
D FF
rr
xx
zz
r x Z
0 0 1
0 1 0
1 0 0
1 1 0
S1 S2
1/01/00/10/1
1/00/01/00/0
Input Current State
Next State Output
0 S1 S2 1
0 S2 S1 0
1 S1 S1 0
1 S2 S1 0
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Completely specified Incompletely specified FSM FSM
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Merge the equivalent states into a single stateTwo states are equivalent iff:oFor the same input, they have identical
outputsoFor the same input, the corresponding next
states are equivalent
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S3S1 S2
S4 S5
0/10/1
1/11/1
1/11/1
1/11/1
1/11/1
0/10/1
0/10/10/00/0
0/00/0
1/01/0
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Input Current State Next State Output
0 S1 S3 1
1 S1 S5 1
0 S2 S3 1
1 S2 S5 1
0 S3 S2 0
1 S3 S1 1
0 S4 S4 0
1 S4 S5 1
0 S5 S4 1
1 S5 S1 0
Output based partition -> {S1, S2} Next state based partition -> {{S1, S2}, {S3}, {S4}, {S5}}
{S3, S4}, {S5}}
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Output based partition
Next state based partition -> {{S1, S2}, {S3}, {S4}, {S5}}
S1, S2 S3, S4 S5
P1 P2 P3
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Input Current State Next State Output
0 S12 S3 1
1 S12 S5 1
0 S3 S12 0
1 S3 S12 1
0 S4 S4 0
1 S4 S5 1
0 S5 S4 1
1 S5 S12 0
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S3S12
S4 S5
1/01/0
0/00/0
0/00/01/11/1
1/11/1
1/11/1
0/10/1
0/10/1
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The optimization process will reduce the area of circuit.
So, we can save cost. It ensures better performance
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Computer memoryDelay and storage elementsFinite state machinesMinimizing ensures smaller circuit areaBetter performance from fewer number of
components
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Sequential logic circuit The minimization process Improvement in speed and cost Applications
Questions?
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Digital systems principles and applications oBy Tocci 2001
Synthesis And Optimization of Digital circuitso Giovani De Micheli
Digital Logic Design [Sequential circuits] oDr. Eng. Ahmed H. Madian
http://en.wikipedia.org/wiki/Moore_machine http://en.wikipedia.org/wiki/Mealy_machine
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