sequential circuits

Chapter

SequentialCircuits

Circuits• Combinational circuit

‣ The output depends only on the input

• Sequential circuit

‣ Has a state

‣ The output depends not only on the input but also on the state the circuit is in

Sequential circuit• Constructed from standard gates, but with

one or more feedback connections

• An unstable state is one that will change a few gate delays later because of the feedback connection

• A stable state is one that will persist indefinitely until the input changes

An unstable circuit.

A stable circuit.

a b dc

Figure 11.1

SR Latch• The SR latch has two stable states

• When SR = 00, output Q can be 0 or 1 depending on the state of the latch

• S = 1 sets ouput Q to 1

• R = 1 resets output Q to 0

Figure 11.2

Initial

Stability

Stable

Unstable

Stable

Figure 11.3

Initial

Stability

Stable

Figure 11.4

Figure 11.5

a b c d e

System clock• Controls the state transitions of all the

sequential circuits to happen at the same time

• Sequence of regularly spaced pulses with period T

Figure 11.6

Clocked SR flip-flop• Two AND gates that act as an enable

• Only when Ck is high can the S and R inputs affect the state of the flip-flop

• The effect is to digitize the time axis

Block diagram.( )a Implementation.

Figure 11.7

Figure 11.8

a b c d e

The feedback problem• Flip-flops are often used in circuits with

feedback connections (in addition to the internal feetback in the latch)

• Therefore, unstable states are possible

• There are two design solutions to the feedback problem

‣ Edge-triggered flip-flops

‣ Master-slave flip-flops

Combinational

circuitOutput

Figure 11.9

Master-slave SR flip-flop• Solves the instability problem caused by

possible external feedback

• Input goes to the master latch first, and then from the master to the slave, in four steps

• The threshold of a gate is the value of the input signal that causes the output to change

• Engineers can make gates with thresholds a little above or a little below the average value between 0 and 1

(a) Block diagram. (b) Implementation.

Threshold V1

Threshold V2

Master Slave

Figure 11.10

(a) Block diagram. (b) Implementation.

Threshold V1

Threshold V2

Master Slave

Timing detail of a single Ck pulse

• t1: Isolate slave from master

• t2: Connect master to input

• t3: Isolate master from input

• t4: Connect slave to master

Figure 11.11

Effect on timing• The output changes on the falling edge of

the Ck pulse and depends on the external SR input at that time

Figure 11.12

Characteristic table• A truth table is not adequate to describe a

flip-flop, because its output depends on more than its input

• Given the inputs at time t and the state at time t, the characteristic table shows the state at time t + 1, that is, after one clock pulse

Condition

No change

Not defined

Q( t + 1)

Figure 11.13

Figure 11.14

Four common flip-flops• SR Set/reset

• JK Set/reset/toggle

• D Data or delay

• T Toggle

Excitation table• The excitation table is a design tool for

constructing circuits from a given type of flip-flop

• Given the desired transition from Q(t) to Q(t +1), what inputs are necessary to make the transition happen?

Q(t + 1)

Figure 11.15

JK flip-flop• Resolves the undefined transition in the SR

flip-flop

• When JK = 00, output Q can be 0 or 1 depending on the state of the latch

• J = 1 sets ouput Q to 1 (like S)

• K = 1 resets output Q to 0 (like R)

• JK = 11 toggles from one state to the other

(b) Characteristic table.

K(t) Q(t + 1)J(t)

No change

Toggle

Q(t) Condition

(a) Block diagram.

Figure 11.16

JK flip-flop design• Must design a three-input two-output

combinational circuit

• Inputs

‣ J(t), K(t), Q(t)

• Outputs

‣ S(t), R(t)

Combinational

circuitOutput

Figure 11.9

Design table• Step 1: Given Q(t), J(t), and K(t), list the

desired state after the transition Q(t + 1)

• Step 2: Given Q(t) and Q(t + 1), use the excitation table to list the required input for S(t) and R(t)

• Step 3: Use Karnaugh maps to design minimized two-level combinational circuits for S(t) and R(t)

S(t) R(t)

Q(t + 1)

J(t) K(t)

Figure 11.17

(a) Karnaugh map for S. (b) Karnaugh map for R.

00 01 11 10JK

00 01 11 10

Figure 11.18

Figure 11.19

D flip-flop• The “delay” or “data” flip-flop

• Only one input, D

• Regardless of the current state Q(t), the state after the clock pulse Q(t + 1) will be the same as D(t)

Figure 11.20

562 Chapter 11 Sequential Circuits

Figure 11.20The D flip-flop.

(a) Block diagram. (b) Characteristic table.

(c) A timing diagram.

D(t) Q(t)

Q(t + 1)

Condition

The D Flip-Flop

The D flip-flop is a data flip-flop with only one input, D, besides the clock. Figure11.20(a) is its block diagram and (b) is its characteristic table. The table shows thatQ(t + 1) is independent of Q(t). It depends only on the value of D at time t. The Dflip-flop stores the data until the next clock pulse. Part (c) of the figure shows a tim-ing diagram. This flip-flop is also called a delay flip-flop because on the timing dia-gram, the shape of Q is identical to that of D except for a time delay.

Figure 11.19Implementation of the JK flip-flop.

71447_CH11_Chapter11.qxd 1/28/09 1:26 AM Page 562

(b) Karnaugh map for S.(a) Design table.

(c) Karnaugh map for R.

S(t) R(t)

Q(t + 1)

Q(t) D(t)

Figure 11.21

(b) Karnaugh map for S.(a) Design table.

(c) Karnaugh map for R.

S(t) R(t)

Q(t + 1)

Q(t) D(t)

Figure 11.22

T flip-flop• The “toggle” flip-flop

• Only one input, T

• If T = 0, the state remains unchanged

• If T = 1, the state toggles from 0 to 1 or from 1 to 0

T(t) Q(t + 1)

No change

Toggle

Q(t) Condition

Figure 11.23

T(t) Q(t + 1)

No change

Toggle

Q(t) Condition

Flip-flop design• Any given flip-flop can be constructed from

any other flip-flop with the right combinational circuit

• Use the excitation table for the flip-flop from which you are constructing the given flip-flop

(a) The JK flip-flop.

Q(t + 1)

J(t) K(t)

(b) The D flip-flop.

Q(t + 1)

(c) The T flip-flop.

Q(t + 1)

Figure 11.24(a) The JK flip-flop.

Q(t + 1)

J(t) K(t)

Q(t + 1)

(a) The JK flip-flop.

Q(t + 1)

J(t) K(t)

Q(t + 1)

General sequential circuits

• A general sequential circuit is an interconnection of gates and flip-flops

• The flip-flops are called state registers

• The current state and current input determine the current output

• The current state and current input determine the next state, that is, the state after one Ck clock pulse

registers

Combinational

circuit

Output

Feedback

Figure 11.25

Design The input and desired output are given.

The sequential circuit is to be determined.

Analysis The input and sequential circuit are

given. The output is to be determined.

InputSequential

circuit

Output

Input ?

Figure 11.26

Sequential analysis• Step 1: List all possible combinations of

current state and current input in an analysis table

• Step 2: For each combination, compute the output and the current inputs to the state registers

• Step 3: From the characteristic table, determine the next state and construct the state transition table and diagram

Figure 11.27

TA(t) TB(t)

A(t + 1) B(t + 1)

X1(t) X2(t)

A(t) B(t)

Figure 11.28

00 01A(t) B(t)X1(t) X2(t)

A(t + 1) B(t + 1), Y(t)

00, 001, 011, 010, 0

01, 000, 011, 010, 0

00, 111, 011, 100, 0

01, 110, 011, 100, 0

00011011

Figure 11.29

00/0, 01/0, 10/1, 11/1

11/010/0 00/001/0

01/011/1

00/010/1

10/011/0

Figure 11.30

Asynchronous inputs• An asynchronous input changes the state of a

flip-flop immediately without regard to Ck

• Preset sets Q to 1

• Clear clears Q to 0

• Used to initialize the state of a machine

PresetQ

QClear

Figure 11.31

Sequential design• Given the state transition diagram, the

output, and the type of flip-flop to be used, design the combinational circuit

• Any unused input combinations or unused states are don’t care conditions

• 2n states are possible with n flip-flops

Design steps• Step 1: In a design table, list the initial state,

input, and output, and from the transition diagram list the next state

• Step 2: Use the excitation table for the given type of flip-flop to determine the input required for the state registers

• Step 3: Use Karnaugh maps to design a minimized two-level circuit for each flip-flop input

10/11/

01/0 01/0 01/0

10/11/

Figure 11.32

Flip-flop input conditions

Nextstate

Initialoutput

B(t + 1)

Initial Initialstate input

X1(t) A(t + 1)

Figure 11.33

(a) SA = A X1 (b) RA = A B X2 + A B X1 X2

00 01 11 10X1 X2

(c) SB = B X1 (d) RB = B X1 + A X2 (e) Y = A X2 + A X1 X2

Figure 11.34

Figure 11.35

Register• An example is the 16-bit accumulator in the

Pep/8 CPU

• Constructed as an array of D flip-flops with a Load line that connects to each Ck input

• Data is clocked into the register in parallel

Block diagram.( )a

DataIn

DataOut

DataIn

DataOut

Implementation with D flip-flops.( )b

Figure 11.36

Block diagram.( )a

DataIn

DataOut

DataIn

DataOut

Implementation with D flip-flops.( )b

Bus• A bus is a group of wires connecting two

subsystems

• With a unidirectional bus, data can flow in only one direction

• With a bidirectional bus, data can flow in both directions

Bidirectional bus• Requires only half the number of wires

between subsystems

• Problem: You can connect the inputs of two gates, but you cannot connect the outputs of two gates

• Solution: The tri-state buffer

Figure 11.37

Subsystem A

Subsystem B

Figure 11.37

Figure 11.38

Disconnected

Figure 11.38

Figure 11.39

Subsystem A

Subsystem B

Figure 11.39

Memory subsystems• CS: Chip select, to enable or select the

memory chip

• WE: Write enable, to write or store a memory word to the chip

• OE: Output enable, to enable the output buffer to read a word from the chip

CS WE OE CS WE OE

Figure 11.40

(a) 64 8 bit memory chip. (a) 512 1 bit memory chip.

Figure 11.40

Memory access• To store a word (memory write)

‣ Select chip by setting CS to 1

‣ Put data and address on the bus and set WE to 1

• To retrieve a word (memory read)

‣ Select chip by setting CS to 1

‣ Put address on the bus, set OE to 1, and read the data on the bus

Figure 11.41

Word 0

Word 1

2 ! 4decoder

Word 2

Word 3

Read enable Read enable

Figure 11.41

Word 0

Word 1

decoder

Word 2

Word 3

Read enable Read enable

Figure 11.41(Expanded)

Figure 11.42

Figure 11.43

Disconnected

Connect DR to D

OE Operation

Figure 11.43

The monostable multivibrator

gates connected to the Q outputs of the D flip-flops in row 2, and disables the ANDgates connected to the flip-flop outputs of all the other rows. Consequently, datafrom the second row flows through the two OR gates into the Read enable box andonto the bidirectional bus.

A memory write works in conjunction with the box labeled MMV, whichstands for monostable multivibrator, in Figure 11.41. Assuming that the D flip-flopsare of the master–slave variety, to do a store requires a Ck pulse to go from low tohigh then high-to-low as Figure 11.11 shows. A monostable multivibrator is a de-vice that provides such a pulse. Figure 11.44 shows the timing diagram of a mono-stable multivibrator with an initial delay. When the input line goes high it triggers adelay circuit. After a predetermined time interval, the delay circuit triggers themonostable multivibrator, which emits a clock pulse with a predetermined width.Monostable multivibrators are also known as one-shot devices because when theyare activated they emit a single “one shot” pulse.

The memory write operation

Figure 11.44Timing diagram of a monostablemultivibrator with initial delay.Output

Delay Oneshot

To see how a memory write works, consider the scenario where A1 A0 = 10,CS = 1, WE = 1, and OE = 0. Assuming that the address lines, data lines, and con-trol lines are all set simultaneously, the memory circuit must wait for the addresssignals to propagate through the decoder before clocking the data into the flip-flops.The initial delay in MMV is engineered to allow sufficient time for the outputs ofthe decoder to be set before clocking in the data. The Read enable circuit puts thedata from the bidirectional bus on the input of all the flip-flops. However, when theMMV emits the clock pulse, three of the four AND gates to which it is connectedwill disable the pulse from reaching their rows. It will only reach the row of Word2, so those are the only flip-flops that will store the data.

Several types of memory chips are available on the market. The circuit modelin Figure 11.41 most closely resembles what is known as static memory or SRAM.In practice, a master–slave D flip-flop is not the basis of bit storage, as it requiresmore transistors than are necessary. Many static RAM devices use a circuit that is amodification of Figure 11.1(b), a stable circuit consisting of a pair of inverters withfeedback. It takes only two additional transistors to implement a mechanism for set-ting the state. The advantage of static RAM is speed. The disadvantage is its physi-cal size on the chip, because several transistors are required for each bit cell.

Figure 11.44

Memory types• SRAM: Static random access memory

• DRAM: Dynamic RAM

• ROM: Read-only memory

• PROM: Programmable ROM

• EPROM: Erasable PROM

• EEPROM: Electrically erasable PROM

• Flash memory: A type of EEPROM

Constructing memory subsystems

• Two design problems

‣ How to combine several n×m chips to make an n×k module where k is greater than m

‣ How to combine several n×m chips to make an l×m module where l is greater than n — the address decoding problem

Address Decoding

A single memory chip usually does not have the capacity to provide main memorystorage for an entire computer. You must combine several chips into a memory sub-system to provide adequate capacity. Most computers are byte addressable, as isPep/8. A chip like the one in Figure 11.40(a) would be convenient for such a machinebecause the word size of the chip matches the cell size that the CPU addresses.

Suppose, however, that you have a set of 4 ! 2 chips like the one in Figure11.41 and you want to use it in Pep/8. Because the word size of the chip is 2 and thesize of an addressable cell for the CPU is 8, you must group four 4 ! 2 chips toconstruct a 4 ! 8 memory module. Figure 11.45 shows the interconnections. Youcan see that the input and output lines of the module are identical to the input andoutput lines of what would be a 4 ! 8 chip. The bits of each byte in memory aredistributed over four chips. The bits of the byte at address A1 A0 = 01 are stored inthe second row (Word 1) of all four chips.

(b) Implementation.

Figure 11.45Constructing a 4 ! 8 memory mod-ule from four 4 ! 2 memory chips.

Similarly, it would take eight of the chips in Figure 11.40(b) to construct a 512! 8 memory module. For high reliability, you could use 11 of the chips for eacheight-bit cell with the three extra chips used for single-error correction, as describedin Section 9.4. With such an ECC system, the bits of each byte would be spread outover all 11 chips.

These examples show how to combine several n ! m chips to make an n ! kmodule where k is greater than m. In general, k must be a multiple of m. You simplyhook up k/m chips with all their address and control lines in common, and assignthe data lines from each chip to the lines of the module.

A different problem in constructing memory subsystems is when you have sev-eral n ! m chips, m is equal to the size of the addressable cell for the CPU, and youwant an l ! m module where l is greater than n. In other words, if you have a set ofchips whose word size is equal to the size of the addressable cell of the CPU, howdo you connect them to add memory to your computer? The key is to use the chip

CS WE OE

D0D1D2D3D4D5D6D7

(a) Block diagram.

Figure 11.45(a)

Address Decoding

A single memory chip usually does not have the capacity to provide main memorystorage for an entire computer. You must combine several chips into a memory sub-system to provide adequate capacity. Most computers are byte addressable, as isPep/8. A chip like the one in Figure 11.40(a) would be convenient for such a machinebecause the word size of the chip matches the cell size that the CPU addresses.

Suppose, however, that you have a set of 4 ! 2 chips like the one in Figure11.41 and you want to use it in Pep/8. Because the word size of the chip is 2 and thesize of an addressable cell for the CPU is 8, you must group four 4 ! 2 chips toconstruct a 4 ! 8 memory module. Figure 11.45 shows the interconnections. Youcan see that the input and output lines of the module are identical to the input andoutput lines of what would be a 4 ! 8 chip. The bits of each byte in memory aredistributed over four chips. The bits of the byte at address A1 A0 = 01 are stored inthe second row (Word 1) of all four chips.

(b) Implementation.

Figure 11.45Constructing a 4 ! 8 memory mod-ule from four 4 ! 2 memory chips.

Similarly, it would take eight of the chips in Figure 11.40(b) to construct a 512! 8 memory module. For high reliability, you could use 11 of the chips for eacheight-bit cell with the three extra chips used for single-error correction, as describedin Section 9.4. With such an ECC system, the bits of each byte would be spread outover all 11 chips.

These examples show how to combine several n ! m chips to make an n ! kmodule where k is greater than m. In general, k must be a multiple of m. You simplyhook up k/m chips with all their address and control lines in common, and assignthe data lines from each chip to the lines of the module.

A different problem in constructing memory subsystems is when you have sev-eral n ! m chips, m is equal to the size of the addressable cell for the CPU, and youwant an l ! m module where l is greater than n. In other words, if you have a set ofchips whose word size is equal to the size of the addressable cell of the CPU, howdo you connect them to add memory to your computer? The key is to use the chip

CS WE OE

D0D1D2D3D4D5D6D7

(a) Block diagram.

Figure 11.45(b)

Address decoding• An example with 8 address lines and four

chips in an address space of 256 bytes

‣ 64-byte RAM at address 0

‣ 32-byte RAM at address 64

‣ 8-port I/O chip at address 208

‣ 32-byte ROM at address 224

0 32 64 96 128 160 192 224 256

RAM RAM ROM

8-port I/O chip

Figure 11.46

Device

Minimum address

Maximum address

General address

64 ! 8 RAM

0000 0000

0011 1111

00xx xxxx

32 ! 8 RAM

0100 0000

0101 1111

010x xxxx

8-port I/O

1101 0000

1101 0111

1101 0xxx

32 ! 8 ROM

1110 0000

1111 1111

111x xxxx

Figure 11.47

A0A1A2A3A4A5A6A7

64 ! 8 bitRAM

32 ! 8 bitRAM

8-portI/O

32 ! 8 bitROM

Figure 11.48

Partial address decoding• 0 0 x x x x x x, 64×8 bit RAM

• 0 1 0 x x x x x, 32×8 bit RAM

• 1 1 0 1 0 x x x, 8-port I/O chip

• 1 1 1 x x x x x, 32×8 bit ROM

A0A1A2A3A4A5A6A7

64 ! 8 bitRAM

32 ! 8 bitRAM

8-portI/O

32 ! 8 bitROM

Figure 11.49

0 32 64 96 128 160 192 224 256

RAM ROM

8-port I/O chip

Figure 11.50

Two-port register bank• Implementation of the registers

(accumulator, index register, etc.) in the Pep/8 CPU

• The data buses are unidirectional instead of bidirectional

• There are two output ports instead of one

LoadCk

220x00 0x01

0x02 0x03

0x04 0x08

0xFA 0xFC

0xFE 0xFF

31CPU registers

CBus ABus BBus

Figure 11.51

LoadCk

ABus8 32-inputmultiplexers

8 32-inputmultiplexers

5 32decoder

Figure 11.52

1000 001 010 011 100 101 110 111

1 1 1 1 1 1

0 0 0 0 0 0 0

Figure 11.53

000 001 010 011 100 101 110 111

1 1 1 1 1 1

0 0 0 0 0 0

Figure 11.54

01 10 11

01 01 01

00 00 00 00

Figure 11.55

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