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Quartus II 2.1(LogicLock/Timing Closure)Quartus II 2.1(LogicLock/Timing Closure)

AgendaAgendaTiming Closure FlowNetlist OptimizationDesign AnalysisTiming Closure AssignmentsSummary

What is Timing Closure?What is Timing Closure?

Way to Achieve Timing Requirements

on a Design!

A Concept!

What Does Quartus II Version 2.1 Offer?What Does Quartus II Version 2.1 Offer?

New Tools to Help Achieve Timing Closure− Timing Closure Floorplan− Netlist Optimization Options− Path-Based Assignments

Timing Closure FlowTiming Closure Flow

CompileCompileDesignDesign

NetlistNetlistOptimizationOptimization

DesignDesignAnalysisAnalysis

Assignments Assignments & Compile& Compile

Success!!Success!!

Netlist Optimization OptionsNetlist Optimization OptionsWYSIWYG Primitive ResynthesisGate-level Register RetimingRetiming Trade-Off With Tsu/TcoLogic Element Duplication

WYSIWYG Primitive ResynthesisWYSIWYG Primitive ResynthesisUsed with Atom NetlistfFrom 3rd

Party ToolUnmaps AlteraPrimitives to Gates & Then RemapsOption Not Available When Using Native Synthesis Why?

Gate-Level Register RetimingGate-Level Register RetimingMoves Registers across Combinatorial Logic to Balance TimingTrades off Between Critical & Non-Critical PathsChanges at Gate Level

D

>

Q D

>

QD

>

Q7 ns 8 nsD

>

Q D

>

QD

>

Q10 ns 5 ns

Gate-Level Register RetimingGate-Level Register RetimingMust Use WYSIWYG Primitive Resynthesis Option if Using an ATOM Netlist Why?

Must Happen at Gate Level!

Gate-Level Register RetimingGate-Level Register RetimingOptions Allows Registers to Be Combined If

− All Registers Have Same Clock− All Registers Have Same Clock Enable− All Registers Same Asynchronous Control Signals− Only One Register Has Asynchronous Load Other

than VCC or GND

Gate-Level Register RetimingGate-Level Register RetimingList of Registers Created & Removed in Compilation Report

Logic Element DuplicationLogic Element DuplicationAllows LEs that Fan Out to Multiple Locations to Be Duplicated Based on Fitter Information

Netlist Optimization OptionsNetlist Optimization OptionsWith Third Party Atom Netlist

1. No Netlist Optimizations Turned On2. WYSIWYG Primitive Resynthesis Turned On3. WYSIWYG Primitive Resynthesis & Gate-Level

Register Re-timing Turned On4. Logic Element Duplication Turned On5. All Three Turned OnQuartus® II Native Synthesis

1. No Netlist Optimizations Turned On2. Gate-level Register Re-timing Turned On3. Logic Element Duplication Turned On4. Gate-Level Register Re-Timing & Logic Element

Duplication Turned On

Design AnalysisDesign AnalysisAfter Compiling, Need to Analyze DesignTwo Common Ways We Do So− Timing Analysis Report− Floorplans

Current AssignmentsLast CompilationTiming Closure

We Will Focus on the New Timing Closure Floorplan

Timing Closure FloorplanTiming Closure FloorplanFloorplan Views− Field View− Interior Cells− Package Top− Package Bottom

Viewing AssignmentsCritical PathsPhysical Timing EstimatesLogicLock Region Connectivity

New

Field ViewField ViewShows Resources

LABs

M512

M4K

MegaRAM

DSP BlockLogicLockRegion

User AssignmentsUser AssignmentsDisplays Current AssignmentsLogicLock Regions Shown in Navy

Fitter PlacementsFitter PlacementsDisplays Last Compilation AssignmentsLogicLock Regions Shown in Magenta

Viewing AssignmentsViewing AssignmentsCan View User Assignments & Fitter Locations Together

Why Different Region

Locations?

Critical PathsCritical PathsNew Utility in Quartus IIView Paths with Longest DelayCan Choose to View− A Number of or Percentage of Critical Paths− Paths in All Clock Domains or a Specific Clock

Domain− Type of Paths

Pin-to-PinPin-to-RegisterRegister-to-PinRegister-to-Register

What Do These Types Mean?tPDtSUtCO

FMAX

Critical Path Settings WindowCritical Path Settings WindowView -> Routing -> Critical Path SettingsCritical Path Settings Icon

Critical PathsCritical PathsView -> Routing -> Show Critical PathShow Critical Paths Icon

Critical Path Routing DelaysCritical Path Routing DelaysCan View Routing Delay of Critical PathsView -> Routing -> Show Routing DelaysShow Routing Delays Icon

Show Path EdgesShow Path EdgesShows Worst Case Path Between Registers

D

>

Q

Source

A B C D D

>

Q

Destination

Max IntraRegion DelayMax IntraRegion DelayAvailable After Using the Critical Paths Utility OncePut Mouse Over LogicLock Region HandleMaximum Delay Possible in LogicLock Region

LogicLock Region ConnectivityLogicLock Region ConnectivityNumber of Connections Seen With Thickness of LineTo See Number of Connections, Select Show Connection Count Icon

LogicLock Region Fan-In/Fan-outLogicLock Region Fan-In/Fan-outCan See Fan-in & Fan-out of RegionsOnly Nodes with User Assignments Will Be Shown

Timing Closure AssignmentsTiming Closure AssignmentsQuartus II Assignments− Location Assignments− LogicLock Regions

Applying Assignments− Node Assignments− Entity Assignments− Path-Based Assignments

Location AssignmentsLocation AssignmentsHard Assignments of Nodes to Resources− Logic Elements− Memory Blocks− DSP Blocks

Can Do Through− Assignment Organizer− Current Assignments Floorplan− Timing Closure Floorplan

LogicLock GUILogicLock GUIQuartus II 2.1 Introduces New View for LogicLockComprised of 2 Dialog Boxes− LogicLock Regions− LogicLock Region Properties

Tabular, Editable Display of Properties Column Display Is ConfigurableRegions with Invalid Properties Shaded Red − Repair Region via Context-Menu Entry

LogicLock GUILogicLock GUI

Reserve PropertyReserve PropertyAdd Path…Add Path…

Add Node…Add Node…

Priority…Priority…

LogicLock Regions LogicLock Region Properties

Creation Of LogicLock RegionsCreation Of LogicLock RegionsQuartus II Version 2.1 Provides 4 Methods to Create LogicLock Regions− Using The LogicLock Regions Dialog Box− Using The Floorplan Editor− Using The Hierarchy Window− Using A Tcl Script

Soft LogicLock RegionsSoft LogicLock RegionsLogicLock Regions Are Defined With A Hard Rectangular BoundarySoft LogicLockRegions Removes The Hard Boundary− Quartus II Has The

Ability to Remove Nodes Within a LogicLock Region That Has Been Declared Soft

Soft RegionSoft Region

Soft LogicLock RegionsSoft LogicLock RegionsAn Arbitrary Hierarchy Can Be Applied to Soft LogicLock RegionsSoft LogicLock Regions Will Remain Within The Boundaries of The First Non-Soft Region

Node AssignmentsNode AssignmentsNodes Are Altera Specific PrimitivesCan Be Made Through − Assignment Organizer− Current Assignments Floorplan− Timing Closure Floorplan− Back-annotating Design

Entity AssignmentsEntity AssignmentsModules of a DesignCan Be Made Through− Assignment Organizer− Dragging and Dropping From Hierarchies

Window toTiming Closure FloorplanLogicLock Regions Window

Path-Based AssignmentsPath-Based AssignmentsCan Only Be Made to LogicLock RegionsCan Be Made:− Using New Path Window− By Dragging and Dropping Paths From Timing

Analysis Section of Compilation Report− By Dragging and Dropping Using the Critical

Paths Utility in the Timing Closure Floorplan

Path-Based AssignmentsPath-Based AssignmentsAssigns Every Path From Source & Destination Nodes− Nodes Source, N1, N2, N3, N4, Destination Will Be

Assigned

Source Destination

N1 N2

N3

N4

What Nodes Shown If Using Critical Paths?

Path WindowPath WindowAllows Path to Be Specified Using Source & DestinationCan Exclude Nodes− Source− Destination− Matching Wildcard

Can Change LogicLock Region

Path WindowPath WindowList Node Lists Every Node to Which Assignment Will ApplyCan Use * & ?Wildcards in− Source Name− Destination Name− Name Exclude

What Does * Wildcard Do?What Does ? Wildcard Do?

Path WindowPath WindowCan Access Path Window from

LogicLock Regions Properties Window

Right Clicking on Critical Path

Priority of AssignmentsPriority of AssignmentsNeed Way to Determine Priority of Nodes Assigned through Paths or WildcardsPriority Window

SummarySummaryNew Integrated SynthesisNow a Detailed Timing Closure FlowNetlist Optimization Options AvailableNew Timing Closure Floorplan Tools for Design AnalysisMaking Assignments to Achieve Timing Closure