ppt on vlsi

INTEGRATED CIRCUITSINTEGRATED CIRCUITS• INTEGRAED CIRCUITES (IC) MEANING THAT ALL THE INTEGRAED CIRCUITES (IC) MEANING THAT ALL THE

COMPONENTS IN THIS CIRCUITS ARE FABRICATED ON COMPONENTS IN THIS CIRCUITS ARE FABRICATED ON THE SAME THE SAME ““CHIPCHIP””. .

• ICs HAVE BECOME A VITAL PART OF MODERN ICs HAVE BECOME A VITAL PART OF MODERN ELECTRONICS CIRCUITS DESIGN.ELECTRONICS CIRCUITS DESIGN.

• THEY ARE USED IN THE COMPUTER THEY ARE USED IN THE COMPUTER INDUDTRY ,AUTOMOBILE INDUSTRY, HOME INDUDTRY ,AUTOMOBILE INDUSTRY, HOME APPLIANCES, COMMUNICATION AND CONTROL APPLIANCES, COMMUNICATION AND CONTROL SYSTEMS.SYSTEMS.

• ICs ARE OF TWO BASIC TYPES :ICs ARE OF TWO BASIC TYPES :

• DIGITAL ICDIGITAL IC’’SS

• LINEAR ICLINEAR IC’’SS

DIGITAL ICDIGITAL IC’’SS• DIGITAL ICDIGITAL IC’’ S ARE COMPLETE FUNCTIONING LOGIC NETWORK THAT S ARE COMPLETE FUNCTIONING LOGIC NETWORK THAT

EQUIVALENTS OF BASIC TRANSISTOR LOGIC CIRCUITS.EQUIVALENTS OF BASIC TRANSISTOR LOGIC CIRCUITS.

• THEY ARE USED TO FORM SUCH CIRCUITS AS GATE,COUNER,MUX, THEY ARE USED TO FORM SUCH CIRCUITS AS GATE,COUNER,MUX, DEMUX, REGISTER,ETC.DEMUX, REGISTER,ETC.

• DIGITAL CIRCUITS CONCERNED WITH ONLY TWO LEVELS OF DIGITAL CIRCUITS CONCERNED WITH ONLY TWO LEVELS OF VOLTAGE VOLTAGE ““HIGHHIGH”” AND AND ““LOWLOW””..

• DIGITAL CKTS ARE EASY TO DESIGN AND PRODUCE IN LARGE DIGITAL CKTS ARE EASY TO DESIGN AND PRODUCE IN LARGE QUANTITIES AS LOW COST DEVICES.QUANTITIES AS LOW COST DEVICES.

LINEAR ICLINEAR IC’’SS• LINEAR ICLINEAR IC’’S ARE EQUIVALENT OF DISCREAT TRANSISTER S ARE EQUIVALENT OF DISCREAT TRANSISTER

NETWORKS SUCH AS AMPLIFIER ,FILTER ,FREQUENCY MULTIPLIEAR NETWORKS SUCH AS AMPLIFIER ,FILTER ,FREQUENCY MULTIPLIEAR AND MODULATORS.AND MODULATORS.

• IT REQUIEARS EXTRA COMPONENTSFOR SATISFACTORY IT REQUIEARS EXTRA COMPONENTSFOR SATISFACTORY OPERATIONS.OPERATIONS.

• IN LINEAR CKTS THE OUTPUT OF ELECTRICAL SIGNALS VARY IN IN LINEAR CKTS THE OUTPUT OF ELECTRICAL SIGNALS VARY IN PROPORTION TO THE INPUT SIGNALS APPLIED.PROPORTION TO THE INPUT SIGNALS APPLIED.

• LINEAR CKTS ARE ALSO REFERRED TO AS ANALOG CIRCUITS.LINEAR CKTS ARE ALSO REFERRED TO AS ANALOG CIRCUITS.

GENERATION OF INTEGRATED GENERATION OF INTEGRATED CIRCUITSCIRCUITS

TECHNOLOGY NO. OF TRANSISTER PER CHIP

YEAR

INVENTON OF TRANSISTOR

1 1947

DISCREATE COMPONENTS

1 1950

SMALL SCALE INTEGRATION

10 1961

MEDIUM SCALE INTEGRATION

100-1000 1966

LARGE SCALE INTEGRATION

1000-20,000 1971

VERY LARGE SCALE INTEGRATION

20,000-1,00,000 1980

ULTRA LARGE SCALE INTEGRATION

1,00,000-10,00,000 1990

GIANT SCALE INTEGRATION

>10,00,000 2000

VLSI DESIGNVLSI DESIGN

VLSI AN INTRODUCTIONVLSI AN INTRODUCTION•VLSI Stands For Very Large Scale IntegrationVLSI Stands For Very Large Scale Integration

• VLSI IS A PROCESS OF INTEGRATION OF VLSI IS A PROCESS OF INTEGRATION OF MILLIONS OF TRANSISTOR IN A SINGLE MILLIONS OF TRANSISTOR IN A SINGLE CHIP .VLSI DESIGN INVOLVES ALL ASPECTS CHIP .VLSI DESIGN INVOLVES ALL ASPECTS OF CREATING AN IC.OF CREATING AN IC.

•USING VLSI WE CAN PACK MORE AND MORE USING VLSI WE CAN PACK MORE AND MORE LOGIC DEVICES INTO SMALLER AND SMALLER LOGIC DEVICES INTO SMALLER AND SMALLER AREAAREA

LANGUAGE USED IN VLSILANGUAGE USED IN VLSI

• VLSI BASICALLY USE HDL’S ie, HARDWARE VLSI BASICALLY USE HDL’S ie, HARDWARE DESCRIPTION LANGUAGEDESCRIPTION LANGUAGE

• HDL IS A LANGUAGE FOR FORMAL HDL IS A LANGUAGE FOR FORMAL DESCRIPTION OF ELECTRONIC CIRCUITSDESCRIPTION OF ELECTRONIC CIRCUITS

• IT CAN DESCRIBE CIRCUITS OPERATION , ITS IT CAN DESCRIBE CIRCUITS OPERATION , ITS DESIGN AND TESTS TO VERIFY ITS DESIGN AND TESTS TO VERIFY ITS OPERATIONOPERATION

• THEY CAN BE USED TO DESIGN ANYTHING THEY CAN BE USED TO DESIGN ANYTHING FROM INDIVIDUAL FUNCTION MODULES TO FROM INDIVIDUAL FUNCTION MODULES TO LARGE MULTIPLE SYSTEMSLARGE MULTIPLE SYSTEMS

VARIOUS HDL’s IN VLSIVARIOUS HDL’s IN VLSI

• VHDL- VERY HIGH SPEED INTEGRATED VHDL- VERY HIGH SPEED INTEGRATED CIRCUIT HARDWARE DESCRIPTION CIRCUIT HARDWARE DESCRIPTION LANGUAGELANGUAGE

• VERILOG- VERIFY LOGIC HARDWARE VERILOG- VERIFY LOGIC HARDWARE DESCRIPTION LANGUAGEDESCRIPTION LANGUAGE

• ABEL- ADVANCE BOOLEAN EXPRESSION ABEL- ADVANCE BOOLEAN EXPRESSION LANGUAGELANGUAGE

THE VHDL LANGUAGE THE VHDL LANGUAGE

• VHDL IS ONE OF THE MOST ACCEPTED AND VHDL IS ONE OF THE MOST ACCEPTED AND WIDELY USED LANGUAGE FOR DESCRIBING WIDELY USED LANGUAGE FOR DESCRIBING DIGITAL SYSTEM .DIGITAL SYSTEM .

• VHDL HAS BEEN APPROVED BY IEEE AS A VHDL HAS BEEN APPROVED BY IEEE AS A STANDARD LANGUAGE FOR DESIGING STANDARD LANGUAGE FOR DESIGING HARDWARE.HARDWARE.

• VHDL IS ABBRIVATION FOR VHDL IS ABBRIVATION FOR

““Very High Speed Integrated Circuit HARDWARE Very High Speed Integrated Circuit HARDWARE DESCRIPTION LANGUAGE.DESCRIPTION LANGUAGE.””

HISTORY OF VHDLHISTORY OF VHDL

• In 1987: STANDARD VERSION OF VHDL In 1987: STANDARD VERSION OF VHDL ““IEEE Std 1076-1987IEEE Std 1076-1987”” WAS LAUNCHED FOR WAS LAUNCHED FOR INDUSTRIAL USEINDUSTRIAL USE

• In 1993: REVISED In 1993: REVISED ““IEEE Std-1076-1993IEEE Std-1076-1993”” STANDARD WAS RELEASED, VHDL-93.STANDARD WAS RELEASED, VHDL-93.

• In 2001: REVISED In 2001: REVISED ““IEEE Std-1076-2001IEEE Std-1076-2001”” STANDARD WAS RELEASED, VHDL-2001.STANDARD WAS RELEASED, VHDL-2001.

• In 2002: WORK ON In 2002: WORK ON ““VHDL -200XVHDL -200X”” STARTED. STARTED.

VHDL DESIGN CYCLE VHDL DESIGN CYCLE

SIMULATED WAVEFORMS

SIMULATION

DESIGN IDEA

SYNTHESIZER

CIRCUIT GENERATED

CIRCUITED IMPLEMENTED

VHDL MODLE

PROGRAM STRUCTURE PROGRAM STRUCTURE

ARCHITECTURE

LIBRARY/PACKAGE

ENTITY

BASIC TERMINOLOGY/ BASIC TERMINOLOGY/ DESIGN UNITS DESIGN UNITS

(A) ENTITY DECLARATION(B) ARCHITECTURE BODY(C) CONFIGURATION DECLARATION(D) PACKAGE DECLARATION(E) PACKAGE BODY

ENTITY:• AN ENTITY IS THE MOST BASIC BUILDING BLOCK IN A

DESIGN. • A HARDWARE DESCRIPTION OF A DIGITAL SYSTEM IS

CALLED AN ENTITY.• AN ENTITY SPECIFIES THE EXTERNAL VIEW AND ONE OR

MORE INTERNAL VIEWS.

ARCHITECTURE BODY: • THE ARCHITECTURE BODY CONTAINS THE INTERNAL

DESCRIPTION OF THE ENTITY.• THE ARCHTECTURE DESCRIBES THE FUNCTIONALITY &

BEHAVIOUR OF THE ENTITY.• AN ARCHITECTURE IS ALWAYS RELATED TO AN ENTITY.

CONFIGURATION:• IT SPECIFIES THE BINDING OF ONE ARCHITECTURE BODY

FROM THE MANY ARCHITECTURE BODIES.• CONFIGURATION DECLARATION IS USED TO BIND ONE OF

MANY ARCHITECTURE BODIES TO AN ENTITY. • IT IS ALSO USED TO BIND COMPONENTS USED IN STRUCTURAL

MODEL TO OTHER ENTITY –ARCHITECTURE PAIR.• AN ENTITY MAY HAVE ANY NUMBER OF DIFFERENT

CONFIGURATION.

PACKAGE:• A PACKAGE IS A COLLECTION OF COMMONLY USED DATA

TYPES AND SUB PROGRAMS USED IN A DESIGN.

PACKAGE DECLARATION:• A PACKAGE DECLARATION ENCAPSULATES A SET OF

RELATED DECLARATIONS SUCH AS DATA TYPES, COMPONENTS, SUB PROGRAM (PROCEDURE AND FUNCTIONS).

• THE DECLARATION INSIDE A PACKAGE CAN BE SHARED BY OTHER DESIGN UNITS BY USING A “USE” CLAUSE.

PACKKAGE BODY:• A PACKAGE BODY CONTAIN THE DEFINITIONS OF

SUBPROGRAMS DECLARED IN A PACKAGE DECLARATION.• NAME OF PACKAGE BODY SHOULD BE SAME AS PACKAGE

DECLARATION.

NOTE: A HADRWARE DESCRIPTION OF DIGITAL SYSTEM i.e. AN ENTITY MUST HAVE AN ENTITY DECLARATION AND AT LEAST ONE ARECHITECTURE BODY.

ENTITY DECLARATION :• ENTITY DECLARATION DESCRIBES HOW AN ENTITY

IS CONNECTED TO OUTSIDE WORLD. • IT DESCRIBES THE EXTERNAL VIEW OF THE ENTITY.• ENTITY DECLARATION SPECIFIES THE NAME OF

ENTITY.• IT ALSO SPECIFIES THE INPUT AND OUTPUT PORTS

THROUGH WHICH ENTITY COMMUNICATES WITH THE EXTERNAL WORLD.

SYNTEX OF ENTITY DECLARATION :

ENTITY entity-name ISPORT (port1: port1-type: port2: port2-type);END entity-name;

Ex.1 WRITE THE ENTITY DECLARATION FOR A 2 INPUT AND GATE.

entity AND2 isport (a, b: in bit ; c : out bit);end AND2;

Ex. 2 WRITE THE ENTITY DECLARATION FOR A FULL ADDER.

entity FullAdder isport (X, Y, Cin: in bit; -- InputsCout, Sum: out bit); -- Outputsend FullAdder;

FullAdder

ARCHITECTURE : • IT SHOWS THE INSIDE VIEW OR WHAT ARE THE

FUNCTIONS OPERATION ARE DONE AND WHICH TYPE OF THAT .

• AN ARCHITECTURE IS ALWAYS RELATED TO AN ENTITY & DESCRIBES THE BEHAVIOUR OF THE ENTITY.

• INTERNAL DETAILS OF AN ENTITY ARE SPECIFIED BY AN ARCHITECTURE BODY BY USING ANY ONE OF THE FOLLOWING MODEL:

SYNTEX OF ARCHITECTURE:ARCHITECTURE arcitecture-name OF entityname IS ….declare some signals hereBEGIN….put some concurrent statement hereEND architecture-name;

AREHITECTURE BODY AREHITECTURE BODY

•BEHAVIORAL MODELBEHAVIORAL MODEL

•STRUCTURAL MODELSTRUCTURAL MODEL

•DATAFLOW MODEL DATAFLOW MODEL

BEHAVIORAL MODEL:• THE BEHAVIORAL STYLE OF MODELING SPECIFIES THE

BEHAVIORAL OF AN ENTITY AS A STATEMENTS THAT ARE EXECUTED SEQUENTIALLY IN THE SPECIFIED ORDER.

• ALL STATEMENTS WHICH ARE SPECIFIED INSIDE A PROCESS STATEMENT, DO NOT CLEARLY SPECIFIES THE STRUTURE OF THE ENTITY BUT MERELY ITS FUNCTIONALITY.

• A PROCESS STATEMENT IS A CONCURRENT STATEMENT THAT CAN APPEAR WITH IN AN ARCHITECTURE BODY.

EX.1 WRITE THE BEHAVIORAL MODEL DESCRIPTION OF AND GATE .

architecture AND-2-BEHAVIOR of AND-2 is beginprocess (A,B)begin C<=A and B;end process;end AND-2 BEHAVIOR;

EX.2 WRITE THE BEHAVIORAL MODEL DESCRIPTION OF EX-OR GATE .

architecture EX-OR-2-BEHAVIOR of EX-OR-2 is beginprocess (X,Y)begin Z<=X and Y;end process;end EX-OR-2 BEHAVIOR;

STRUCTURE ARCHITECTURE:STRUCTURE ARCHITECTURE:

• IN THE STRUCTRE STYLE OF MODELING AN IN THE STRUCTRE STYLE OF MODELING AN ENTITY IS DESCRIBED IN TERMS OF ITS ENTITY IS DESCRIBED IN TERMS OF ITS COMPONENTS AND THEIR INTERCONNECTIONS.COMPONENTS AND THEIR INTERCONNECTIONS.

• A STRUCTURE MODEL DOES NOT TELL ABOUT A STRUCTURE MODEL DOES NOT TELL ABOUT THE FUNCTIONALITY OF THE ENTITY.THE FUNCTIONALITY OF THE ENTITY.

• A STRUCTURE DESCRIPTION IS EASIEST TO BE A STRUCTURE DESCRIPTION IS EASIEST TO BE SYNTHESIZED.SYNTHESIZED.

• THE ARCHITECTURE BODY IS COMPOSED OF TWO THE ARCHITECTURE BODY IS COMPOSED OF TWO PARTS:PARTS:

1.1.THE DECLARATION PART (BEFORE THE KEYWORD THE DECLARATION PART (BEFORE THE KEYWORD BEGIN) BEGIN)

2.2.THE STATEMENT PART (AFTER THE KEYWORD THE STATEMENT PART (AFTER THE KEYWORD BEGIN).BEGIN).

• HALF ADDER IS SUCH TYPE OF STRUCTURE HALF ADDER IS SUCH TYPE OF STRUCTURE ARCHITECTURE. ARCHITECTURE.

EX.1 STRUCTURAL DESCRIPTION OF HALF EX.1 STRUCTURAL DESCRIPTION OF HALF ADDER.ADDER.

architecture architecture HALF-ADDER-STRUCTURE HALF-ADDER-STRUCTURE ofof HALF-ADDER HALF-ADDER isiscomponent AND2component AND2portport(IN1,IN2: (IN1,IN2: inin bit ; OUT1: bit ; OUT1: outout bit); bit);end component;end component;

component XOR2component XOR2portport(IN3,IN4: (IN3,IN4: inin bit ; OUT2 : bit ; OUT2 : outout bit); bit);end component;end component;begin begin A1:AND2 A1:AND2 port map port map (A,B, Sum);(A,B, Sum);X1:XOR2 X1:XOR2 port map port map (A,B,Carry);(A,B,Carry);endend HALF-ADDER-STRUTURE; HALF-ADDER-STRUTURE;

DATAFLOW ARCHITECTUREDATAFLOW ARCHITECTURE: :

• IN THE DATAFLOW STYLE OF MODELING AN IN THE DATAFLOW STYLE OF MODELING AN ENTITY IS DESCRIBED IN TERMS OF DATA ENTITY IS DESCRIBED IN TERMS OF DATA FLOW BY USING CONCURRENT SIGNAL FLOW BY USING CONCURRENT SIGNAL ASSIGNMENT STATEMENTS.ASSIGNMENT STATEMENTS.

• A DATAFLOW MODEL DOES NOT TELL ABOUT A DATAFLOW MODEL DOES NOT TELL ABOUT THE STRUCTURE OF THE ENTITY.THE STRUCTURE OF THE ENTITY.

EX.1 DATAFLOW DESCRIPTION OF HALF ADDER.EX.1 DATAFLOW DESCRIPTION OF HALF ADDER.

architecture architecture HALF-ADDER-DATATFLOW HALF-ADDER-DATATFLOW ofof HALF- HALF-ADDER ADDER isis

begin begin

SUM<=A SUM<=A xorxor B; B;

CARRY<=A CARRY<=A andand B; B;

endend HALF-ADDER-DATAFLOW; HALF-ADDER-DATAFLOW;

VHDL SOFTWARE USED VHDL SOFTWARE USED

1.1.XILINX ISE 8.1 IXILINX ISE 8.1 I2.2.ALTERA ALTERA 3.3.QUARTUSQUARTUS

OUTPUT WAVE FORMOUTPUT WAVE FORM

OUTPUT WAVE FORMOUTPUT WAVE FORM

OUTPUT WAVE FORMOUTPUT WAVE FORM