module 07 board consult ii & test consultant

Agilent 3070 User Fundamentals

Board & Test Consultant 7 - 1

Module 7: Board Consultant & Test ConsultantTable of Contents

Goals of the Board Consultant II & Test Consultant Module .............................. 2The rest of the Flowchart ................................................................................ 3

The "testability.rpt" before Test Consultant.......................................................... 6Agilent IPG Test Consultant.................................................................................. 7

Agilent IPG Test Consultant ........................................................................... 8Test Consultant's Inputs ................................................................................ 11Test Consultant's Outputs.............................................................................. 13

The "testability.rpt" after Test Consultant........................................................... 16LAB 07A: Finish the Board Consultant Process ................................................. 18LAB 07B: Use Agilent IPG Test Consultant....................................................... 26

Appendix.............................................................................................................. 32Board Consultant Conventions ..................................................................... 32

Agilent Technologies

Goals of the Board Consultant II & Test Consultant Module

• In the previous visit to Agilent Board Consultant, you discovered somemissing libraries.

− You created two Part Description Editor entries for the resistor packson the Angela Board.

• Having made the needed corrections, you are ready to return to BoardConsultant and finish its development process.

− In this module, you will finish the rest of the development process usingAgilent Board Consultant and its flowchart.

− This will include entering a library path for the oscillator chip.− You will create and analyze a testability report, the "testability.rpt" file.− You will run Agilent IPG Test Consultant to generate test and fixture

files.− You will create a new "testability.rpt" and analyze it.

13070 User FundamentalsModule 7: Board Consultant & Test Consultant sA

Test Development FlowchartProcess Files Tools

Generates Modify

testability.rpt

Fixture Files

Individual TestFiles

config

testplan

Translate CAD1

Generate Test & Fixture files3

Build & Verify test Fixture4

Turn-On / Debug all Tests5

Release to Production & Long Term Support

Describe board & system2

Custom libraries

board_xy

CAMCAD Translator

BT-BASIC

Board Consultant

Part Description Editor

Digital Setup Editor

IPG Test Consultant

PushButton Debug

The rest of the Flowchart• Before you can resume, you MUST reload the data or restart the interface.

If you iconified the Board Consultant, the information currently loaded wasloaded before your work in the Part Description Editor or Digital SetupEditor. Therefore, the changes you made with these editors needs to bereloaded in Board Consultant.

• Resume the process by checking the missing libraries are no longer missing.

This completes the processes under the library's COMPILE & VERIFY block.

• Continue to the COMPILE & VERIFY block at the bottom of the leftcolumn, below VIEW / EDIT TEST SYSTEM DATA.During the previous visit, this block was skipped so you could see the librarycolumn first.

− VERIFY FIXTURE TYPEThis will check to see that your fixture settings are all compatible withthe board description.

− VERIFY CONFIGURATION SIZEThis checks to see that the number of nodes on the printed circuit boarddo not exceed the number of testhead resources you have specified.

− ACCESS CONSULTANTAccess Consultant will be described later in the class. When you have abetter understanding of the entire system, Access Consultant is easy tounder stand; however, until then, it can be confusing.

Agilent Board ConsultantFlowchart

− SHOW DEVICES USING POLARITY CHECK / TESTJETDuring the first visit to Board Consultant, you marked all the integratedcircuits and the connector to be tested with TestJet. This will list allthose devices so you can make sure you did not accidentally omit adevice.Polarity Check uses the TestJet probe to test the polarity of a polarizedcapacitor. The Tantalum slug is always closer to pin 2 of the slug andthis tests for that. If the device is loaded backward, it is easily detectedwith this test.

− SHOW BOTTOM KEEPOUT FOR POLARITY & TESTJETIf a TestJet or Polarity Check probe must be mounted in the SupportPlate of your fixture, you must remove a piece of the Support Plate.This prevents test probes or Personality Pins from being placed in thisimmediate area. This tests for that situation.

− SHOW DEVICES USING CONNECTCHECKProvide a list of the devices that have been marked for test withConnect Check. (This will not be covered in the class.)

− VERIFY NODE PROBING ACCESSAre all the nodes that you indicated as available, actually available?

− VERIFY POWER NODE PROBING ACCESS &VERIFY GROUND NODE PROBING ACCESSAre there enough power node locations. The system expects to connectto a large number of power and ground points to minimize the signal tonoise ratio during test.

• FINAL COMPILE & VERIFY− SAVE BOARD FILES

As always, it is good to save often.− COMPILE "BOARD" FILE

Compile the "board" file. A successful compile means there are noapparent problems with the "board" file. A failure will include a listingof the compiler error/warning in the Board Consultant Messagewindow. These messages should help you locate the faulty entry.

− COMPILE "BOARD_XY" FILEThe same is true for the "board_xy".

− GENERATE X-Y PLOTSGenerate a plot file. This is used by the fixture builder.

− SHOW IPG DEVICE SUMMARYShow summary information about the overall test.

− VERIFY IPG DISABLE RESULTSCheck the ability to disable all digital devices that have disablefunctions (output enable lines).

− VERIFY SAFEGUARD INHIBIT RESULTSSafeguard protects adjacent devices from potentially damaging tests. Ifyou are testing one device, the devices around it are being overdrivenby the 3070's drivers. Safeguard protects those adjacent devices. ASafeguard Inhibit here means an adjacent device is being overdriven toolong. More on this during the Digital portions of the class.

• GENERATE "TESTABILITY.RPT"Generate the report and review it.

− If there is something in the report that does not meet your needs or testdefinitions; then you must change something in the test definitions toproduce the results you expected.

At this point, the board description should be complete and accurate and ready for TestConsultant.

The "testability.rpt" before Test Consultant

After the board description is complete and successfully compiling the board andboard_xy files, you should generate a "testability.rpt". The report provides summaryinformation reflecting all the verification process steps performed during BoardConsultant. Review this report. If anything is missing, return to Board Consultant andcomplete that description.

• Number of devices− Analog− Digital

• Number of integrated circuits− Using Library tests− Are the needed libraries available?− Using TestJet (and connectors)

• Node information− Inaccessible nodes?− Critical nodes? (Nodes which use scarce testhead resources.)

• Review the report to see if you are ready to run Test Consultant

“testability.rpt”

TESTABILITY REPORT SUMMARY/users<#>/angela_bd

<date>

RESULTS HAVE BEEN DERIVED FROM[X] Board description and config entries[X] Information from library objects[ ] Information from bsdl objects[ ] Information from test generation[ ] Information from test compilation

MISSING LIBRARIES RESULTSLibrary sources exist for all (13) devices requiring them

AGILENT POLARITY CHECK RESULTS

None of the capacitors use

Agilent IPG Test Consultant

The next step in the Development Process is to run Agilent IPG Test Consultant.

• IPG stands for Integrated Program Generator. This means it creates the testfiles for both unpowered and powered tests. It also creates the files thatdescribe how to build the test fixture needed for this board.

• Agilent IPG Test Consultant was the original user interface developed forthe 3070. It has several functions that are no longer used as they have beenreplaced by improved software and other user interfaces. Therefore, thisclass will only use two aspects of Test Consultant.

− The FILE pull down menu that allows you to open almost all the otherinterfaces on the system.

− The DEVELOP BOARD TEST function. This initiates the generationof the test and fixture files.

− The MANAGEMENT menu allows you to Clean Up a Board Directoryor Copy/Move a Board Directory.

Test Development Flowchart

Process Files Tools

Generates Modify

testability.rpt

Fixture Files

IndividualTest Files

config

testplan

Translate CAD1

Generate Test & Fixture files3

Build & Verify test Fixture4

Turn-On / Debug all Tests5

Release to Production & Long Term Support

Describe board & system2

Custom libraries

board_xy

CAMCAD Translator

BT-BASIC

Board Consultant

Part Description Editor

Digital Setup Editor

IPG Test Consultant

PushButton Debug

Agilent IPG Test Consultant

You may need to initialize Test Consultant to perform the tasks, as you want it toperform them. The number of boards on a fixture and the default generation mode isalways set for a first time run. It assumes there is no fixture and any files that exist canbe rewritten.

The FIXTURE FORMAT setting can be changed from SINGLE BOARD PERFIXTURE to MULTIPLE BOARDS PER FIXTURE.

• SINGLE BOARD PER FIXTUREExpect to have one and only one type of printed circuit board or panelloaded on the fixture.

• MULTIPLE BOARDS PER FIXTUREAllows you to place multiple boards on a fixture. These are completelyseparate boards that happen to be built on a single fixture. There are multipleboard test directories … multiple of everything except one fixture. This isoccasionally used in applications where there are low volume boards, usuallyrelatively small boards and there is limited space available to store fixtures.If multiple boards will co-exist on a single fixture, storage space is saved andthe expense of multiple fixture kits.

Agilent IPG Test ConsultantProcess

These images are from the Agilent 3070PC

The TEST REGENERATION BEHAVIOR field should be checked each time, beforerunning Test Consultant. This provides you control over Engineering Change Order testregeneration. For a first time board development, you will run in the ComprehensiveRegeneration (default) mode. The modes:

− Limited RegenerationThis mode allows Test Consultant to edit the tests for those devices thathave changed as a part of the ECO. No other device tests may bealtered. This includes devices adjacent to the modified device - teststhat may or may not need to be modified.However, if a test that is directly involved with the ECO has been"marked permanent", Test Consultant may not modify it. The"permanent" marker can be applied when you are debugging a test.

− Limited; Clear PermanentThis mode allows Test Consultant to edit the tests for those devices thathave changed as a part of the ECO, even if they are marked permanent.No other device tests may be altered. This includes devices adjacent tothe modified device - tests that may or may not need to be modified.

− Comprehensive Regeneration (default)The tests for all modified devices, devices adjacent to or interactivewith modified devices are re-evaluated. If the device is markedpermanent, it cannot be overwritten. Otherwise, any device may have anew test generated. While every device is reevaluated, only those teststhat change significantly will actually be rewritten..

− Comprehensive; Clear PermanentThe tests for all modified devices, devices adjacent to or interactivewith modified devices are re-evaluated. If the device is markedpermanent, it can be overwritten. While every device is reevaluated,only those tests that change significantly will actually be rewritten.

The label on Test Consultant always says “Regeneration”, even for the first time you run.

Tell Test Consultant to generate the test and fixture files:

• Click ACTIONS | DEVELOP BOARD TESTThis creates a new window, the Dependencies Calculation Window. It hasthis title because it looks at the entire printed circuit board, prioritizes nodeassignment, identifies access dependency (when testing this integratedcircuit, the test must disable that device…)OR

• Click ACTIONS | BATCH MODEThe Interactive Mode allows you to control / monitor each step of thedevelopment process. This close monitoring is no longer needed or advised.Therefore, always run in Batch Mode.

Use Test Consultant to copy an existing board development into a new directory.

• Click MANAGEMENT | COPY/MOVE BOARD DIRECTORYThis function is usually used when you encounter an Engineering Change.You should always copy the working test and work on the copy. When thecopy is working correctly, decide whether to add the new work as a differentrevision of the test or overwrite the existing test.

• When you select this function, the format of the interface changes. You havea FROM Directory field and a TO Directory field. The Selected DirectoryContents field changes depending on which directory is selected, From orTo.To change the TO/FROM directory, click ACTIONS | TOGGLE FROM/TOLISTINGS

Test Consultant's Inputs

What information does each file provide?

• “board”− The component designators: These are used to name the individual test

file for each device.− The components value and tolerance used to create the test and define

the test limits for each device.− The Tolerance Multiplier and Remote Sensing options that you

provided as a way of telling the software how accurately to test thedevice.

− The connectivity of the devices on the PC board. This is accomplishedthrough the node names entered via CAD translation or the manualentry process.

• “board_xy”− The location of each component lead, via, test pad or other location that

can be probed.− The accessibility of each probeable location.− If you are using TestJet tests, this file provides the information needed

by the fixture builders.− If you are building a Simplate Fixture (long wire) this file is not needed.

Agilent IPG Test ConsultantInputs

Test Consultant’s inputs

boardboard_xyconfigstandard test librariescustom library

• “config”− Describes which system resources are available.

• “/var/hp3070/library/”− The source files for generating tests of digital devices and/or many

analog devices. There are several libraries.− The “ttl”, “cmos”, “lsi”, “ecl”, “setup” directories contain many

standard digital device tests.− The “interface” and “linear” libraries contain many analog devices.− The “template” library provides templates for building custom libraries

for devices not currently in the 3070 library but are needed to test agiven board.

− “supplemental libraries” that contain new digital tests that have beendeveloped recently.

• “custom_lib”− Custom generated directory that contains library sources that you have

created. The directory may be named “custom_lib,” but this is NOT areserved name. Any name will work; this is simply the Agilentconvention.

Test Consultant's OutputsDirectories:

• analog/This directory contains all the test files for the individual analog devices.

− There is one test file for each device.− Each test file has a source file and an object. E.g.: r1 and r1.o− Both analog unpowered and powered tests are in this directory.

• debug/− The debug directory supports Agilent PushButton Debug. This interface

allows you access to general test types - run a test subroutine orindividual tests.

• digital/− There is one test file for each device or test.− Each test file has a source and an object. E.g.: u201 and u201.o

• fixture/− This directory contains all the information about the test fixture.

• ipg/− The ipg directory contains summary files describing the test generation

process.

Agilent IPG Test ConsultantOutputs

Test Consultant generates Directories: Files:

analog/ testplandebug/ testorderdigital/ pinsfixture/ shorts ipg/ safeguard

testjet

• functional/− This directory contains tests for digital clusters. You will not have this

directory with the Angela Board, but you will see it with theCombination Board later in the class.

• mixed/− This directory contains tests that use both analog functional and digital

test tools. This will be needed on the Combination Board.

Files:• testplan

− This program manages the testing sequence. It is critical that allprogrammers become familiar with testplan as you will use itfrequently. During the lab, you will load and review it.

• Parts of testplan: (See flowchart in Appendix of this module.)− Header Section: Comments, explanation, dimensioning of strings,

arrays... call Initialization routines...− nrun =1 (This is the number of times the test has been run during this

session. The software needs this information.)− call Characterize (learn the capacitance of the fixture for small value

capacitors.)− Main Loop: Prompt the operator to place the board on the fixture...

Wait for the Start key to be pressed• Enter serial number if using serialization• Turn on the vacuum• unpowered command• Pins Test if mode = Pretest• Call Test_Sections

Preshorts TestShorts TestAnalog Unpowered TestsTestJet and Polarity Check TestsSetup Power Supplies (Turn on the power supplies and check forcurrent limits.)Digital Incircuit TestsDigital Functional Tests (an Advanced Digital Class topic)Analog Powered TestsMixed Signal TestsBoundary Scan Tests

• Cleanupunpowered commandPins Test if mode = Failuresvacuum offDisplay Pass/Fail messageClear report device and failure logs (datalogging)

• Return to beginning of Main Loop.

• testorder− The testorder file lists each test, in the order it is preformed.− During debug, you have the option of marking a test "permanent". This

means the software cannot overwrite the test if Test Consultant is re-run. Testorder is where this flag is stored. Other flags also saved intestorder: nulltest, characterize, comment, preshorts. More details abouteach will follow in later training modules.

• pins− This is the pins test.− There is a text and an object file. (pins and pins.o)

• shorts− This is the shorts test.− There is a text and an object file. (pins and pins.o)

• safeguard− The digital test technique used on the 3070 has the potential to damage

devices adjacent to the device being tested. Safeguard is monitoringprogram that ensures this potential is never realized. More on Safeguardduring the Digital training modules that follow.

• testjet− TestJet is the unpowered test of integrated circuits and connects.− It measures the capacitance of the lead that is adjacent to the TestJet

probe.− This file supports that test.− There is a text file and an object.

The "testability.rpt" after Test Consultant

Having created the test and fixture files, you should now return to Board Consultant andgenerate a new "testability.rpt".

• The first report described what the software expected to happen. It wasprojected results.

• Now that Test Consultant has run, but before the fixture is built, check thereport again to see that the projected results match the actual results.

The report provides summary information about the quantity and quality of yourtest. Information includes a listing of each test type:• Shorts

Number of expected shortsNumber of Inaccessible nodes

• Analog:Number of null tests1 and the device designatorsNumber of commented tests and the device designatorsNumber of limited tests and the device designators

• Digital:Number of digital devices that cannot be disabled and the device designatorsNumber of Safeguard Inhibits and the device designators

1 Many of the descriptions listed are not yet explained. Each will be covered as the class progresses.

During the lab that follows this lecture, you will generate a "testability.rpt" and analyze it. Specificdetails will be provided then.

“testability.rpt”

TESTABILITY REPORT SUMMARY/users<#>/angela_bd

<date>

RESULTS HAVE BEEN DERIVED FROM[X] Board description and config entries[X] Information from library objects[ ] Information from bsdl objects[X] Information from test generation[X] Information from test compilation

…The tests for the following devices have been commented:Test and Subtest | DUT Tolerance | Test ToleranceName Designation | Nominal Plus Minus | Nominal Plus Minus

r212 | 10K 1.0% 1.0% | 10K -38.2% 138.8%r207 | 250K 1.0% 1.0% | 250K 4.1% 150.0%

• Polarity Check:Number and designators of capacitors being tested with Polarity Check

• TestJetNumber and designators of devices being tested with TestJet

• If you are using optional software such as Boundary Scan, there is a list ofinformation specifically for boundary scan.

When you evaluate the "testability.rpt", you may discover something that is not "right".To correct limited test coverage or other concerns:

• Return to Board Consultant and make modifications to the description.• If modifications cannot be made, see if you can identify test alternatives.

(If an "output enable" is tied to ground - you cannot change that, but youmight be able to modify your test technique so you do not need it. You couldtest with TestJet only or perhaps the tests will be fast enough that the outputenable is not needed.)

• If an analog device is listed in the "limited" or "commented" test categories,allow the software to use remote sensing on it (if remote sensing is disabledglobally). Or check the schematic, could you widen the tolerance limits forthe device?

Eventually, you should be satisfied with the results of the "testability.rpt" and continue tothe next step…

LAB 07A: Finish the Board Consultant Process

During the previous labs, you:

• Created a directory to contain the board description.• Created a "config" file for the board.• Started Agilent Board Consultant and developed much of the description of

the Angela Board.• Discovered that there were missing libraries for the Angela Board.• Used the Part Description Editor to create a library for some of the missing

devices.

Now you will:

• Continue with the Board Consultant process from where you left off earlier.• Complete the Board Consultant process.• Generate and evaluate the "testability.rpt".• Run Agilent IPG Test Consultant to create the fixture and test files.

Check your resources:

• During this lab: Complete the data entry phase of the board development.• All work is done at the development stations; no testhead is required.• The board is the “angela_bd”.

This lab is done at the Test Development Station.

1. Log onto your Test Development Station.At the logon screen:

Type in your <user#>. (E.g.: user4 - no space) The password is: class

2. Before starting, you need to include the test for Y1, the oscillator chip. The partnumber is 1813-0616.

Start or restore a BT-BASIC window. Copy the instructor's version of the Y1 test into your Custom Lib directory:

NOTE: Later in the class, you will learn to write analog functional tests, includingtests for oscillator chips. But to teach those details now detracts from learning theoverall test development process, so the instructor is providing this test today. Youwill write one later.

HP-UX USERS copy "/hp3070/boards/sources/custom_lib/1813-0616"

to "custom_lib/1813-0616"

MS WINDOWS USERS copy "D:/Agilent3070/boards/sources/custom lib/1813-0616"

to "custom_lib/1813-0616"

EVERYONE3. Start Board Consultant and define the path to the Angela Board.

HP-UX USERS Click on the 3070 icon in the pop-up menu and click Board Consultant. Verify the path: /home/user<#>/angela_bd

MS WINDOWS USERS PC users: Click on the Board Consultant icon on the desktop. Verify the path: /D=/Agilent3070/home/user<#>/angela_bd

EVERYONE Click LOAD BOARD

4. Verify / review the previous data entry. Click VIEW / EDIT PHYSICAL BOARD DATA

The Board outline information exists and is correct.The Board Tooling hole information has been defined.

Click VIEW / EDIT BOARD DESCRIPTIONAll the devices for this board have been entered.

Click COMPILE & VERIFYThis information has been previously verified.

Click VIEW / EDIT LIBRARY DATA (on the right side of the flowchart)Have the libray paths been updated?

Click COMPILE & VERIFY. This was where you were when youdiscovered that there were missing libraries.

COMPILE MODIFIED LIBRARIESThe same message appears as before! Why?All the library source files have been created and compiled. But the systemis not finding them.

OK to close the window.

5. Clarify the mystery… in a BT-BASIC window: cat cat "custom_lib"

The files are there. Why did Board Consultant not find them?What is the path to these parts? custom_lib

Click VIEW / EDIT LIBRARY DATA Select ENTER LIBRARY PATHS In the LIBRARY PATHS FORM Place the mouse cursor on the first line. Press F9 Ins Line (On The Keyboard) Add custom_lib

It should look like: custom_lib /<path2>/library/ttl /<path>/library/cmos …

Click Update | CloseNow Board Consultant will look in the Custom_lib directory…

2 On the HP-UX system the <path> = /hp3070/

On the Personal Computer the <path> = D:/Agilent3070/

Click COMPILE AND VERIFY under View / Edit Library Data Click COMPILE MODIFIED LIBRARIES

The Confirm Message readsA library compile needs to be done …

Click OK. The compile should succeed.

Click COMPILE MODIFIED SAFEGUARD FILESSafeguard will be explained later. For now, the compile should be successfulafter you okay the compilation

Click OK to allow the compilation and OK again to close the window3.

VERIFY MISSING LIBRARIESAll the library source files should exist.The switches are listed again as devices without a library, but because theyare marked Not Testable, their absense is okay.Library devices within Part Description Libraries are not analyzed duringthis process. (E.g.: The nine resistors within the 1910-1000 package.)

Click CLOSE

VERIFY DISABLE METHODS EXISTDisable Methods exist for all (0) bussed pins.Because of the 33 Ohm series resistors, none of the digital devices share abus.Another reminder about the switches. If you intended to test these switches,libraries would have to be created for the switches. Remember the switchesare used for fault simulation. A "real" board would not have these switches.

VERIFY DISABLE NODES USABLEThe software checks to see that a device test does not have an output enable(or similar disabling pin) tied directly to ground or Vcc. The information thatis needed is not available because the device tests have not been created.Test Consultant will create the individual device tests. Presently only thelibraries exist not the individual tests for each digital device.

VERIFY TIED NODES DATAThe software checks to see that device pins that are not listed as power pinsare tied directly to ground or Vcc. If pins are tied to a fixed node, youreceive a message. While you may not be able to change the design, youshould be aware of the potential problems that tied pins create.2 of 94 pins examined are tied high or low. U4.2 and U5.2.

VERIFY - SHOW BOUNDARY SCAN CHAINSSkip these two selections. There are no boundary scan circuits on this board.

3 Your safeguard may already be "up to date" and therefore, the message may read, compile is not

needed. Clicking OK will do the right thing either way.

SHOW … LIBRARYUse the next three selections to see where the software has found librarysource files for the devices on your printed circuit board. These selectionssort the information in three different ways.

Sort all three ways to see the information each provides.

6. COMPILE & VERIFY (on the left side of the flowchart - below Test System Data).You have already developed the "config" file, so you do not need to review theinstructions for developing your “config” file.

Click on COMPILE “CONFIG” FILEThe message window says it needs to be compiled. But you compiled italready, during a previous lab. You also edited the source code (addeddocumentation) after the compile. Therefore, the object is older than thesource code and Board Consultant wants the object file to be more current.

Click on OKThe configuration compile should be successful (No errors, No warnings)

7. Verify Fixture Type: Click VERIFY FIXTURE TYPE

The software compares the fixture defined for use in the Fixture Options ofTest System Data with the “config” file. The configuration and the fixturetype and size are consistent

8. Verify Configuration Size Click on VERIFY CONFIGURATION SIZE

The software forecasts the number of probes needed to test the board.It compare that against the number of testhead resources in the “config” file.

− The result of the comparison is a summary table at the top of the form.If it looks like there will be enough testhead resources; you simplycontinue the development process.If the testhead will definitely not have enough resources, you mustdecide on the proper action for the specific board being developed.(This might include reducing the number of probe locations orincreasing the number of testhead resources.) The Angela board will fitfine. The node count and General Purpose relay is well within the"config" files capability.

9. Do not run Access Consultant. Access Consultant is used by optional software that isbeyond the scope of this class. This software includes MagicTest, DriveThru andAdvanced Boundary Scan.

10. Show Devices Using TestJet / Polarity Check / Connect Check Click on SHOW DEVICES USING POLARITY CHECK

None of the 12 capacitors use Polarity Check.One is marked for future testing with Polarity Check. This is C7.

Click on SHOW DEVICES USING TESTJETSeven of the 19 digital devices and connectors will be tested using TestJet.

Click on VERIFY BOTTOM KEEPOUTS FOR TESTJET…If there were TestJet tested devices on the bottom of the board, the softwarerequires their outlines be described and keepout regions defined. Thisprevents the software from placing probes or personality pins that wouldconflict with the TestJet probe.

Click SHOW DEVICES USING DRIVETHRUNone of the devices use DriveThru

Click SHOW DEVICES USING CONNECT CHECKNone of the devices use Connect Check.

Click VERIFY NODE PROBING ACCESSAll (111) nodes examined have adeuate probing access. All the guardednodes have optimal access.

Click VERIFY POWER NODE PROBING ACCESSAll (1) power nodes examined have sufficient, good probing access.

Click VERIFY GROUND NODE PROBINGThe ground node has sufficient, good probing access.

For Power and Ground nodes, the software determines the number of probesneeded to carry the current specified in the Power Supply form. The softwareverifies that there are enough probeable locations to satisfy the calculatedcurrent and voltage signals.

11. FINAL COMPILE & VERIFY Click FINAL COMPILE & VERIFY Click SAVE BOARD FILES

It is always good to save often.

Click COMPILE BOARD FILEThe "board" file must be compiled successfully.The board should compile successfully with 0 Errors and 17 Warnings.Scroll through the Board Consultant Message window for details.

If it does not compile successfully:Open the Board Consultant Message window and read the error message.This should lead you to a skipped instruction or typing error. If you cannotresolve the conflict within two minutes, ask for help.

Click COMPILE BOARD_XY FILEThe "board_xy" file must be compiled successfully before Board Consultantis finished. The board_xy should compile successfully with 0 Errors and 23Warnings.

If it does not compile successfully:Open the Board Consultant Message window and read the error message.This should lead you to a skipped instruction or typing error. If you cannotresolve the conflict within a minute or two, ask the instructor for help.

Click GENERATE X-Y PLOT(Not available on the Windows platform.)The X-Y plot file can be plotted with a 1:1 ratio. If you plot it on atransparency, you can compare it to a real printed circuit board and verifythat the 3070's description matches the physical board.

The following Selections are grayed out because the information required forthese reports has not been generated. After the Test Consultant Lab theinformation from IPG (Interactive Program Generator) will be available.

Click SHOW IPG DEVICE SUMMARY

Click VERIFY IPG DEVICE DISABLE RESULTS

Click VERIFY SAFEGUARD INHIBIT RESULTS

12. Generate a "testability.rpt" file. Click TESTABILITY REPORT

This creates the report.

13. Assuming your compiles both succeeded without errors, you are now through withAgilent Board Consultant. (At least for the moment. You will reopen the interfaceand generate another "testability.rpt" file after running Test Consultant.)

Click FILE | EXITOR

Iconify the interface.

NOTE: Do not use this sequence: Save Boards \ Compile Boards \ SaveBoards again.This will corrupt the "board" and "board_xy" files. The board files must besaved before compiling, but after they have been compiled, do not save themagain. The software uses a time stamp based on the last time the file wassaved. If a "board" file has been saved more recently than its object, thesoftware assumes the object is out-of-date and will not use it.

14. Load and analyze the "testability.rpt" report.In a BT-BASIC window,

msi "<home path4>/angela_bd" get "testability.rpt"

First a look at the Summary Section

Analyze the "Results have been Derived From…" section:− What input information was used?

RESULTS HAVE BEEN DERIVED FROM: [x] Board description and config entries [x] Information from library objects [ ] Information from bsdl objects [ ] Information from test generation [ ] Information from test compiltation

− Are there missing libraries? (Yes/No)

Analyze the Polarity Check, TestJet and Connect Check test sections:− None of the capacitors require Polarity Check.− How many of the integrated circuits did you mark for TestJet? ____− None of the TestJet probes need to be mounted in the Probe Plate, so

there is no need for Keepout entries.− No devices are tested with Connect Check.

Assuming your results were typical, you can iconify or exit the BT-BASICwindow.

Iconify the Board Consultant interface. You will use it again during the nextlab, but for now, set it aside.

This concludes this part of the lab.

Continue to the Test Consultant lab.

4 On the HP-UX system: <home path> = /hp3070/home/user<#>

On the Personal Compuer: <home path> = D:/Agilent3070/home/user<#>This is the last time in the manual where the "home path" will be explained. In the future, themanual will use this term and expect everyone to remember what it means.

LAB 07B: Use Agilent IPG Test Consultant

During the previous labs, you:

• Created a directory to contain the board description.• Created a "config" file for the board.• Started Agilent Board Consultant and developed much of the description of

the Angela Board.• Discovered that there were missing libraries for the Angela Board.• Used the Part Description Editor to create a library for some of the missing

devices.• Used the Digital Setup Editor to create a library for the last missing device.• Completed the board description using Board Consultant.• Successfully compiled the "board" and "board_xy" files.

Now you will:

• Run Agilent IPG Test Consultant to create the fixture and test files.

Check your resources:

• During this lab: Generate the fixture files needed to build a test fixture andgenerate the files used to test the devices.

• All work is done at the development stations; no testhead is required.• The board is the “angela_bd”.

This lab is done at the test development workstation.

1. Start Agilent IPG Test Consultant and verify the path is to the Angela Board.HP-UX USERS

Click on the 3070 icon for the pop-up menu. Click on Test Consultant.

OR Double click on the Test Consultant icon to restore it. The path should be: /home/user<#>/angela_bd

MS WINDOWS USERS Click the Test Consultant shortcut on the desktop The path should be: D:/Agilent3070/home/user<#>/angela_bd

EVERYONE

SPECIAL INSTRUCTIONS. THE FOLLOWING STEPS MUST BE DONE FORTHE CLASS, BUT ARE NOT PART OF THE USUAL DEVELOPMENTPROCESS.

2. Test Consultant creates a test fixture. But, the class already has test fixtures. Theexisting fixtures were built using pre-release software, in 1989. Since then, theyhave been modified to conform to evolving software requirements.If you let Test Consultant run today, it will design a similar, but different fixture.Therefore, to use the existing fixtures, you must include two files in your directorythat describe the existing fixtures to Test Consultant. Then the tests you generate willwork with the existing fixtures.One file is the "wirelist.o". The second is the "fixture.o" file that must reside in the"fixture" subdirectory. The "fixture" subdirectory does not exist, so create it.

Using a BT-BASIC window:

msi "<home path>/angela_bd create dir "fixture"

HP-UX USERS

These commands should be entered on one line:

copy "/hp3070/boards/sources/angela_bd/wirelist.o" to"wirelist.o"

copy "/hp3070/boards/sources/angela_bd/fixture.o" to"fixture/fixture.o"NOTE: You need to copy the source directory's fixture.o file into your local fixturedirectory as the fixture.o file.

MS WINDOWS USERS

These commands should be entered on one line:

copy "D:/Agilent3070/boards/sources/angela_bd/wirelist.o" to"wirelist.o"

copy D:/Agilent3070/boards/sources/angela_bd/fixture.o" to"fixture/fixture.o"NOTE: You need to copy the source directory's fixture.o file into your local fixturedirectory as the fixture.o file.

EVERYONE

BACK TO THE USUAL DEVELOPMENT PROCESS…

3. Step one of the generation process: Click ACTIONS | DEVELOP BOARD TEST

(The Enter Board Data selection will open Board Consultant.)(The Add a Test selection is an alternate method of modifying the boarddescription after the fixture and tests already exist.)The "Dependencies Calculation" window is created.

4. Step two of the generation process: Restore the Test Consultant Message window to watch the many activities

involved in creating the fixture and test files.

Click ACTIONS | BEGIN BATCH DEVELOPMENT(The Interactive development is sometimes used to modify the fixture andtests after an Engineering Change Order or board redesign.)

5. When complete, close the interface. Assuming the generation process ran successfully, click FILE | EXIT to

close the Test Consultant interface. If there were failures, notify the instructor.

6. Verify that the expected files and directories were created. In a BT-BASIC window,

msi "<home path>/angela_bd"

Get a catalog of the directory, cat; short Verify the following files and directories are included:

analog* board board.o board_xyboard_xy.o board_xy.p config config.odebug* digital* fixture* ipg*shorts shorts.o summary testability.rawtestability.rpt testjet testjet.otestorder testplan wirelist.o* Indicates a directory.Other files may be included, especially backup files. Backup files aredenoted with a "~" appended to the file name.

Examine some of the files. You need to be familiar with most of these and othersyou will need to know in detail.In the BT-BASIC window:

get "testplan" Review the contents of "testplan".

NOTE: The details of this file will be explained when the class reviews eachtest.

Scroll past all the overhead and initialization information.

Find the MAIN LOOP FOR REPEATEDLY TESTING A BOARD. On the command line, enter number

This gives you the current line number in the testplan. ______This is where the software waits for the operator to load a board on thefixture and press the START key. When it is pressed, testing begins.There is a single line, call Test_Sections that branches to the testroutines and performs all the tests.

Find and examine the Set_Custom_Options routine.Use the command findn "Set_Custom"What is the line number here? ______

Scroll down to the "END OF TESTMAIN" label. Below this label are thetest routines. What is the line number here? ______

Scroll down to see the subroutines that call the tests for Shorts, AnalogIncircuit, TestJet, and the Setup_Power_Supplies routine. Find the call forthe Digital tests and the Analog Functional tests.

You are at the bottom of the "testplan". How many lines are in the entirefile? ______(This number will vary with the size of the board and types of tests used.)

7. Reopen Board Consultant Restore Board Consultant from the icon or restart it. Click LOAD EXISTING BOARD

Because Test Consultant has changed the "board" and "board_xy" files, youneed to reload the information in the interface.

Give the path: /<home path>/angela_bd Click TESTABILITY REPORT.

This generates a new "testability.rpt". The first time, the file predicted howTest Consultant would process the board. This time, the report will useactual information from the board test to define its parameters.

NOTE: Do not resave the board files again. If you resave the files now, theobject files will be out of sequence.

Click FILE | EXIT to close Board Consultant.

8. Open a BT-BASIC window and evaluate the "testability.rpt" again. msi to the correct path and load "testability.rpt" Analyze the access information (many of these were checked individually

earlier in the lab):− Are any of the integrated circuit's pins tied directly to VCC or GND?

(Yes/No)− Can you disable any/all of the bussed devices? (Yes/No)− Are any of the enable/disable pins inaccessible? (Yes/No)− How many nodes are on the printed circuit board? ____− How many nodes can be probed? ____− How many power supplies are needed? ____− Are there enough probe locations to satisfy the current requirements of

the power and ground connections? (Yes/No)− Are there enough testhead resources to test the board? (Yes/No)− How many nodes are on the printed circuit board according to the

DEVICE TEST RESULTS table? ____There are more here than evaluated above. Why?(Hint: How many power nodes are there?)

− Are there any devices not tested? (Yes/No)− How many devices will have tests written, but the tests will be

commented - not used? ____(You will see the specific devices listed later.)

− How many devices will have test written, but the quality of the testswill be limited? ____(You will see the specific devices listed later.)

− Can all the digital devices that need to be disabled be disabled?(Yes/No)

− Are there any tests Safeguard Inhibited? (Yes/No)

The next section is the Testability Report Details section. It containsinformation that is more specific.

− Most of the information appears to be identical.− The actual testhead configuration is listed in the Configuration Size

Results section.

In the Device Test Results section, you have additional details too.− How many known shorts are on the board? ____− How many of the library tests are Setup Only Tests? ____− Do any devices have "commented tests"? YES/NO

How many? ____________

− What is a "commented test"?A "commented test" is a test that is written but not used. The circuitaround the device makes this device so difficult to test that the softwarehas to widen the test limits to the point that the test is essentiallyineffective.

− Which devices have "limited tests" written? ______________

What is a "limited test"?A "limited test" is one written but because of the surrounding circuitry, thetest tolerances had to be widened. The wider tolerances were not so wide asto be a "commented test," but were wider than desired.

9. Open the "fixture/details" file and see if the software wants to modify the existingtest fixture.

get "fixture/details" find "Difference Report" Scroll down to see the number of wires removed and added. Both values

should be zero. If not, tell the instructor and explore further. Sometimes the software will

add an additional ground wire.

10. Close Board Consultant and Test Consultant.

This concludes this lab.

Appendix

Board Consultant Conventions• When using a device entry form, you can move from field to field with the

TAB key.• When entering a device value the software recognizes notation such as k for

kilo-, m for milli-, M for mega-, u from micro-, n for nano-, etc.• When entering the Device Outline, you can Capture Graphic Device Outline

which uses some default values for the outline information. This is usuallyample for the 3070's purposes. However, if the device outline is incorrect (asseen in the graphics window), you can override the captured values and enteryour own values manually.

• Tolerance Multiplier, Remote Sensing and Adjust Options are defined in theGlobal Options form. However, you can override those global settings forany specific device(s). E.g.: You can set your Global Tolerance Multiplier at5, then set the Tolerance Multiplier for a specific device to 0.1 or 10.

• All the device entry forms include a description of the probe locationattributes. You can change this description as needed.

− mandatory:Force the system software to locate the probe at the specified location.

− preferred:This marks the specified location as the one you would like to seeprobed if there are no other considerations that would prevent thislocation from being used.

− normal:The software will process this node without special consideration.

− unreliable:This marks the location as one to use but only if no others are available.

− extra:It is possible that there are probeable locations on the PC board that donot appear as specific components in the data entry. Typically thiswould be a location for an additional part to be added in the future. Ifthe exact coordinates for this location are known, the software willallow you to enter them now so the fixturing software will include holesin the fixture for the device if needed in the future.

− no_probe:This tells the software that the associated location is prohibited frombeing a valid probe location, because you say it is not to be probed.There is a table in the On-Line Help (CDE-HELP) that will helpillustrate when to use this.

− critical:Force the system software to locate the probe at the specified location.This is required to minimize the wire length from the testhead resourceto the node location.

− top:Specifies that the indicated location is only accessible from the top ofthe PC board.

− bottom:The default, this is node is processes without special consideration.

− both:Specifies that the location is accessible from either the top or bottom ofthe PC board. A via that is plated from the top to bottom would qualifyfor this designation.

− manual:This is the default and assumes that while testing this board (on thefixture) you can place a hand-held probe on this node. This is importantwhen using features like Digital Backtrace, but not critical for mostapplications.

− no_manual:Indicates that the location cannot be probed with the guided probe. Thiswould apply to a trace between two surface mount devices on thebottom of the board. When the vacuum is applied and the board is beingtested, there is no way for you to manually probe that node.

module 07 board consult ii & test consultant

toolscamcad translator bt

digital setup editor

printed circuit board

test development station

good probing access

ux users click

final compile

running test consultant

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