metal oxide semiconductor field effect transistors...

Department of EECS University of California, Berkeley

EECS 105 Spring 2017, Module 3

Prof. Ali M. Niknejad Prof. Rikky Muller

Metal Oxide Semiconductor Field

Effect Transistors (MOSFETs)

EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller

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Announcements

l  Pick up Midterm 1 if you haven’t already! l  Two options: (1) from my office hours, or (2) from

lecture today

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EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller

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MOSFET Cross Section

l  Add two junctions around MOS capacitor l  The regions forms PN junctions with substrate l  MOSFET is a four terminal device l  The body is usually grounded (or at a DC potential) l  For ICs, the body contact is at surface

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p-type substrate

n+ n+

source drain diffusion regions

L

gate body

p+

EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller

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MOSFET Layout

l  Planar process: complete structure can be specified by a 2D layout

l  Design engineer can control the transistor width W and L

l  Process engineer controls tox, Na, xj, etc. University of California, Berkeley

p-type substrate

n+ n+

S D G

B

p+

B S D

L

L

W

contact poly gate

jx

G

EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller

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PMOS & NMOS

l  A MOSFET by any other name is still a MOSFET: –  NMOS, PMOS, nMOS, pMOS –  NFET, PFET –  IGFET –  Other flavors: JFET, MESFET

l  CMOS technology: The ability to fabricate NMOS and PMOS devices simultaneously

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p-type substrate

n+ n+

S D B

p+ L jx

n-type substrate

p+ p+

S D B

n+ L jx

NMOS PMOS

G G

EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller

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CMOS

l  Complementary MOS (CMOS): Both P and N type devices l  Create a n-type body in a p-type substrate through

compensation. This new region is called a “well”. l  To isolate the PMOS from the NMOS, the well must be

reverse biased (p-n junction) University of California, Berkeley

n+ n+

S D B

p+ L jx

n-type well

p+ p+

S D B

n+ L jx

NMOS PMOS

G G

p-type substrate

EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller

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Circuit Symbols

l  The symbols with the arrows are typically used in analog applications

l  The body contact is often not shown l  The source/drain can switch depending on how the

device is biased (the device has inherent symmetry) University of California, Berkeley

NMOS PMOS

EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller

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Circuits!

l  When the inventors of the bipolar transistor first got a working device, the first thing they did was to build an audio amplifier to prove that the transistor was actually working!

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EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller

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A Simple Circuit: An MOS Amplifier

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DSI

GSV

sv

DR DDV

GS GS sv V v= +

ov

Input signal

Output signal

Supply “Rail”

EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller

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Plot of Output Waveform (Gain!)

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output

input

mV

EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller

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Observed Behavior: ID-VGS

l  Current zero for negative gate voltage l  Current in transistor is very low until the gate

voltage crosses the threshold voltage of device (same threshold voltage as MOS capacitor)

l  Current increases rapidly at first and then it finally reaches a point where it simply increases linearly

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GSV

DSI

TV

GSV

DSIDSV

EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller

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Observed Behavior: ID-VDS

l  For low values of drain voltage, the device is like a resistor l  As the voltage is increases, the resistance behaves non-linearly

and the rate of increase of current slows l  Eventually the current stops growing and remains essentially

constant (current source) University of California, Berkeley

DSV

/DSI k

“constant” current

resistor region

non-linear resistor region

2GSV V=

3GSV V=

4GSV V=

GSV

DSIDSV

EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller

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Operating Points

l  Which bias voltages you operate the MOSFET at will make a big difference in how it functions.

l  We will explore these regions of operation in this lecture. l  If we operate with a sufficiently high VGS AND a sufficiently

high VDS, we can make a very good small-signal amplifier! University of California, Berkeley

DSI

GSV

sv

DR DDV

GS GS sv V v= +

ov

Input signal

Output signal

Supply “Rail”

EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller

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Small Signal vs. Large Signal

l  We observe IDS vs. VGS to be quadratic for VGS > VT

l  Large changes in vGS result in quadratic changes at the output l  However, for small changes in vGS (denoted as vgs) will

produce linear changes at the output! l  We can show this using Taylor series expansion:

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VGS

DSI

TV

GSV

DSIDSV

iDS = k(vGS −VT )2;vGS =VGS + vgs

TS : iDS (vGS ) VGS = k(VGS −VT )2 + 2k(VGS −VT )vgs + kvgs

2

EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller

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Simple Small Signal Model for MOSFET

l  This is a simplified, 3-terminal small-signal model for a MOSFET

l  In later lectures we will develop a more complete model l  gm = transconductance

–  defined as dids/dvgs, units [Ohms]-1

l  ro = output resistance –  defined as [dids/dvds]-1, units Ohms

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NMOS

EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller

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Small Signal Gain Example

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DSI

GSV

sv

DR DDV

GS GS sv V v= +

ov

Input signal

Output signal

Supply “Rail”

l  Steps to analyze small signal amplifiers: l  1. Calculate bias points using DC sources

–  As you will see in later lecture, you will use these bias points to determine the MOSFET region of operation as well as to calculate small-signal parameters

l  2. Turn off DC sources l  3. Plug in the small-signal model for a MOSFET

EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller

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Small Signal Gain Example

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l  4. Calculate the gain (vout/vin) of the circuit

Department of EECS University of California, Berkeley

EECS 105 Spring 2017

MOSFET Large Signal Models and

Regions of Operation

EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller

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Cut-off, VGS < VT

l  This structure should look familiar! It is an MOS capacitor with two n+ diffusion regions on each side.

l  When VGS < VT, the device is either in accumulation or in depletion.

l  Since there are no (or few) inversion charges at the surface, therefore no current will flow regardless of the value of VDS. University of California, Berkeley

p-type

n+ n+ p+

Depletion Region

VGS <VT

100mVDSV ≈G

D S

NMOS

x

y

EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller

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“Linear” Region Current

l  If the gate is biased above threshold, the surface is inverted l  This inverted region forms a channel of inversion charges

(in this case electrons) that connects the drain and source – inversion charges originate from n+ diffusion

l  If a drain-source voltage (VDS) is applied positive, electrons will flow from source to drain

l  Note: electrons flow S à D, current flows D à S University of California, Berkeley

p-type

n+ n+ p+

Inversion layer “channel”

VGS >VT

100mVDSV ≈G

D S

NMOS

x

y

EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller

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MOSFET “Linear” Region

l  The current in this channel is given by

l  The charge proportional to the voltage applied across the oxide over threshold

l  If the channel is uniform density, only drift current flows

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DS y NI Wv Q= −

( )N ox GS TnQ C V V= −

( )DS y ox GS TnI Wv C V V= − −

y n yv Eµ= − DSy

VEL

= −

GS TnV V>( )DS n ox GS Tn DSWI C V V VLµ= − 100mVDSV ≈

EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller

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MOSFET: Variable Resistor

l  Notice that in the linear region, the current is proportional to the voltage

l  Can define a voltage-dependent resistor

l  This is a nice variable resistor, electronically tunable!

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( )DS n ox GS Tn DSWI C V V VLµ= −

1 ( )( )

DSeq GS

DS n ox GS Tn

V L LR R VI C V V W Wµ

⎛ ⎞= = =⎜ ⎟− ⎝ ⎠W

EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller

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Finding ID = f (VGS, VDS) l  Approximate inversion charge QN(y): drain

voltage is higher than the source à less charge at drain end of channel

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p-type

n+ n+ p+

GS TnV V>

DSVG

D S

NMOS

GS TnV V−

y=L y=0

EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller

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Inversion Charge at Source/Drain

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)()0()( LyQyQyQ NNN =+=≈

)()0( TnGSoxN VVCyQ −−== == )( LyQN)( TnGDox VVC −−

DSGSGD VVV −=

EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller

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Average Inversion Charge

l  Charge at drain end is lower since the vertical field is lower at that point

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( ) ( )( )2

ox GS T ox GD TN

C V V C V VQ y − + −≈ −

Source End Drain End

( ) ( )( )2

ox GS T ox GS SD TN

C V V C V V VQ y − + − −≈ −

(2 2 )( ) ( )2 2

ox GS T ox SD DSN ox GS T

C V V C V VQ y C V V− −≈ − = − − −

EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller

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Drift Velocity and Drain Current

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Use mobility to find velocity v

( ) ( ) ( / ) n DSn n

Vv y E y V yL

µµ µ= − ≈ − −Δ Δ =

Substituting:

( )2

DS DSD N ox GS T

V VI WvQ W C V VL

µ= − ≈ − −

ID =WLµCox (VGS −VT −

VDS2)VDS

Family of Inverted Parabolas

EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller

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Square-Law Characteristics

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Boundary: what is ID,SAT?

TRIODE REGION TRIODE REGION

EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller

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The Saturation Region

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When VDS > VGS – VTn, there isn’t any inversion charge at the drain … what happens?

Why do curves flatten out?

SATURATION REGION

EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller

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Why does current saturate?

l  The charge at drain end goes to zero once VGD < VT

l  We say that the drain end is “pinched off” –  If you pinch a hose, water flow stops ! –  But then how does current flow?

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EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller

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Pinch Off

l  Excess field beyond Edsat drops across tiny region between drain and channel –  Huge field means that electrons flow at very high

velocity across the “high field” region. –  They are injected from source end and are collected at

the drain end l  Increasing the drain voltage does not increase

current (appreciably) because the current is limited by the supply of electrons from channel side

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EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller

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Square-Law Current in Saturation

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Current stays at maximum (where VDS = VGS – VTn = VDS,SAT)

( )2DS

D ox GS T DSVWI C V V V

Lµ= − −

, ( )( )2

GS TDS sat ox GS T GS T

V VWI C V V V VLµ

−= − − −

2, ( )

2ox

DS sat GS TCWI V V

Lµ

= −

EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller

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Actual Saturation Current l  Measurement: ID increases slightly with increasing VDS: l  The physics is complicated, but a simple way to see this is that

the channel is getting shorter as the drain voltage depletes away more electrons from the drain end

l  We model this with an additional linear factor:

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2, ( ) (1 )

2ox

DS sat GS T DSCWI V V V

Lµ

λ= − +

EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller

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Channel Length Modulation l  When vDS = vGS-VT, the channel pinches off near the drain. With

further increase in vDS, the pinch-off point moves toward the source, effectively reducing the channel length from L to L-ΔL.

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ID =12µnCox

WL −ΔL

VGS −VT( )2

The continual increase of ID with VDS is modeled by

ID =12µnCox

WLVGS −Vtn( )2 1+λVDS( )

EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller

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Summary: Regions of Operation

l  Cut-off: VGS < VT –  IDS = 0 –  Note: this is an approximation we will make in EE105, in later

courses you will learn about sub-threshold conduction

l  Linear: VGS > VT, VDS << VGS – VT

l  Triode: VGS > VT, VDS < VGS – VT

l  Saturation: VGS > VT, VDS > VGS – VT

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2, ( ) (1 )

2ox

DS sat GS T DSCWI V V V

Lµ

λ= − +

IDS =WLµnCox (VGS −VT −

VDS2)VDS

IDS =WLµnCox (VGS −VT )VDS

EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller

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PMOS Device

l  So far, we’ve derived all of our equations for an NMOS device

l  PMOS devices work exactly the same way, but with an n-type body and a channel made of positive charges (holes)

l  The direction of the voltages and currents are inverted, for example:

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ISD,sat =WLµCox2(VSG −VTp )

2(1+λVSD )

EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller

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Next Lecture

l  In the next lecture we will learn how to analyze small-signal amplifiers, including –  Computation of bias points –  How to derive and compute small signal model

parameters (gm, ro) –  How to calculate small signal gain

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