many ways to build logic out of mosfetshomepage.cs.uiowa.edu/~bdmyers/cs2630_sp17/public/... ·...

ManywaystobuildlogicoutofMOSFETs

passtransistorlogic(mostsimilartothefirstswitchlogicwesaw)

staticCMOSlogic(whatwesawlasttime)

dynamicCMOSlogic• Clock=0precharges X

throughthepMOS• clock=1givesthetwo

nMOS timetodrainchargeonXtoground(ifAandBturnthemon)

Wikimediacommons

Switchesotherthantransistors

relays(electro-mechanical)

diodes

ORgate

Wikimediacommons

CS2630ComputerOrganization

CombinationallogicforarithmeticBrandonMyers

UniversityofIowa

Peerinstruction• Drawthecircuitforthefollowingtruthtable(thisonehas2inputs,2outputs)

In0 In1 Out0 Out1

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

Answerthenumberoflogicgatesusedwhenfinished;workinpairs

Wherewearegoing

Instructionsetarchitecture(e.g.,MIPS)

Compiler

Memorysystem I/OsystemProcessor

Datapath&Control

Digitallogic

translatingsourcecode(CorJava)ProgramstoassemblylanguageAndlinkingyourcodetoLibrarycode

HowthesoftwaretalksTothehardware

HowaprocessorrunsMIPSPrograms!

Howswitches(1or0)canbeusedtobuildInterestingfunctions:fromintegerarithmetictoprogrammablecomputers

Ingredientsforaprocessor• Combinationallogic• arithmeticandbitwiseoperations• multiplexors(pick1outofofNinputs)• controllogic• branchcalculation• addresscalculation

• Synchronouslogic(we’llgettotheselater)• registers• programcounter,orPC• datamemory• instructionmemory

startlearninghowtobuildthesecombinationallogiccircuits

Howdoweaddtwonumbersaddu $t0,$t1,$t2

Weknow:Thenumbersarephysicallystoredinregistersasbits

Thesumoftwonumbersisafunctionwecanimplementusingcombinationallogic

Startwitha1-bitadder

+

Sum

Carryout

A BCarryin

Peerinstruction:2-bitadder

+2-bit

Sum0

Carryout

A0B0Carryin

Sum1

A1B1

NumberofrowsoftruthtableforSum1outputof2-bitadder?

Howmanyrowsinthistruthtable?

4GBmemoryx8bit/byte=32Gbits

32registersx4Bytex8bit/byte=1Kbit

PCregisterx4Bytex8bit/byte=32bits

processortakesonestepfromcurrentstatetonewstate.Howmanyrowsinthetruthtableofbit0?

https://commons.wikimedia.org/wiki/File:Performance_PIPER_die.JPG

currentstate(theinput)

newstate(theoutput)

Administrivia• 2MidtermpracticesareonICON• takethemlikearealexamandthen checkyouranswerswiththesolutions

• DebugYourBrainnextWednesdaywillbededicatedtoreview• extraofficehour4-5pmonMonday2/27,tobededicatedtoHW3

• Reminder:Midterm3/6• opennotesopenbook,nodevices

https://en.wikipedia.org/wiki/Field-programmable_gate_array

Lookuptable(LUT)– aprogrammabletruthtableinhardware!

“3-LUT”means3inputs(somustprogram8rows)

Field-programmablegatearray(FPGA)

1-bitadder

programmableMUXselectsinputs

analternativetomanufacturingyourownsiliconchip

CS2630ComputerOrganization

AddersandtimingBrandonMyers

UniversityofIowa

Howhumansaddtwonumbers• compute65210 +36710 onpaper

• compute110102 +010112 onpaper

Buildinglargercircuitsoutofcomponents:2-bitadderbuiltfrom1-bitadders

+

Sum0

C1

A0 B00

+

Sum1

C2

A1 B1individualcomponentshavetheirownsmalltruthtables;thenwejustcombinethecomponents

32-bitadder

+

Sum0

A0 B00

+

Sum1

A1 B1

+

Sum2

A2 B2

+

Sum31

A31 B31

…

Reflect:WenowhaveacircuitforA+B.WhatisasmallchangewecanmaketogetA-B?

Undertherugofcombinationallogic:computationtime

PropagationdelaythroughlogicgatesResistor-capacitor(RC)modelofNOTgatewhengiveninput0

1à0 0à1

inputchanges

R

C

1à0 0à1

ChargingacapacitorinanRCcircuit

https://www.quora.com/How-does-a-RC-circuit-work-especially-the-charges-on-the-capacitor

PropagationdelaythroughlogicgatesResistor-capacitor(RC)modelofNOTgatewhengiveninput0

1à0 0à1

inputchanges

R

C

Whentheinputchangesfrom1to0,thereisadelaybeforetheoutputoftheNOTgatereaches1

drainingthecapacitorwheninputgoes0à1

0à1

1à0 0à1

Backuptotheleveloflogicgates• InCS2630,whenwethinkaboutdelay,we’llusethefollowingsimplifiedmodel• propagationdelayishigherformorecomplexgates• propagationdelayincreaseswiththenumberofinputstoagate

• e.g.,2-inputORgateisfasterthana3-inputORgate• propagationdelayofasequenceofgatesisadditive• allinputsmustbeavailablebeforelogicgatebeginscomputing

T=0 T=0.5 T=1 T=1.5

Example:assumedelayofinverteris0.5ns

Delayofaddercircuit

+

Sum0

A0 B00

+

Sum1

A1 B1

+

Sum2

A2 B2

+

Sum31

A31 B31

…

1-bitadderdelay:sum=21-bitadderdelay:carry=1

Peerinstruction:delaytogetSum31?

Delayofaddercircuit

+

Sum0

A0 B00

+

Sum1

A1 B1

+

Sum2

A2 B2

+

Sum31

A31 B31

…

1-bitadderdelay:sum=21-bitadderdelay:carry=1

Thisadderiscalled“ripplecarryadder”

Next…• Wenowknowhowonekindofadderworksandhowlongittakestocomputetheresult• Canwebuildfasteradders?Yes!Usehierarchy/trees

Administrivia• Reminders:• extraofficehour4-5pmtodayforHW3• DYBthisweekdedicatedtoreview• MidtermonMonday3/6:opennoteopenbook,nodevices

Carry-selectadder

Peerinstruction

WhatisthedelayfromthetimeAandBareavailabletowhenSumisavailable?

delays:sum:1carry:1mux:1

Administrivia• Reminders:• DYBtonight6-7pmdedicatedtoreview

• bringyourprioritizedlistofspecificproblemsorquestionsthatyou’dliketoreview

• itwillbemostusefulifyoutakethepracticeexam(s)first• MidtermonMonday3/6:opennoteopenbook,nodevices

Peerinstruction

WhatisthedelayfromthetimeAandBareavailabletowhenSumisavailable?

delays:sum:1carry:1mux:1

1

1

22

3

3

1

1

11

2

4

4

timesignalisavailableshowninred/bold

http://www-inst.eecs.berkeley.edu/~cs150/sp13/agenda/lec/lec20-adders.pdf

computecarries

usecarriestofinishthesums

Bestcasedelayofadders?O(logn)pmeans“propagateacarry”gmeans“generateacarry”

important:pandgarenotfunctionsofc

Bestcasedelayofadders?O(logn)

http://www-inst.eecs.berkeley.edu/~cs150/sp13/agenda/lec/lec20-adders.pdf

computecarries

usecarrys tofinishthesums

criticalpath

Multiplication• Evaluate50110 x42210 onpaper

• Evaluate11002 x10012 onpaper

Aside:usefullogiccircuitnotation

Shiftingbyaconstant

Variableshifter:firstattemptwith1-bitmuxes

Variableshifter,similardesignwith8-bitmux

Canyouthinkofadesignthatavoidsusingahuge8-bitx8-choicemux?

e.g.,usingonly8-bitx2-choicemuxes andhardwiredshifters?

hardwiredshiftsbyeachpossibleshiftamount

pickwhichoneusingtheshiftamount

Multi-stageshifterusingthemagicofbinarydecision-making• Hint:RecalltheenvelopesfromHW1

anothersolution(butusesmore2-inputMUXs)istobuildthe8-inputMUXonthepreviousslideusing2-inputMUXs,likeasoccertournamentwith8teamsandonechampion

Peerinstruction• Builda2-bitmultiplier(4-bitoutput)• youmayuseanynumberof

• exampletestcases:• 01*01=0001• 10*01=0010• 10*11=0110• 11*11=1001