manufacturing process
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Manufacturing Process
http://www-micrel.deis.unibo.it/CEDLA
General info Date esami:
Giugno Luglio
Sito per le slide o il materiale delle esercitazioni:
http://www-micrel.deis.unibo.it/CEDLA Tutor del corso: ing. Elisabetta Farella. Per contattare il tutor: tutorcedla@gmail.com
The MOS Transistor
n+n+
p-substrate
Field-Oxyde
(SiO2)
p+ stopper
Polysilicon
Gate Oxyde
DrainSource
Gate
Bulk Contact
CROSS-SECTION of NMOS Transistor
The MOS Transistor
Polysilicon Aluminum
Cross-Section of CMOS Technology
A Modern CMOS Process Dual-well approach
Circuit Under Design – Symbolic representation
VDD VDD
VinVout
M1
M2
M3
M4
Vout2
Its Layout View
The Manufacturing Process
The Silicon Wafer
Single-crystal ingot
Sliced wafers
Important metric: defect density of the base material
10-30 cm diameters, 1mm thickness Doping: 2x1021 impurities/m3
Diamond sawSeed crystal
Molten Silicon Bath andCzochralski method
2:00 – 4:15
Clean Rooms
Photolithography
1. Oxidation layering 2. Photoresist coating 3. Stepper exposure 4. Photoresist development and bake 5. Acid Etching 6. Spin, rinse, and dry 7. Various process steps 8. Photoresist removal (or ashing)
oxidation
opticalmask
processstep
photoresist coatingphotoresistremoval (ashing)
spin, rinse, dryacid etch
photoresist
stepper exposure
development
Typical operations in a single photolithographic cycle (from [Fullman]).
Photo-Lithographic Process
Example: Patterning of SiO2
Si-substrate
Si-substrate Si-substrate
(a) Silicon base material
(b) After oxidation and depositionof negative photoresist
(c) Stepper exposure
PhotoresistSiO2
UV-lightPatternedoptical mask
Exposed resist
SiO2
Si-substrate
Si-substrate
Si-substrate
SiO2
SiO2
(d) After development and etching of resist,chemical or plasma etch of SiO2
(e) After etching
(f) Final result after removal of resist
Hardened resist
Hardened resist
Chemical or plasmaetch
Scaling is getting mask-based steps more and more challenging
Done in parallel on the entire wafer
Recurring processing step (1) DIFFUSION and ION IMPLANTATIONDoping recurs many times. Two approaches:
DIFFUSION IMPLANTATION: wafers in quartz tube in a heated furnace (900-1100 °C); dopants in gas diffuse in the exposed surface vertically and horizontally. more dopants on the surface than deeper in the material
ION IMPLANTATION (+ annealing): dopants introduced by directing a beam of purified ions over semiconductor surface. Ions accelerations deepness of penetration; Beam current and exposure time dosage. lattice damage. Repair by ANNEALING step (heating based)
A wafer handling tray in ion implantation
The magnets used to control the ion beam
Diffusion furnace
Recurring processing step (2) DEPOSITIONRepetitively, material is deposited over the wafer
(buffering, insulating, etc.). Different techniques depending on materials
Chemical vapor deposition (CVD): gas-phase reaction with energy supplied by heat (850°C). Ex. Si3N4
Chemical deposition: Silane gas over heated wafer coated with SiO2 = Polysilicon non-crystalline amorphous material
Sputtering for Alluminium interconnect layers. Alluminium evaporated in vacuum, heated by electron-beam or ion-beam bombarding.
… etc.
Recurring processing step (3) ETCHINGTo selectively form patterns (wires, contact
holes) Wet etching – use of acid or basic solutions Dry or plasma etching – well defined
directionality (sharp vertical contours)
PLANARIZATIONTo ensure a flat surface a chemical-
mechanical planarization (CMP) step is included before deposition of extra-metal layer on top of insulating SiO2
CMOS Process at a GlanceDefine active areasEtch and fill trenches
Implant well regions
Deposit and pattern polysilicon layer
Implant source and drainregions and substrate contacts
Create contact and via windows Deposit and pattern metal layers
CMOS Process Walk-Through
p+
p-epi (a) Base material: p+ substrate with p-epi layer
p+
(c) After plasma etch of insulatingtrenches using the inverse of the active area mask
p+
p-epiSiO2
3SiN
4
(b) After deposition of gate-oxide andsacrificial nitride (acts as abuffer layer)
CMOS Process Walk-ThroughSiO2
(d) After trench filling, CMP planarization, and removal of sacrificial nitride
(e) After n-well and VTp adjust implants
n
(f) After p-well andVTn adjust implants
p
CMOS Process Walk-Through
(g) After polysilicon depositionand etch
poly(silicon)
(h) After n+ source/drain andp+ source/drain implants. These
p+n+
steps also dope the polysilicon.
(i) After deposition of SiO2insulator and contact hole etch.
SiO2
CMOS Process Walk-Through
(j) After deposition and patterning of first Al layer.
Al
(k) After deposition of SiO2insulator, etching of via’s,
deposition and patterning ofsecond layer of Al.
AlSiO2
Advanced Metallization
Advanced Metallization
Design Rules
3D Perspective
Polysilicon Aluminum
Design Rules
Interface between designer and process engineer
Guidelines for constructing process masks
Unit dimension: Minimum line width scalable design rules: lambda
parameter absolute dimensions (micron rules)
CMOS Process Layers
Layer
Polysilicon
Metal1
Metal2
Contact To Poly
Contact To Diffusion
Via
Well (p,n)
Active Area (n+,p+)
Color Representation
Yellow
Green
Red
Blue
Magenta
Black
Black
Black
Select (p+,n+) Green
Layers in 0.25 m CMOS process
Intra-Layer Design Rules
Metal24
3
10
90
Well
Active3
3
Polysilicon
2
2
Different PotentialSame Potential
Metal13
3
2
Contactor Via
Select
2
or6
2Hole
Transistor Layout
1
2
5
3
Tra
nsis
tor
Vias and Contacts
1
2
1
Via
Metal toPoly ContactMetal to
Active Contact
1
2
5
4
3 2
2
Select Layer
1
3 3
2
2
2
WellSubstrate
Select3
5
CMOS Inverter Layout
A A’
np-substrate Field
Oxidep+n+
In
Out
GND VDD
(a) Layout
(b) Cross-Section along A-A’
A A’
Layout Editor
Design Rule Checker
poly_not_fet to all_diff minimum spacing = 0.14 um.
Sticks Diagram
1
3
In Out
VDD
GND
Stick diagram of inverter
• Dimensionless layout entities• Only topology is important• Final layout generated by “compaction” program
Packaging
Packaging Requirements
Electrical: Low parasitics Mechanical: Reliable and robust Thermal: Efficient heat removal Economical: Cheap Size: small
Bonding Techniques
Lead Frame
Substrate
Die
Pad
Wire Bonding
Tape-Automated Bonding (TAB)
(a) Polymer Tape with imprinted
(b) Die attachment using solder bumps.
wiring pattern.
Substrate
Die
Solder BumpFilm + Pattern
Sprockethole
Polymer film
Leadframe
Testpads
Flip-Chip Bonding
Solder bumps
Substrate
Die
Interconnect
layers
Package-to-Board Interconnect
(a) Through-Hole Mounting (b) Surface Mount(SMD)
(c) Ball Grid Array
Package Types
Package Parameters
Multi-Chip Modules
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