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EECS240 – Spring 2012
Advanced Analog Integrated Circuits
Lecture 1: Introduction
Elad AlonDept. of EECS
EECS240 Lecture 1 2
Course Focus• Focus is on analog design
• Typically: Specs circuit topology layout
• Will learn spec-driven approach• But will also look at where specs come from
• Key point:
• Especially in analog, some things are much“easier” to do than others
• Sometimes (often) the right thing to do ischange the specs
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EECS240 Lecture 1 3
Course Goal
• Learn how to create systematic approaches
to analog design
• Based on fundamental principles
• For a wide variety of applications
• Will show specific design methodology
example
• OTA designs embedded in ADCs
• And then move on to a more complex system
EECS240 Lecture 1 4
Teaching Staff • Elad’s office hours
• 519 Cory Hall
• Tues. and Thurs. 11am-12pm (right after class)
• GSI: Pierluigi Nuzzo
• Weekly discussion session/office hours times TBA
• (Most likely Fri. afternoons in 550 Cory)
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EECS240 Lecture 1 5
Administrative
• Course web page:http://bwrc.eecs.berkeley.edu/classes/icdesign/ee240_sp12
• Lecture videos link TBA
• Will likely be posted on course website
• All announcements made through piazza
• Enroll in EE240 at:
http://www.piazza.com/berkeley/winter2012/ee240
EECS240 Lecture 1 6
Lecture Notes• Based on material from Simone Gambini,
Prof. Bernhard Boser, Prof. Ali Niknejad, and
myself
• Primary source of material for the class
• No required text – reference texts on next slide
• Notes posted on the web at least 1 hour
before lecture
• Will hand out limited # of hard copies in class
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EECS240 Lecture 1 7
Reference Texts
• Analysis and Design of Integrated Circuits,Paul R. Gray, Paul J. Hurst, Stephen H. Lewis, Robert G. Meyer,4th Ed., Wiley, 2001.
• Design of Analog CMOS Integrated Circuits,Behzad Razavi, McGraw-Hill, 2000.
• The Design of CMOS Radio-Frequency Integrated Circuits,Thomas H. Lee, 2nd Ed., Cambridge University Press, 2003.
• Analog Integrated Circuit Design,D. Johns and K.Martin, Wiley, 1997.
• The Designers Guide to SPICE & SPECTRE,K. S. Kundert, Kluwer Academic Press, 1995.
• Operation and Modeling of the MOS Transistor,Y. Tsividis, McGraw-Hill, 2nd Edition, 1999.
EECS240 Lecture 1 8
Grading• Grading:
• HW: 20%
• One HW roughly every two weeks
• Essential for learning the class material
• Need to setup HSPICE or equivalent simulator
(SpectreRF, Eldo, or other favorite tool)
• Project: 25%
• Groups of 2 – find a partner ahead of time
• Midterm: 20%
• Final Exam: 35%
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EECS240 Lecture 1 9
Homework
• Homework:
• Can discuss/work together
• But write-up must be individual
• Drop in box outside Elad’s office (519 Cory)
• Generally due 5pm on Thursdays
• No late submissions
• Start early!
EECS240 Lecture 1 10
Schedule Notes• ISSCC Week: 2/20 - 2/24 (no lectures)
• Midterm: March 8 (tentative)
• Spring break: 3/26 – 3/30
• Project:
• Part 1 due Apr. 12
• Part 2 due Apr. 20
• Part 3 due May 7 (tentative)
• Final: Wed., May 9, 11:30am-2:30pm
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EECS240 Lecture 1 11
“Analog ICs in a Digital World?”
Digital circuitry:• Cost/function
decreases by29% each year
• 30X in 10 years
Analog circuitry:• Cost/function may not scale very well
• Common complaints about scaling analog:
• Supply voltage is too low, device gain is low, horriblematching…
“Analog will die – everything will be digital!”• Who agrees?
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cost:cost:¢¢--per per --transistor transistor
Fabrication cost per transistor
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cost:cost:¢¢--per per --transistor transistor
Fabrication cost per transistor
EECS240 Lecture 1 12
(Good) Digital Design Needs Analog Insights
• Can synthesize large blocks at “medium”frequencies in ASIC flow, but
• Need to know transistors to design the cells
• Really need to know transistors to design memories
• Lots of analog issues to deal with when push digitalperformance, power, etc.
• Charge sharing, interconnect parasitics, etc.
• Matching growing concern in advanced CMOStechnologies
• Especially in memories
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EECS240 Lecture 1 13
Another Example
• Look at interfacebetween twodigital chips• Is received bit a
“1” or a “0”?
• Analog circuitscritical forreceiving bitscorrectly
TX RX
Initial eye
EECS240 Lecture 1 14
The More Fundamental Reason• The “real” or “physical” world is analog
• Analog is required to interface to just aboutanything
• Digital signals have analog characteristics too…
• In many applications, analog is in the critical path
• Examples:
• Wireline, optical communications• RF transceivers (receiver + transmitter)
• Sensors and actuators (e.g., MEMS)
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EECS240 Lecture 1 15
RF Receiver
• Why so many RF and analog buildingblocks?
• Why not just put the ADC right after theantenna?
EECS240 Lecture 1 16
RF Transceiver Layout
• Analog buildingblocks take upsignificant die area• Even in 0.18um…
Source: Mehta et al, “An 802.11g WLAN SoC”,JSSC Dec. 2005
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EECS240 Lecture 1 17
MEMS Accelerometer
DSP
A/D Conversion
Amplification
C/V conversion
MEMS
sensor
Acceleration
Digital Output
M. Lemkin and B. E. Boser, “A Three-AxisMicromachined Accelerometer with a C MOS
Position-Sense Interface a nd Digital Offset-TrimElec tronics,” IEEE J. So lid-Sta te Circ uits , vol. SC-34,pp. 456-468, April 1999
EECS240 Lecture 1 18
Digital Versus Analog Design• Abstraction in digital is Boolean logic (1’s, 0’s)
• Works because of noise margins
• At a higher level, it’s gates and registers (RTL)
• Digital layout is often automated
• Abstraction in analog is the device model
• (BSIM is a few thousand lines long)
• At a higher level, it’s the (opamps) (filters)(comparators)
• Abstraction depends on the problem you’re solving
• Analog layout is usually hand crafted
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EECS240 Lecture 1 19
“Analog” versus “RF”
• RF = “Analog with inductors”• RF signal is usually narrowband (i.e., sinusoidal)
• Tuned circuit techniques used for signalprocessing.
• RF impedance levels are relatively low• Can’t make antenna impedance too high
• Analog impedances are high (low) for voltage(current) gain.• Voltage/current gain versus power gain.
• “Mixed-signal” analog is often discrete time(sampled).
EECS240 Lecture 1 20
RF Shifting Toward Analog
• Classic RF uses inductors to tune the circuits
• Inductors are big – would be nice to get rid of them
• With increasing f T
, moving towards wideband
analog & feedback
• What’s the penalty?
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EECS240 Lecture 1 21
Mixed-Signal Design
• Many building blocks involve analog anddigital circuit co-design• PLLs, ADCs, etc.
• Sometimes hard to even distinguishbetween analog and digital• Is VCO analog, or digital?
Clk
PFD Regulator Vcp
Vreg
up
down
÷N
Ref_clk
+
-
EECS240 Lecture 1 22
Digitally-Assisted Analog
• In 90nm, one RF inductor (200µ× 200µ) takes same
area as a microprocessor!
• Leverage digital processing to improve analog circuits
• Good analog design doesn’t go away though
• Need to find right partitioning to maximize the benefit
Source: B. Murmann,“Digitally-Assisted
Analog Circuits – A
Motivational Overview,”
ISSCC 2007.
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EECS240 Lecture 1 23
Syllabus
• Devices (both passive and active):• Models, simulation, layout, and matching
• Electronic noise
• Basic support functions:• Current sources, references, biasing
• Basic analog “gate”: amplifier • Opamps, OTAs, feedback, settling time, common-
mode feedback
• Application driver: high-speed links or ADCs• Motivates additional building blocks
• As well as why you care about certain specs
• Data converters, comparators, offset cancellation,filters, sample & hold, oscillators, PLLs
EECS240 Lecture 1 24
EECS 240 versus 247• EECS 240
• Transistor level building blocks
• Device and circuit fundamentals
• A lot of the class at a low level of abstraction
• SPICE
• EECS 247• Macro-models, behavioral simulation, large
systems• Signal processing fundamentals
• High level of abstraction
• Matlab
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EECS240 Lecture 1 25
240 versus 242/142
• 142/242 mostly concerned with narrowbandcircuits operating at a “high” carrier frequency
• Signals mostly look like sinusoids
• Inductors ubiquitous
• Use of feedback is rare
• 240 focuses on more “wideband”, general-
purpose analog and mixed-signal
• Signals are “arbitrary”
• Spend a lot of time worrying about capacitance• Feedback common
EECS240 Lecture 1 26
240 versus 231• 231 concentrates on device physics
• 240: device physics abstracted to the extentpossible• Device models from a “circuit designer’s perspective”
• Treat transistor as black box described by complexequations
• Equations relevant for biasing, nonlinear effects(output swing), and some charge storage effects
• Mostly outside design loop
• “small signal analysis”
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