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IEEE Standard 1500 Based Interconnect Diagnosis
for Delay and Crosstalk Faults
Katherine Shu-Min Li, Yao-Wen Chang*, Chauchin Su, Chung-Len Lee, and Jwu E Chen**
National Chiao Tung University, National Taiwan University*, National Central University**
Outline
IntroductionOscillation Ring Test Scheme for Interconnect Detection and Diagnosis Interconnect Diagnosis AlgorithmOptimization Techniques for Interconnect Diagnosis Experimental Results Conclusion
Why Interconnect Testing and Diagnosis are Difficult?
Complexity issueToo many ringsConsider a bus-connected system
m cores, n bus linesAssuming each core passed by a ring at most once (a lower bound)
…
Core 1 Core 2 Core m
1 2 n
# rings of length I from n buses (connecting i cores):
niC
niC
# all rings:),min(
2
nm
ini
mi CC Exponential !
Introduction (Cont’d)
Interconnect dominates performanceInterconnect Diagnosis
SoC Design MethodologyIEEE Std.1500 Based Interconnect Diagnosis
Other Applications: PCB,MCM,SiPInterconnect Test
GoalInterconnect Detection Problem=>Pass/FailInterconnect Diagnosis Problem=>Fault Location
Target Fault ModelsDelay FaultCrosstalk Glitch FaultTraditional Stuck-at Fault, Open Fault
Oscillation Ring (OR) Based Test Scheme
Contribution of this WorkApply a heuristic algorithm to generate test rings quickly (Rt)
Previous Work on Oscillation Ring (OR) Based Interconnect Test Scheme for SOC
ASPDAC 2005Provide a fast diagnosability check algorithm
Similar to fast fault simulationProvide a heuristic algorithm to generate extra diagnosis rings
Similar to IORD test pattern generationPresent two optimization testing process
Concurrent ORAdaptive OR
Outline
IntroductionOscillation Ring Test Scheme for Interconnect Detection and DiagnosisInterconnect Diagnosis AlgorithmOptimization Techniques for Interconnect Diagnosis Experimental Results Conclusion
Oscillation Ring Test Scheme for Interconnect Detection and Diagnosis
Oscillation Ring Test SchemeTest ArchitectureEnhanced IEEE Std.1500-Compliant Wrapper Cell DesignEffectiveness
Delay Fault: longest & shortest ring in HP circuit (fmin vs. fmax)Crosstalk Glitch Fault: SoC simulation results
Oscillation Ring Test Scheme forInterconnect Detection Problem (IORT)Interconnect Diagnosis Problem (IORD)
C1
C2
Oscillation Ring W
TAM
System clock
counter for delay detection and measurement
…
SOC
…
…
…
…
Central counter counter for
crosstalk glitch detection
Test Architecture for Delay and Crosstalk Detection and Delay Measurement
Oscillation Ring Test Scheme for Interconnect Detection and Diagnosis
Oscillation Ring Test SchemeTest ArchitectureEnhanced IEEE Std.1500-Compliant Wrapper Cell DesignEffectiveness
Delay Fault: longest & shortest ring in HP circuit (fmin vs. fmax)Crosstalk Glitch Fault:
Oscillation Ring Test Scheme forInterconnect Detection Problem (ORT)Interconnect Diagnosis Problem (ORD)
IEEE Std.1500 Wrapper Cell Design
SI
IN
SO
1 0
OscTest To Core
normal wrapper
cell SI
OUT
From Core
normal wrapper
cell
0 1 OscTest
1 0
sel
OscTest
1 0
SO inv
(a) Input (b) Output
Modified with force Inversion
Oscillation Ring Test Scheme for Interconnect Detection and Diagnosis
Oscillation Ring Test SchemeTest ArchitectureEnhanced IEEE Std.1500-Compliant Wrapper Cell DesignEffectiveness
Delay Fault: longest & shortest ring in HP circuit (fmin vs. fmax)Delay Measurement
Crosstalk Glitch Fault:
1
1
2
3
4
5
6
7
8
Longest Test Ring in HP circuit
Simulated Waveforms of Longest and Shortest Test Rings of HP Circuit
Longest Ring of 38 ns
fmin= 21.316 MHz
Shortest Ring of 2.8 ns
fmax= 357.143 MHz
Oscillation Ring Test Scheme for Interconnect Detection and Diagnosis
Oscillation Ring Test SchemeTest ArchitectureEnhanced IEEE Std.1500-Compliant Wrapper Cell DesignEffectiveness
Delay Fault: longest & shortest ring in HP circuit (fmin vs. fmax)Delay Measurement
Crosstalk Glitch Fault:
Delay Measurement
0min
1Tf
Let fi be 4 MHz to 400 MHz (fmin = 4MHz, fmax = 400MHz )n
nff ii
be at least is 0.001
=>nmin 1000 =>T0 250 s
=> T0 = 250 s (OscTest Spec.)
Oscillation Ring Test Scheme for Interconnect Detection and Diagnosis
Oscillation Ring Test SchemeTest ArchitectureEnhanced IEEE Std.1500-Compliant Wrapper Cell DesignEffectiveness
Delay Fault: longest & shortest ring in HP circuit (fmin vs. fmax)Delay Measurement
Crosstalk Glitch Fault: longest ring in HP circuit with 5 wrapper cells
Crosstalk Glitch Fault Detection –longest ring in HP with 5 wrapper cells
Oscillation Signal
Glitches on victim net
Counteroutput
Crosstalk Glitch Detection (cont’d)
Oscillation Signal
Xtalk-induced Glitch
Detector output After 5 wrapper
cells
Counter output
Modified Input Wrapper Cell for Crosstalk Glitch Faults
Pulse detector –
an inverter
with special W/L
SI
IN
SO
1
0
OscTestTo Core
normalw rapper
cell
1
0
sel
Oscillation Ring Test Scheme for Interconnect Detection and Diagnosis
Oscillation Ring Test SchemeTest ArchitectureEffectiveness
Delay Fault: longest & shortest ring in HP circuit (fmin vs. fmax)Crosstalk Glitch Fault:
Oscillation Ring Test Scheme forInterconnect Detection Problem (IORT)Interconnect Diagnosis Problem (IORD)
Oscillation Ring Test Scheme
Single-Fault AssumptionInterconnect Detection Problem (IORT)
Pass or Fail=>Edge-Covering ProblemGoal: Fault Detection on Test RingsInterconnect Detection Model
Interconnect Diagnosis Problem (IORD)Fault Diagnosis=>Fault Location ProblemGoal: Optimal Resolution to Net SegmentInterconnect Diagnosis Model
An Example SOC Circuitfor Interconnect Test
C3 C2
C1
n1
n2
n3
Signal path
Scan path
(a) Hypergraph of SoC Circuit
with multiple-terminal nets
C3 C2
C1
n11
n2
n3
Signal path
Scan path
n13
n12
(b) Interconnect Test Modeling
Hypernet
Oscillation Ring Test Scheme
Single-Fault AssumptionInterconnect Detection Problem (IORT)
Pass or Fail=>Edge-Covering ProblemGoal: Faults on Test RingsInterconnect Detection Model
Interconnect Diagnosis Problem (IORD)Fault Diagnosis=>Fault Location ProblemGoal: Optimal Resolution to Net SegmentInterconnect Diagnosis Model
Interconnect Detection Model
2-pin nets (N11=n11+n12, N12=n11+n13)
N11 N2
N3
interconnect
scan path C1
C2 C3
N12
Oscillation Ring Test Scheme
Single-Fault AssumptionInterconnect Detection Problem (ORT)
Pass or Fail=>Edge-Covering ProblemGoal: Faults on Test RingsInterconnect Detection Model
Interconnect Diagnosis Problem (ORD)Fault Diagnosis=>Fault Location ProblemGoal: Optimal Resolution to Net SegmentInterconnect Diagnosis Model
Interconnect Diagnosis Model
(a) Hypernet (b) Interconnect Diagnosis Model
Ring 1
Ring 2
Ring 4
e1 e2 e3 e4 e5
e1
e2 e3
e4 e5
(a) (b)
e6 e7
Ring 3
e6 e7
For Diagnosis: Every Edge Influences Different Rings=>Optimal Diagnosis Resolution is Edge
Outline
IntroductionOscillation Ring Test Scheme for Interconnect Detection and Diagnosis Interconnect Diagnosis AlgorithmOptimization Techniques for Interconnect Diagnosis Experimental Results Concluding Remarks
Interconnect Diagnosis Algorithm
Diagosability ConditionsHeuristic Diagnosability Check Number of TestsInterconnect Diagnosis Algorithm
IORT (Interconnect Oscillation Ring Test)IORD (Interconnect Oscillation Ring Diagnosis)
An Interconnect Diagnosis Graph Example to Show Diagosability Conditions
ej
r3 r2 r1 r5
ek
r4
ei r1=r2 =r3=r4 ={ei, ej, ek}
r5 ={ej, ek}
Ri={r1, r2, r3, r4}
Rj= Rk={r1, r2, r3, r4, r5 }
Ei=r1 r2 r3 r4= {ei, ej, ek}
Ej= Ek= r1 r2 r3 r4 r5 = {ej, ek} =>Ei Ej= Ek
An Interconnect Diagnosis Graph Example
ej
r3 r2 r1 r5
ek
r4
ei Ri={r1, r2, r3, r4}
Rj= Rk={r1, r2, r3, r4, r5 }
Ri Rj= Rk
|Ri|=4, distinguishable with |Rj|=|Rk|=5
Ri is distinguishable with Rj and Rk
An Illustrative SoC Circuit for Interconnect Diagnosis
C3 C2
C1
n1
n2
n3
Signal path
Scan path
n4
C3 C2
C1
e1
e2
e3
Signal path
Scan path
e6 e5
e4
(a) Hypergraph (b) Interconnect Diagnosis Model=>Optimal Resolutation is Edge
An Illustrative DiagnosabilityExample
r1
e3
e2
e4
e5
C1
C3
e1
e6
C2
r2 r3
r1={e1, e2, e3, e6}
r2={e1, e3, e5}
r3={e1, e4, e6}
For Test Rings thru e1
=>R1={r1, r2, r3}
|R1|=3
Syndrome=[1,1,1]
Matrices for the Heuristic Diagnosability Checking
e1 r1 r2 r3
1 1 1 1 0 0 1 1 0 0 0 1 1 0 1 0 1 0
e3 e6
(a) (b)
e2 e4 e5 e1
r1 r2 r3
1 1 1 1 0 0 1 1 0 0 0 1 1 0 1 0 1 0
e3 e6 e2 e4 e5
Complexity for check: O(n2m)
Flow Chart of Diagnosability Checking
Edge ei is diagnosable, remove eifrom all rings in Rj with |Rj|=|Ri|
YesYesNoNo
|Ei|=1
Compare ei to all ej with |Rj|=|Ri|
Sort all edges ei according to |Ri|
ej such that Ej =Ei
Pick an edges ei
All edges processed or enough resolution
YesYesNoNo
YesYes
Interconnect Diagnosis Algorithm
Diagosability Conditions Heuristic Diagnosability Check Number of TestsInterconnect Diagnosis Algorithm
IORT (Interconnect Oscillation Ring Test)IORD (Interconnect Oscillation Ring Diagnosis)
Number of Tests
IORT (|Rt|)Lower Bound: 1Upper Bound: n
IORD (|Rd|)Previous Example: n/2 distinct ringsN-bus Example: n-1 ringsRandom Case: |Rd|=|Rt|+additional Diagnosis Rings predetermined rings
Assume:
m equivalence classes, whose sizes are s1, s2, …, sm, respectively.
The upper bound on the number of additional diagnosis rings “ |Rd|–|Rt|” as theoretical results:
Theorem for Upper Bound ofPredetermined Diganosis
EquClassNoDiagmSSm
ii
m
ii ##)1(
11
An Illustrated Example ofPredetermined Diganosis Ring Generation
e1 r1 r2 r3
1 1 1 1 0 0 1 1 1 0 0 1 1 0 0 0 1 0
e3 e6 e2 e4 e5 e1 r1 r2 r3 r4
1 1 1 1 0 0 1 1 1 0 0 1 1 0 0 0 1 0 0 1 0 0 1 0
e3 e6 e2 e4 e5
Add r4 to distinguish between e3 and e6 in Group of |Ri|=2
=> Syndrome of e3 and e6 is different!
Interconnect Diagnosis Algorithm
Interconnect Diagnosability AnalysisHeuristic Diagnosability Check Number of Tests Interconnect Diagnosis Algorithm
IORT (Interconnect Oscillation Ring Test)IORD (Interconnect Oscillation Ring Diagnosis)
Diagnosis Ring Generation Procedure
Generate a
Diagnosis Ring (Rd)
Diagnosability Check
YesYes
NoNo
Diagnosability Check
Test Ring Generation (Rt)
Enough diagnosis resolution?
Outline
IntroductionOscillation Ring Test Scheme for Interconnect Detection and Diagnosis Interconnect Diagnosis AlgorithmOptimization Techniques for Interconnect DiagnosisExperimental Results Concluding Remarks
Optimization Techniques forInterconnect Diagnosis
Concurrent Diagnosis: under Worst Case Scenario
Scan Path ConstraintShared Edge Constraint
Adaptive Diagnosis (Ra)Use almost same test cost with IORT (Rt) only to reduce test time efficiently
Scan Path Constraints
. . .
Core Boundary
p3 p4
e3 e4 e1 e2
p1 p2
Concurrent TestScan path conflict
Shared edge conflict
{e2}
r1
{e5}
{e4}
{e1 }
r3r4
r2
{e2}
{e4}
{e1 }
r4
r1 r2
r3
{e5}
(a) Conflict Graph (b) Graph coloring
Optimization Techniques forInterconnect Diagnosis
Concurrent DiagnosisScan Path ConstraintShared Edge Constraint
Adaptive Diagnosis (Ra)Construct adaptive diagnosis treeDiagnosis cost
Best Case: Balanced adaptive treeWorst Case: Skewed adaptive tree
Adaptive Diagnosis Tree
F r3 {fe1, fe4, fe6}
r1
{ , fe1, fe2, fe3, fe4, fe5, fe6}
F
{ , , fe2, fe3, fe5}
P F
r2 P F {fe1, fe6} {fe4}
{ }
{ , fe5}
{fe3}
r1 P F
P
{fe2, fe3}
{fe1} {fe6}
P
P F
{fe2} {fe5}
r2 r2
e1 r1 r2 r3
1 1 1 1 0 0 1 1 0 0 0 1 1 0 1 0 1 0
e3 e6 e2 e4 e5
Diagnosability Checking Matrix
Upper Bound of Adaptive Diagnosis
|Rt|: the number of test rings for detection (IORT)Lh: the length of the longest test ringBest Case
If the tree is balanced, the minimum number of diagnosis patterns required is
Worst case for Skewed Adaptive Tree, Apply |Rt| rings to find out that there is a faulty net, and The last ring contains Lh net segments that are all passed by the ring only. It takes up to Lh–1 rings to distinguish these Lh possible faults, and thus the maximum number of diagnosis rings is |Rt|+ (Lh–1).
)1log(n
Outline
IntroductionOscillation Ring Test Scheme for Interconnect Detection and Diagnosis Interconnect Diagnosis AlgorithmOptimization Techniques for Interconnect Diagnosis Experimental ResultsConclusion
Experimental Results for Interconnect Diagnosis both for
Predetermined and Adaptive Methods
10.9679Compar.
1.54
222(55.5ms)
5124862143461.57342(85.5ms)
218(54.5ms)
356161
210xerox
1.89
87(21.8ms)
782511451762.02164(41ms)
81(20.3ms)
195724511hp
1.61
76(19ms)
44940941271.67122(30.5ms)
73(18.3ms)
13692739apte
2.38
162(40.5ms)
9230883374062.47386(96.5ms)
156(39ms)
475361
2249ami49
1.23
246(61.5ms)
561591263091.25303(75.8ms)
242(60.5ms)
343117
4233ami33
2.67
140(35ms)
8 241683233892.81374(93.5ms)
133(33.3ms)
416211
7527ac3
|Rd|/
|Ra|
|Ra|max. EC
|Rd|–|Rt|
#Equ
Class
#NoDiag
#OneRing
|Rd|/|Rt|
|Rd||Rt|#net_seg.
#hyp
#pad
#core
AdaptiveAnalysisPredeterminedStatisticsCircuit
Experimental Results –Concurrent Test Sessions
4.57%11.0432Comparison15 (4.59%)327342xerox4 (2.50%)160164hp3 (2.52%)119122apte
34 (9.66%)352386ami4917 (5.86%)290303ami331 (0.27%)373374ac3
|Rd|-|Rc||Rc|(worst case)
|Rd|Circuit
Experimental Results –Comparison between Theoretical Bounds and
Experimental Results•.
6.64%11.0712Comparison4 (3.13%)12412886214xerox
12 (12.77%)829451145hp1 (2.00%)49504094apte
19 (7.63%)23024988337ami496 (8.96%)616759126ami33
14 (5.49%)24125568323ac3
(#NoDiag-#EquClass)
and (|Rd|–|Rt|)
Extra Rings(|Rd|–|Rt|)
(#NoDiag-#EquClass)
#EquClass
#NoDiag
Circuit
Outline
IntroductionOscillation Ring Test Scheme for Interconnect Detection and Diagnosis Interconnect Diagnosis AlgorithmOptimization Techniques for Interconnect Diagnosis Experimental Results Conclusion
Present an Interconnect OR Test scheme for interconnect faults in SOC circuits
IORT scheme achieves 100% fault detection coverage for each net IORD scheme achieves the maximum diagnosability for each net segment
Present fast diagnosability check and diagnosis ring generation
with theoretical study and integrated them into the IORD algorithmwith difference around 6 or 7% between theoretical and experimental results
Conclusion
Two optimization techniques
Concurrent OR Test (Rc)Under worst case scenario: average within 5% and up to 9.66%
Adaptive OR Test (Ra)Improves by 1.23 X to 2.38 X compared with predetermined diagnosis Rd
with difference of predetermined detectionIORT (Rt) by 3.21%
Conclusion (Cont’d)
Thank you for your Kind Participation!
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