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( DOC No. HX8852-A-DS )
HX8852-A LCOS display controller Preliminary version 02 Jan, 2008
-P.1- Himax Confidential
January 2008 This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. Subject to change without notice.
1. General Description
The HX8852-A is a video processor which supports MIPI interface and converts video signal’s frame rate up to 120Hz for LCOS. HX8852-A built in OSD, Scaling engine and video enhancement functions together. It uses just single clock input to generate all the clocks for whole chip by internal PLL and the video enhancement processes includes: CTI, 8-bit Gamma LUT, sRGB and wide-range adjustment for Brightness/Contrast/ Hue/Saturation. HX8852-A’s low-power and simple pin-count can be used for portable/hand-held device.
2. Features
Support ITU-656, ITU-601 and 24-bit RGB input format. Support CPU interface which is compliant to MIPI standard (DBI/DPI/DCS). Support output resolution 640x480@120Hz to drive LCOS panel. Support input resolution from 320x240 ~ 800x480 and frame rate 0Hz ~ 60Hz. Embedded 2D de-interlace & scaling engine. Embedded programmable RGB 8-bit Gamma look-up table. Embedded font-based OSD engine. Embedded B/C/H/S, CTI, sRGB. Built-in two programmable PLL. Support EEPROM interface to initialize registers after power-on 95 pin TFBGA.
SYMBOL PARAMETER Min. TYPICAL MAX UNIT VDDDCORE VDDQ 1.35 1.5 1.65 V VDDIOLCOS VDDIO_LC 2.6 3.3 3.6 V VDDIOMIPI VDDIO 1.6 1.8/2.8 3.3 V
VDDIOSDRAM VDDQ, VDDM 1.7 1.8 1.95 V VDDAPLL VDDQ 1.45 1.5 1.55 V
PTOTAL Analog & Digital power - 150 - mW
HX8852-A LCOS display controller with interface compliant to MIPI Preliminary Version 02
Jan, 2008
-P.2- Himax Confidential
Jan 2008 This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. Subject to change without notice.
HX8852 Video processor for LCOS display
DATA SHEET Preliminary V02
3. Block Diagram
Figure 3.1 HX8852-A block diagram
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Jan 2008 This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. Subject to change without notice.
HX8852 Video processor for LCOS display
DATA SHEET Preliminary V02
4. Pin Assignment
4.1 TFBGA- 95 (6mm x 6mm x 1.3mm)
SDRAM (1.8V)
MIPI (1.8V~3.3V)
LCOS (3.3V)
B_LCOS6
B_LCOS7
VSS_IO_LC
VDD_COREVSS_IOMOD
E0SCLMSVDD_IOD17D19L
B_LCOS3
B_LCOS4
B_LCOS5
VDD_MIO
VSS_CORETESTMODE
1SDA_ROMD16D18D20K
B_LCOS1
B_LCOS2
VSS_MIO
SMODE
SCL_ROMD21D22J
G_LCOS7
B_LCOS0
VDD_IO_LC
VDD_MIOSDAD23VSS_I
OH
G_LCOS4
G_LCOS5
G_LCOS6D9D8D11D12G
G_LCOS3
G_LCOS2
VSS_IO_LCD15D10D14D13F
G_LCOS1
G_LCOS0
R_LCOS7
VDD_IOD3VDD_
COREVSS_COREE
R_LCOS6
R_LCOS5
R_LCOS4
VSSQ_IOPCLKD2D1D0D
R_LCOS3
VDD_IO_LC
R_LCOS2
VDDQ_IO
VDD_MIO
CLK_IND5D4C
R_LCOS1
R_LCOS0
DE_LCOS
VSS_CORE
VSSQ_IO
VDDQ_IO
VDD_CORE
RESX
HSYNC
VSS_IOD6B
INV_LCOS
CLK_LCOS
VSS_IO_LC
VDD_CORE
VSS_MIO
VSS_CORE
VDD_IOCSXVSYN
CDED7A
1110987654321
TFBGA95 Top view
CORE (1.5V)
PLL (1.5V)
Figure 4.1 HX8852-A pin assignment
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Jan 2008 This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. Subject to change without notice.
HX8852 Video processor for LCOS display
DATA SHEET Preliminary V02
5. Pin Description
LCOS interface (2.6~3.3V) (27) PIN LOCATION PIN NAME DIRECTION DESCRIPTION
A10 CLK_LCOS Clock for LCOS panel. A11 INV_LCOS This pin is used to indicate data inverted for
LCOS. B9 DE_LCOS Data valid signal for LCOS.
B10 R_LCOS0 B11 R_LCOS1 C9 R_LCOS2 C11 R_LCOS3 D9 R_LCOS4
D10 R_LCOS5 D11 R_LCOS6 E8 R_LCOS7
Red data of video sent to LCOS.
E10 G_LCOS0 E11 G_LCOS1 F10 G_LCOS2 F11 G_LCOS3 G11 G_LCOS4 G10 G_LCOS5 G8 G_LCOS6 H11 G_LCOS7
Green data of image sent to LCOS.
H10 B_LCOS0 J11 B_LCOS1 J10 B_LCOS2 K11 B_LCOS3 K10 B_LCOS4 K9 B_LCOS5 L11 B_LCOS6 L10 B_LCOS7
OUT
Blue data of image sent to LCOS.
MIPI interface (1.6V ~ 3.3V) (30) PIN LOCATION PIN NAME DIRECTION DESCRIPTION
D5 PCLK_WRX IN PCLK (DPI), R/WX(Type A) or WRX(Type B) B3 HSYNC_D_CX IN HSYNC(DPI) or D/CX(DBI) A3 VSYNC_TE IN/OUT VSYNC(DPI) or TE(DBI) B4 RESX IN Global reset signal. A4 CSX IN Chip select pin for MIPI interface. A2 DE_RDX IN DE(DPI), E(DBI Type A) or RDX(DBI Type B)D1 D0 D2 D1 D3 D2 E4 D3 C1 D4 C2 D5 B1 D6 A1 D7
IN/OUT
D0 ~ D7 of DPI while MODE1/0 = “01” D0 ~ D7 of DBI while MODE1/0 = “10” or “11”
G4 D8 IN D8 ~ D15 of DPI while MODE1/0 = “01”.
-P.5- Himax Confidential
Jan 2008 This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. Subject to change without notice.
HX8852 Video processor for LCOS display
DATA SHEET Preliminary V02 G6 D9 IN F5 D10 IN G2 D11 IN G1 D12 IN F1 D13 IN F3 D14 IN F7 D15 IN
D8 ~ D15 of DBI while MODE1/0= “10” or “11”D8 ~ D15 of ITU-656/ITU-601(MODE1/0 = “00”)
K3 D16 IN L2 D17 IN K2 D18 IN L1 D19 IN K1 D20 IN J2 D21 IN J1 D22 IN H3 D23 IN
No use while MODE1/0 = “10” or “11”. D16~D23 of DPI while MODE1/0 = “01”. D16~D23 of video port input. (MODE1/0 = “00”)
Global control interface (1.6V ~ 3.3V) (10) PIN LOCATION PIN NAME DIRECTION DESCRIPTION
C4 CLK_IN IN Global clock input. (12MHz, 20MHz or 27MHz)
K6 TEST NI Test mode selection pin. See table 6.1 L6 MODE0 IN K5 MODE1 IN
Operation mode selection pins. See table 6.1
L5 SCL IN H5 SDA IN/OUT
These 2 pins can be used as “Type C” of DBI to receive commands and SPI to access registers.
K4 SDA_ROM IN/OUT J4 SCL_ROM OUT
This serial interface is used to access external EEPROM to down load register values.
L4 MS IN Serial mode selection for Master/Slave. VDDIO:Master; VSSIO:Slave
J6 SMODE IN Enable for test scan mode. VDDIO:enable Power of LCOS interface (2.6~3.3V) (5) PIN LOCATION PIN NAME DIRECTION DESCRIPTION
A9, F9, L9 VSSIO_LC IN Ground C10, H9 VDDIO_LC IN LCOS interface power
Power of SDRAM & core circuit (1.8V) (17) PIN LOCATION PIN NAME DIRECTION DESCRIPTION
A7, D7 VSSQ IN Ground A7, J8 VSSM IN Ground B6, C8 VDDQ IN SDRAM CORE & IO power = 1.8V C6, H7 VDDM IN SDRAM CORE & IO power = 1.8V
K8 VDDM_1 IN PLL power = 1.5V A6,B8,E1,K7 VSS_CORE IN Ground A8,B5,E2,L8 VDD_CORE IN Core power = 1.5V
Power of MIPI interface (1.6V ~ 3.3V) (6) PIN LOCATION PIN NAME DIRECTION DESCRIPTION
A5, E6, L3 VDDIO IN MIPI interface power B2, H1, L7 VSSIO IN Ground
-P.6- Himax Confidential
Jan 2008 This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. Subject to change without notice.
HX8852 Video processor for LCOS display
DATA SHEET Preliminary V02
6. Functional Description 6.1 Operating mode:
There are four operation modes of HX8852-A: (1) Video input mode, (2) MIPI (DBI Type A), (3) MIPI (DBI Type B) and (4) MIPI (DBI Type C + DPI), which are selected by MODE1/ MODE0 of HX8852-A’s primary input. All the four modes will generate 640x480@120Hz output to LCOS panel.
CSX TEST MODE1/MODE0 Operation mode 00 Video (w/ SPI) input mode 01 MIPI (Type C + DPI) mode 10 MIPI (Type A) mode X 0
11 MIPI (Type B) mode Table 6.1 Operation mode setting
X: don’t care In video input mode, HX8852-A supports 8-bit ITU-656/601(50/60Hz) input format and 24-bit RGB data valid mode (50/60Hz) input with resolution range from 320x240 up to 800x480. All the registers are accessed by 2-wire SPI interface. In MIPI Type A mode and MIPI Type B mode, HX8852-A supports 16/18/24-bit RGB input color format via 8/9/16-bit DBI bus and supports image resolution from 320x240 up to 800x480 with frame rate from 0Hz ~ 60Hz. (0Hz means write into frame buffer once) All the video stream and commands are compliant to (1) MIPI DCS specification v1a and (2) MIPI DBI specification v2.0. In MIPI DBI Type C + DPI mode, HX8852-A supports 16/18/24-bit RGB color format input via 24-bit DPI bus and supports resolution from 320x240 up to 800x480 with frame rate 50/60Hz. All the commands and video stream through DBI (Type C) are compliant to (1) MIPI DCS specification v1a, (2) MIPI DBI specification v2.0 and (3) MIPI DPI specification v2.0. In MIPI standard, there are four types of “Display architecture”. HX8852-A only supports three of them.
Display architecture Type of display interface
(DBI) Command bus 8━ -bit Type 1 DBI Type A /
Type B Support 16/18/24 bit color format (DBI) Video stream bus 8/9/16 bits━
(DBI) Command bus 2━ -bit Type 2 DBI Type C (2
wires) + DPI Support 16/18/24 bit color format (DPI) Video stream bus 16/18/24 bits━
(DBI) Command bus 2━ -bit Type 3 DBI Type C (2
wires) + DPI Support 16/18/24 bit color format (DPI) Video stream bus 16/18/24 bits━
Type 4 Not supported ━ ━
Table 6.2 MIPI type
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Jan 2008 This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. Subject to change without notice.
HX8852 Video processor for LCOS display
DATA SHEET Preliminary V02
ITU-656/ITU-601 24-bit RGB/DPI DBI Type A DBI Type B DBI Type C
CSX CSX CSX CSX CSX
RESX RESX RESX RESX RESX
VSYNC VSYNC TE(option) TE
HSYNC HSYNC D/CX D/CX
PCLK PCLK R/WX WRX
DE DE E RDX
D15 D15 D15 D15
D14 D14 D14 D14
D13 D13 D13 D13
D12 D12 D12 D12
D11 D11 D11 D11
D10 D10 D10 D10
D9 D9 D9 D9
D8 D8 D8 D8
D7 D7 D7
D6 D6 D6
D5 D5 D5
D4 D4 D4
D3 D3 D3
D2 D2 D2
D1 D1 D1
D0 D0 D0
D23 FIXED_E
D22
D21
D20
D19
D18
D17
D16
SDA SDA SDA
SCL SCL SCL
SDA_ROM SDA_ROM SDA_ROM SDA_ROM SDA_ROM
SCL_ROM SCL_ROM SCL_ROM SCL_ROM SCL_ROM
CLK_IN CLK_IN CLK_IN CLK_IN CLK_IN
TEST TEST TEST TEST TEST
MODE0 MODE0 MODE0 MODE0 MODE0
MIPI / Video Stream
Interface (1.8V/2.8V)
MODE1 MODE1 MODE1 MODE1 MODE1
Table 6.3 The pin usage for MIPI of HX8852-A
-P.8- Himax Confidential
Jan 2008 This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. Subject to change without notice.
HX8852 Video processor for LCOS display
DATA SHEET Preliminary V02 6.2 Video process:
Some video processing blocks which are used to enhance display performance and to calibrate display device’s characteristics are embedded. All the parameters of video processing will be automatically downloaded by EEPROM after power-on reset.
6.2.1 Scaling engine 6.2.1.1 Scaling ratio parameters
Formula: scaling ration = (input resolution/output resolution) x 4096 Example: Input resolution: NTSC 720 x 240 Output resolution: WVGA 800 x 480 x-ratio: ((720 -1)/(800 -1)) x 4096 = 3685 y-ratio: ((240 -1)/(480 -1)) x 4096 = 2043 Write the x-ratio & y-ratio value into registers.
6.2.1.2 PLL setting Formula: clock_out = fref x (M+1)/[(Pa+1)(N+1)] clock_m = fref x (M+1)/[(Pb+1)(N+1)] Example: for 800 x 480 resolution @60Hz Clock_out = 33.3 MHz, clock_m = 29.9 MHz, fref = 12 MHz Clock_out = 12 x (199+1)/[(8+1)(7+1)] = 33.33 MHz Clock_m = 12 x (199+1)/[(9+1)(7+1)] = 30 MHz Write the value into registers which control M, N, Pa & Pb parameters to generate proper frequency for scaling engine.
6.2.2 Image enhancement(B/C/H/S, Sharpness)
6.2.2.1 Brightness/Contrast/Hue/Saturation We use the formula to complete the B/C/H/S:
Yout = Y*contrast + brightness Uout = (U*cos(hue) + V*sin(hue))*sat Vout = (V*cos(hue) – U*sin(hue))*sat
The contrast/brightness/hue/sat are controlled by registers.
6.2.2.2 Sharpness/Blur/CTI 6.2.2.2.1 Sharpness
Figure 6.1 The sharpness block diagram
HPF Coring X +
Delay
gain
Y_in
Y_out
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Jan 2008 This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. Subject to change without notice.
HX8852 Video processor for LCOS display
DATA SHEET Preliminary V02 6.2.2.2.2 Blur
This function is implemented by 5-tap low pass filter. The image will become softer after this low pass filter.
6.2.2.2.3 CTI (Chrominance Transient Improvement) This function can improve the color quality by improving the
Cb and Cr transitions.
6.2.3 OSD Font size: 12x18 pixel Font color: 1~2 bit/pixel (1~3 color/pixel) Font memory: 128 piece SRAM Display window size: 24x8 character Palette: 32 colors Blending: 16 steps Transparency Blinking Scaling (pixel duplication): x1, x2
6.2.4 sRGB matrix
This matrix is used to calibrate the color gamut of panel to fit the original color.
⎥⎥⎥
⎦
⎤
⎢⎢⎢
⎣
⎡+
⎥⎥⎥
⎦
⎤
⎢⎢⎢
⎣
⎡×⎥⎥⎥
⎦
⎤
⎢⎢⎢
⎣
⎡=
⎥⎥⎥
⎦
⎤
⎢⎢⎢
⎣
⎡
11
10
9
876
543
210
'''
CCC
CCCCCCCCC
BGR
BGR
The parameters C0 ~ C11 are set by registers.
6.2.5 Gamma LUT Digital 8-bit gamma table is used to calibrate the characteristic of panel, so that the gray level seen on panel will be linearly proportional to input data. The default table is downloaded by EEPROM after power-on reset and it can be programmed by host processor whenever it needs.
6.2.6 Frame rate convert All the video stream input from host processor will be stored into SDRAM first, and then read out to duplicate frames in order to generate 100 ~ 120Hz frame rate for LCOS panel. The frame rate convert is only to duplicate frames without any interpolation.
6.3 MIPI commands & registers :
HX8852-A implements the CPU interface which is compliant to MIPI standard. In addition, HX8852-A supports three kinds of display architectures which MIPI defines four kinds in standard. Please reference to the following specifications: (1). MIPI Alliance Standard for Display Command Set V1.0 (2). MIPI Alliance Standard for Display Bus Interface v2.0 (3). MIPI Alliance Standard for Display Pixel Interface v2.0 (DPI-2) There are two groups of control for HX8852-A. One is the MIPI standard commands and the other group is the registers of video processing blocks. When MODE1/MODE0 = “00”, all the MIPI commands will be ignored and all the registers can be accessed by
-P.10- Himax Confidential
Jan 2008 This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. Subject to change without notice.
HX8852 Video processor for LCOS display
DATA SHEET Preliminary V02 SPI interface. When MODE1/MODE0≠”00”, all the MIPI commands and registers can be processed or accessed by DBI bus. 6.3.1 Display Command Set
According to HX8852-A’s architecture (MCM with SDRAM), some standard commands are not supported by HX8852-A which is high-light at table.
Commands Enter_idle_mode Enter_invert_mode Enter_normal_mode Enter_partial_mode Enter_sleep_mode Exit_idle_mode Mode control Exit_invert_mode Exit_sleep_mode Get_address_mode Get_blue_channel Get_disgnostic_result Get_display_mode Get_green_channel Get_pixel_format Get_power_mode Get_red_channel Get_scanline Get_signal_mode NOP Read_DDB_continue Read_DDB_start Read_memory_continue Read_memory_start
Actions
REG_WRITE(For Type A/B) REG_READ(For Type A/B) Set_address_mode Set_column_address Set_display_off Set_display_on Set_gamma_curve Set_page_address Set_partial_area Set_pixel_format Set_scroll_area Set_scroll_start Set_tear_off Set_tear_on
Display control
Set_tear_scanline Soft_reset Write Buffers Write_LUT Write_memory_continue Write_memory_start
Table 6.4 MIPI command
HX8852-A display command table Num HEX
code Parameter
Num. Command Parameters Description
1 0x01h 0 Soft reset Software Reset 2 0x06h 1 get_red_channel Get the red component of
the pixel at (0, 0). 3 0x07h 1 get_green_channel Get the green component of the pixel
at (0, 0). 4 0x08h 1 get_blue_channel Get the blue component of
the pixel at (0, 0). 5 0x0Ah 1 get_power_mode Get the current power mode. 6 0x0Bh 1 get_address_mode Get the frame memory to the display
panel read order. 7 0x0Ch 1 get_pixel_format Get the current pixel format. 8 0x0Dh 1 get_display_mode Get the current display mode from
the peripheral. 9 0x0Eh 1 get_signal_mode Get display module
signaling mode. 10 0x0Fh 1 get_diagnostic_result Get Peripheral Self-
Diagnostic Result 11 0x10h 0 enter_sleep_mode Power for the display panel is off. 12 0x11h 0 exit_sleep_mode Power for the display panel is on. 13 0x12h 0 enter_partial_mode Part of the display area is used for
image display 14 0x13h 0 enter_normal_mode The whole display area is used for
image display 15 0x20h 0 exit_invert_mode Displayed image colors are not
inverted. 16 0x21h 0 enter_invert_mode Display image colors are inverted 17 0x26h 1 set_gamma_curve Selects the gamma curve used by
the display device. 18 0x28h 0 set_display_off Blanks the display device. 19 0x29h 0 set_display_on Show the image on the
display device. 20 0x2Ah 4 set_column_address SC[15:0] & EC[15:0]
set image width Set the column extent.
21 0x2Bh 4 set_page_address SP[15:0] & EP[15:0] set image height
Set the read order from frame memory to the display panel.
22 0x2Ch N write_memory_start Transfer image data from the Host Processor to the peripheral starting at the location provided by
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Jan 2008 This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. Subject to change without notice.
HX8852 Video processor for LCOS display
DATA SHEET Preliminary V02 set_column_address and set_page_address.
23 0x2Dh N write_LUT Fills the peripheral look-up table with the provided data.
24 0x2Eh N read_memory_start Transfer image data from the peripheral to the Host Processor interface startingat the location provided byset_column_address and set_page_address.
25 0x30h 4 set_partial_area SR[15:0] & ER[15:0] set partial image height
Defines the partial display area on the display device.
26 0x33h 6 set_scroll_area TFA[15:0]=top fix area VSA[15:0] = scroll_area BFA[15:0]=bottom fix area
Defines the vertical scrolling and fixed area on display device.
27 0x34h 0 set_tear_off Synchronization information is not sent from the display module to the host processor.
28 0x35h 1 set_tear_on Synchronization information is sent from the display module to the host processor at the start of VFP.
29 0x36h 1 set_address_mode bit7:PAGE_ADDR_ORDER, bit6:COLUMU_ADDR_ORDER,bit5:PAGE_COLUMU_ORDER,bit4:LINE_ADDR_ORDER, bit3:RGB_ORDER, bit2:DISPLAY_ORDER
Set the read order from frame memory to the display panel.
30 0x37h 2 set_scroll_start VSP[15:0] start scroll point Defines the vertical scrolling starting point.
31 0x38h 0 exit_idle_mode Full color depth is used on the display panel.
32 0x39h 0 enter_idle_mode Reduce color depth is used on the display
33 0x3Ah 1 set_pixel_format Bits[6:4]: DPI pixel format Bits[2:0]: DBI pixel format Bit7 and bit3 are not used.
Defines how many bits per pixel are used in the interface.
34 0x3Ch N write_memory_continue Transfer image information from the Host Processor interface to the peripheral from the last written location.
35 0x3Eh N read_memory_continue Read image data from the peripheral continuing after the last read_memory_continue or read_memory_start.
36 0x44h 2 set_tear_scanline Synchronization information is sent from the display module to the host processor when the display device refresh reaches the provided scanline.
37 0x45h N get_scanline Get the current scanline. 38 0x4Ch 1 set_tear_scanline_2 PAR_8 2nd command 39 0x4Dh 1 set_column_address_2 PAR_16 and PAR_8 2nd command 40 0x4Eh 1 set_column_address_3 PAR_8 3rd command 41 0x4Fh 1 set_column_address_4 PAR_8 4th command 42 0x50h 1 set_page_address_2 PAR_16 and PAR_8 2nd command 43 0x51h 1 set_page_address_3 PAR_8 3rd command 44 0x52h 1 set_page_address_4 PAR_8 4th command 45 0x53h 1 set_partial_area_2 PAR_16 and PAR_8 2nd command 46 0x54h 1 set_partial_area_3 PAR_8 3rd command 47 0x55h 1 set_partial_area_4 PAR_8 4th command 48 0x56h 1 set_scroll_area_2 PAR_16 and PAR_8 2nd command 49 0x57h 1 set_scroll_area_3 PAR_8 3rd command 50 0x58h 1 set_scroll_area_4 PAR_8 4th command 51 0x59h 1 set_scroll_area_5 PAR_8 5th command 52 0x5Ah 1 set_scroll_area_6 PAR_8 6th command 53 0x5Bh 1 set_scroll_start_2 PAR_8 2nd command 54 0x80h 0 PLL_ON PLL output on 55 0x81h 0 PLL_OFF PLL output off 56 0xA1h N read_DDB_start Read the DDB from the provided
location. 57 0xA8h N read_DDB_continue Continue reading the DDB
from the last read location. 58 0xB0h 0 SET_16_ON Bus connect 16 bit 59 0xB1h 0 SET_8_ON Bus connect 8 bit 60 0xB2h 0 SET_9_ON Bus connect 9 bit
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HX8852 Video processor for LCOS display
DATA SHEET Preliminary V02 61 0xB3h 0 PAR_MIPI Parameter MIPI spec. 62 0xB4h 0 PAR_16 Parameter 16 bit 63 0xB5h 0 PAR_8 Parameter 8 bit 64 0xB8h 0 REGULAR Normal display 65 0xBAh 0 ROTATION Display rotation 66 0xCDh 0 OPTION1 See MIPI spec. 67 0xCEh 0 non_OPTION1 See MIPI spec.
68 0xCFh 0 OPTION3 SPI_CLK_OFF. 69 0xD0h 0 non_OPTION3 SPI_CLK_ON. 70 0xEDh 1 REG_WRITE_2 PAR_8 mode only 71 0xEEh 2 REG_WRITE ADR[7:0] & Data[7:0] 72 0xEFh 2 REG_READ ADR[7:0] & Data[7:0]
6.3.1.1 idle mode/sleep mode/normal mode
Memory Display Panel
Figure 6.2 enter_idle_mode Example
Idle mode off
Enter_idle_mode 0x39
Idle mode on
Figure 6.3 enter_idle_mode Flow Chart
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HX8852 Video processor for LCOS display
DATA SHEET Preliminary V02
Idle mode on
Enter_idle_mode 0x38
Idle mode off
Figure 6.4 exit_idle_mode Flow Chart
Any mode
Enter_sleep_mode 0x12
Sleep Mode
Figure 6.5 enter_sleep_mode Flow Chart
Sleep mode
Exit_sleep_mode 0x11
Sleep Mode off
Figure 6.6 exit_sleep_mode Flow Chart
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HX8852 Video processor for LCOS display
DATA SHEET Preliminary V02 6.3.1.2 invert mode
Memory
Display Panel
Figure 6.7 enter_ivert_mode Example
Memory
Memory
Figure 6.8 exit_ivert_mode Example
Invert mode off
Enter_invert_mode
0x21
Invert mode on
Figure 6.9 enter_ivert_mode Flow Chart
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HX8852 Video processor for LCOS display
DATA SHEET Preliminary V02
Invert mode on
exit_invert_mode 0x20
Invert mode off
Figure 6.10 exit_ivert_mode Flow Chart
6.3.1.3 address mode
Set_address_mode Bit B7- page Address order ‘0’ = Top to Bottom ‘1’ = Bottom to Top
B7 = 0 B7 = 1
Top Left Memory
Sent 1st
Top Left Display Panel
Sent 2nd Sent 3rd
Sent Last
Top Left Memory
Sent 1st
Top Left Display Panel
Sent 2nd Sent 3rd
Sent Last
Figure 6.11 B7 Page Address Order
Bit B6 – Column Address Order ‘0’ = left to right ‘1’ = Right to Left Bit6 = 0 Bit6 = 1
Sen
t 1st
Top Left Display Panel
Sen
t 2nd
S
ent 3
rd
Sen
t Las
t
Sent
1st
Top Left Display Panel
Sent
2nd
Se
nt 3
rd
Sent
Las
t
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Jan 2008 This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. Subject to change without notice.
HX8852 Video processor for LCOS display
DATA SHEET Preliminary V02
Top Left Memory
Top Left Memory
Figure 6.12 B6 Column Address Order
Bit B5 – Page/Column Address Order ‘0’ = Normal Mode ‘1’ = Reverse Mode Bit B4 – Line Address Order ‘0’ = LCD Refresh Top to Bottom ‘1’ = LCD Refresh Bottom to Top Bit B3 – RGB/BGR Order ‘0’ = Pixels Sent in RGB order ‘1’ = Pixels sent in BGR order
B3 = 0 Memory Display panel
R G B = sent RGB R G B
B3 = 1 Memory Display panel
R G B = sent RGB B G R
Figure 6.13 B3 RGB Order
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HX8852 Video processor for LCOS display
DATA SHEET Preliminary V02
Address Mode
Set_address_mode 0x36
New Address
B[7:0]
Figure 6.14 set_address_mode Flow Chart
6.3.1.4 pixel format
set_pixel_format Bits D[6:4] – DPI Pixel Format Definition Bits D[2:0] – DBI Pixel Format Definition Bits D7 and D3 are not used.
Pixel Format D6/D2 D5/D1 D4/D0 Reserved 0 0 0 3 bits/pixel 0 0 1 8 bits/pixel 0 1 0
12 bits/pixel 0 1 1 Reserved 1 0 0
16 bits/pixel 1 0 1 18 bits/pixel 1 1 0 24 bits/pixel 1 1 1
Table 6.5 Interface Pixel Formats
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HX8852 Video processor for LCOS display
DATA SHEET Preliminary V02
n bpp mode
Set_pixel_format 0x3A
Invert mode off
Parameter
Figure 6.15 set_pixel_format Flow Chart
6.3.1.5 partial mode
set_partial_area (if set_address_mode bit7=1)
SR[15:0]
ER[15:0]
Partial Area
Figure 6.16 set_partial_area set_address_mode B7 = 1 Example
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HX8852 Video processor for LCOS display
DATA SHEET Preliminary V02 set_partial_area (if set_address_mode bit7=0)
ER[15:0]
SR[15:0]
Partial Area
Figure 6.17 set_partial_area set_address_mode B7 = 1 Example
Any mode
Set_partial_area0x12
Partial mode on
SR[15:0]
and
Enter_partial_mode
Figure 6.18 enter partial display mode Flow Chart
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HX8852 Video processor for LCOS display
DATA SHEET Preliminary V02 To exit partial mode
Partial Mode On
Set_display_off0x28
Set_display_on
Write_memory
Enter_normal_mode
0x13
Normal Mode On
Image data D1[15:0, D2[15:0….
Dn[15:0]]]
Enter Normal Mode turns Partial Mode off
Optional(To avoid Tearing effect
Figure 6.19 exit partial display mode Flow Chart
6.3.1.6 write memory & define column/page address
Set_column_address This command defines the column extent of the frame memory accessed by the host processor with the read_memory_continue and write_memory_continue commands. No status bits are changed.
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HX8852 Video processor for LCOS display
DATA SHEET Preliminary V02
SC[15:0] EC[15:0]
Figure 6.20 set_column_address Example
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HX8852 Video processor for LCOS display
DATA SHEET Preliminary V02
Set_column_address
0x2A
Write_memory
Set_page_address
0x2B
Image data D1[15:0, D2[15:0….
Dn[15:0]]]
As require
SC[15:0] andEC[15:0]
SC[15:0] andEC[15:0]
Next command
Figure 6.21 set_column_address Flow Chart
Set_page_address This command defines the page extent of the frame memory accessed by the host processor with the write_memory_continue and read_memory_continue command. No status bits are changed.
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HX8852 Video processor for LCOS display
DATA SHEET Preliminary V02
SC[15:0]
EC[15:0]
Figure 6.22 set_page_address Example
Set_column_address
0x2A
Write_memory
Set_page_address
0x2B
Image data D1[15:0, D2[15:0….
Dn[15:0]]]
As require
SC[15:0] andEC[15:0]
SC[15:0] andEC[15:0]
Next command
As require
Figure 6.23 set_page_address Flow Chart
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HX8852 Video processor for LCOS display
DATA SHEET Preliminary V02 write_memory_start This command transfers image data from the host processor to the display module’s frame memory starting at the pixel location specified by preceding set_column_address and set_page_address commands.
Write_memory_start
Next command
Image data D1[15:0],D2[15:0],….. Dn[15:0]
Figure 6.24 write_memory_start Flow Chart
write_memory_continue This command transfers image data from the host processor to the display module’s frame memory continuing from the pixel location following the previous write_memory_continue or write_memory_start command.
Write_memory_continue
Next command
Image data D1[15:0],D2[15:0],…..
Dn[15:0]
Figure 6.25 write_memory_continue Flow Chart
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HX8852 Video processor for LCOS display
DATA SHEET Preliminary V02
6.3.1.7 scrolling function set_scroll_area (if set_address_mode bit4=1) This command defines the display module’s Vertical Scrolling Area. TFA, VSA and BFA refer to the Frame Memory Line Pointer.
(0,0)
TFA[15:0]
VSA[15:0]
TFA[15:0]
First line Read from memory
Top Fixed
Bottom Fixed Area
Figure 6.26 set_scroll_area set_address_mode B4 = 1 Example
set_scroll_area (if set_address_mode bit4=0) TFA, VSA and BFA refer to the Frame Memory Line Pointer.
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HX8852 Video processor for LCOS display
DATA SHEET Preliminary V02
(0,0)
TFA[15:0]
VSA[15:0]
TFA[15:0]
First line Read from memory
Top Fixed
Bottom Fixed Area
Figure 6.27 set_scroll_area set_address_mode B4 = 0 Example
set_scroll_start (if set_address_mode bit4=0) This command sets the start of the vertical scrolling area in the frame memory. The vertical scrolling area is fully defined when this command is used with the set_scroll_area command When Top Fixed Area = Bottom Fixed Area = 0, Vertical Scrolling Area = YY and VSP = 3.
VSP[15:0]
(0,0) Memory
(0,YY-1)
VSP[15:0]
(0,0)
Display Panel
(0,YY-1)
Figure 6.28 set_scroll_start set_address_mode B4 = 0
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HX8852 Video processor for LCOS display
DATA SHEET Preliminary V02
Set_scroll_areas
0x33
Write_memory
Set_column_address
0x2A
Image data D1[15:0, D2[15:0….
Dn[15:0]]]
Redefines the Frame Memory window where the scroll data will be written.
TFA[15:0]
SC[15:0] andEC[15:0]
Next command
Optional: It may be necessary to redefine the Frame Memory Write direction.
Normal Mode
TFA[15:0]
TFA[15:0]
Set_page_address
0x2B
SC[15:0] andEC[15:0]
Set_column_address
0x2A
SC[15:0] andEC[15:0]
SC[15:0] andEC[15:0]
Normal Mode
Only required for non-rolling scrolling.
Figure 6.29 set_scroll_area Flow Chart
6.3.1.8 tearing effect
set_tear_off This command turns off the display module’s Tearing Effect output signal on the TE signal line.
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HX8852 Video processor for LCOS display
DATA SHEET Preliminary V02
TE output on or off
Set_tear_off 0x34
TE output off
Figure 6.30 set_tear_off Flow Chart
set_tear_on This command turns on the display module’s Tearing Effect output signal on the TE signal line. The TE signal is not affected by changing set_address_mode bit B4.
TE output on or off
Set_tear_on 0x35
TE output off
M
Figure 6.31 set_tear_on Flow Chart
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HX8852 Video processor for LCOS display
DATA SHEET Preliminary V02 6.3.1.9 soft_reset
TE output off
Soft_reset
Blank display device
Reset to SW defaults
Figure 6.32 soft_reset Flow Chart
6.3.1.10 Display On/Off
Set_display_off
Memory
Display Panel
Figure 6.33 set_display_off Example
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HX8852 Video processor for LCOS display
DATA SHEET Preliminary V02
Display panel on
Set_display_off0x28
Displsy panel off
Figure 6.34 set_display_off Flow Chart
Set_display_on
Memory
Memory
Figure 6.35 set_display_on Example
Display panel off
Set_display_on0x29
Displsy panel on
Figure 6.36 set_display_on Flow Chart
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HX8852 Video processor for LCOS display
DATA SHEET Preliminary V02 6.3.1.11 Read/Write registers (User defined command)
Any mode
Read/write register
0xEE
Any mode
Address, value
Figure 6.37 read/write register Flow Chart
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HX8852 Video processor for LCOS display
DATA SHEET Preliminary V02
6.3.2 Register map of HX8852-A
Index R/W Name Default Description MAIN 00-01h R/W frc_hsize[10:0] 0xD0-0x02 Input horizontal size 02-03h R/W frc_vsize[9:0] 0xF0-0x00 Input vertical size 04-05h R/W frc_htotal[10:0] 0x5A-0x03 Input horizontal total size 06-07h R/W frc_vtotal[9:0] 0x06-0x01 Input vertical total size 08-09h R/W frc_hsync[9:0] 0x40-0x00 Input horizontal blanking
period 0a-0bh R/W frc_vsync[8:0] 0x04-0x00 Input vertical blanking
period 0c-0dh R/W frc_hstart[9:0] 0x7A-0x00 Input horizontal start pixel 0e-0fh R/W frc_vstart[8:0] 0x16-0x00 Input vertical start line INP_FORM 10h R/W vs_delay,
field_rev, vs_active_set, href_active_set, hs_active_set, port_sel, vga_field
0x5D BIT6: vs_delay 0: no input vs delay 1: 4 cycle input vs delay
BIT 5: field polarity reverse output for scaler 0: not reverse 1: reverse
PS: 0: odd field 1: even field BIT 4: vs_active_set(VGA) 0: use internal vs(setting
inp_vtotal, inp_vstart_o) 1: use external vs
BIT 3: href_active_set (601 and VGA) 0: use internal href(seting
inp_h_start, inp_h_size, inp_v_start_o, inp_v_size) 1: use external href
BIT 2: hs_active_set (601 and VGA) 0: use internal hs(seting
inp_h_total) 1: use external hs
BIT 1: port_sel 0 : ccir domain or RGB
domain from port a 1 : ccir doamin from port b
BIT 0: VGA Field 0: even_field 1: odd_field
11h R/W {if_mode, vsp, hsp} 0x0C BIT 3-2: if_mode 00: YpbPr/DBI 01: VGA
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HX8852 Video processor for LCOS display
DATA SHEET Preliminary V02 10: 601 11: 656 BIT 1: vsync polarity 0: negative 1:positive BIT 0: hsync polarity 0: negative 1: positive
12-13h R/W Inp_hstart 0x7A-0x00 To define input h_start position (href position)
14-15h R/W Inp_vstart_o 0x12-0x00 To define input odd field v_start position or RGB v_start position
16-17h R/W Inp_vstart_e 0x13-0x00 To define input even field v_start position
18h R/W { vs_pos_o , vs_pos_e}
0x00 VS position adjustment output for scaler, only used in ccir 601/656. Vs_pos_o : control odd field VS position Vs_pos_e : control even field VS position
19h R/W { npc_set_en , npc_set}
0x00 BIT1: npc_set_en : 0: NTSC/PAL setting by
npc_set 1: auto �iction
BIT0 : npc_set : 0 : NTSC mode 1 : PAL mode
SC 20-23h R/W ratio_data 0x00-0x00-0x00-0x00 BIT31-28:
0: yratio 1: x_ratio_1 2: x_ratio_2 3: x_ratio_3
4: x_ratio_4 5: x_ratio_5
6: x_ratio_6 7: x_ratio_7
8: x_ratio_8 9: x_ratio_9 10: x_ratio_10
11: x_ratio_11 12: x_ratio_12
13: x_ratio_13 BIT27-16: ratio_size BIT1515-0: ratio_value
24-25h R/W border_data 0x00-0x00 BIT11-10: 00: xborder_1 01: xborder_2
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HX8852 Video processor for LCOS display
DATA SHEET Preliminary V02 10: yborder_1 11: yborder_2 BIT9-0: border_value
26h R/W x_delay 0x03 BIT2-0: delay level for 0-7 27h R/W { reg_coeff_sel,
sc_opt, cs_yuv} 0x01 BIT2: reg_coeff_sel
(default: 0) BIT1: sc_opt 1: scaling down 0: scaling up BIT0: cs_yuv 1: yuv_domain 0: rgb domain
2fh R/W { srgb_en, image_en, reserved bit}
0x00 BIT2: srgb_en 1: srgb block enable 0: srgb block disable BIT1: image_en 1: image processing block
enable(B/C/H/S/sharpness/)
0: image processing block disable BIT0: reserved bit
RGBW 30h R/W { rgbw_en,
reg_ud, reg_lr}
0x03 BIT4: regw_en BIT1: reg_ud BIT0: reg_lr
31h R/W K_fac 0x00 Factor for rgbw IMAGE 41h R/W sharpness[4:0] 0x10 0C~0F: blur mode
10: by_pass mode 11~1f: sharpness mode
42h R/W { y_clip, y_coring}
0xF0 BIT7-4: y_clip = clipping value/16; BIT3-0: y_coring;
43h R/W dcti[3:0] 0x00 BIT3-0: dcti level 44h R/W { dcti_clip,
dcti_coring} 0xF0 BIT7-4: dcti_clip = clipping
value/16; BIT3-0: dcti_coring
45h R/W { possharp_en, negsharp_en, sharp_width, dcti_width}
0x0C BIT3: possharp_en BIT2: negsharp_en BIT1: sharp_width BIT0: dcti_width
46h R/W brightness[7:0] 0x80 Brightness adjustment, offset: -127~127
47h R/W contrast[7:0] 0x80 Contrast adjustment, factor: 0~1.99
48-49h R/W sat_sin_hue[8:0] 0x00-0x00 BIT8: sign bit BIT7-0: sat_sin_hue = saturation *
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HX8852 Video processor for LCOS display
DATA SHEET Preliminary V02 sin(hue) * 128 where saturation: 0~1.99
hue -180 ~ 180 4a-4bh R/W sat_cos_hue[8:0] 0x80-0x00 BIT8: sign bit
BIT7-0: sat_cos_hue = saturation * cos(hue) * 128
GAMMA && sRGB 50h R/W gamma_en 0x00 Gamma function enable 51h W gamma_addr - Gamma LUT address 52-54h W gamma_data - Gamma LUT data 55h-57h W sRGB_data[16:0] - BIT 16-13: coefficient index
for C0, C1, …., C11 BIT12: sign bit For C0-C8 matrix coefficient BIT 11-10: 2-bit integer (power of 2) BIT 9-0: 10-bit fraction For C9-C11 BIT11-10: 2-bit integer BIT9-0: 10-bit fraction
TP 60h R/W test_pat[6:0] 0x00 Test pattern Generator
BIT6-4: Pattern resolution 0: Bypass 1: VGA (640x480) 2: WVGA (800x480) 3: SVGA (800x600) 4: QVGA (320x240) 5: Customer setting
BIT 3-0: Aging pattern 0 :
MODE_GRAY_SCALE_2561 : MODE_COLOR_BAR 2 : MODE_BORDER 3: MODE_R_COLOR 4: MODE_G_COLOR 5: MODE_B_COLOR 6:
MODE_WHITE_COLOR 7 : MODE_CHESS_BOX 8 : MODE_RAMP_GRAY 9 : MODE_RAMP_RED A :
MODE_RAMP_GREEN B : MODE_RAMP_BLUE C : MODE_GRILL_11 D : MODE_GRILL_22 E : MODE_GRILL_44
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HX8852 Video processor for LCOS display
DATA SHEET Preliminary V02 F : MODE_GRILL_88
61h R/W pure_pat[7:0] 0xFF Pure pattern gray level 62-63h R/W hsize_cust[11:0] 0xE0-0x01 Customer’s setting 64-65h R/W vize_cust[10:0] 0xF0-0x00 Customer’s setting 66-67h R/W hbse_cust[11:0] 0x11-0x01 131072/hsize 68-69h R/W vbase_csut[10:0] 0x9A-0x01 98304/vsize DITHER && Output && TCON 70h R/W {rev_en, ditherb_en} 0x01 BIT1: rev_en: Rev enable
( “H’ enable) BIT0: ditherb_en: Dithering enable (“L” enable)
71h R/W dith_framemtx 0x5F BIT7-0: four frame rotation coefficient
72h R/W dith_vmtx_l2b 0x2D BIT7-0: frame rotation coefficient
73h R/W dith_hmtx_l2b_r 0x36 BIT7-0:Line rotation coefficient for R
74h R/W dith_hmtx_l2b_g 0x8D BIT7-0:Line rotation coefficient for G
75h R/W dith_hmtx_l2b_b 0x63 BIT7-0:Line rotation coefficient for B
76h R/W { ch2_rev, ch1_rev, ch0_rev}
0x00 BIT2: ch2 bitwise reverse BIT1: ch1 bitwise reverse BIT0: ch0 bitwise reverse
77h R/W { 1’b0, reg_odd, 1’b0, reg_even}
0x00 BIT6-4: reg_odd (odd line color filter) BIT2-0: reg_even (even line color filter) 0: RGB 1: RBG 2: GBR 3: GRB 4: BGR 5: BRG
SDRAM Controller 7Ah R/W { dram_brsw,
dram_bl, dram_wt, dram_cl};
0x23 BIT7: dram_brsw burst read single write
BIT6-4: SDRAM burst length BIT3:dram_wt address wrap type BIT2-0: SDRAM cas latency
7B-7Ch R/W t_ref 0x18-0x06 SDRAM auto refresh time 7Dh R/W t_wait200us 0x04 BTI3-0: the duration to wait
for clock stable in unit of 4k cycle
7Eh R/W { 2.b00, dram_ds, 1’b0,
0x00 BIT5-4: dram_ds BIT2-0:dram_pasr partial self refresh mode
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HX8852 Video processor for LCOS display
DATA SHEET Preliminary V02 dram_pasr} driver strength
7Fh R/W { t_ras, t_wr, t_mrd}
0x8A BIT7-4: t_ras BIT3-2: t_wr BIT1-0: t_mrd
80h R/W { 1’b0, t_rcd,
1’b0, t_rp}
0x33 BIT6-4: t_rcd BIT2-0: t_rp
81h R/W { 1’b0, t_rfc,
1’b0, t_rc}
0x77 BIT6-4: t_rfc BIT2-0; t_rc
82h R/W { frc_en, req_dram_init, req_dram_lmr, mipi_mode, sd_rdata_sel}
0x11 BIT4: frc_en BIT3:req_dram_init BIT2:req_dram_lmr BIT1:mipi_mode BIT0: sd_rdata_sel
83h R/W { frame_rdcnt, frame_set}
0x08 BIT3-2: frame rdcnt BIT1-0: frame set:
84h R/W frame_size 0x96 The size of one frame, in unit of 4096
85h R/W hcnt_bitwidth 0x01 BIT1-0: the horizontal counting unit for SDRAM 00: the SDRAM horizontal
counting unit is 256. 01: the SDRAM horizontal
counting unit is 512. 10/11: the SDRAM
horizontal counting unit is 1024.
87-86h R/W rot_vtotal 0x07-0x01 Rotated vertical total size 89-88h R/W rot_vsize 0xF0 Rotated vertical valid size 8B-8Aah R/W rot_htotal 0xAA-0x01 Rotated horizontal total size8D-8Ch R/W rot_hsize 0x40-0x01 Rotated horizontal valid size8Eh R/W { tg_freerun,
tg_vs2x, fifo_freerw}
0x07 BIT2: tg_freerun BIT1:tg_vs2x BIT0:fifo_freerw
8Fh R/W { sdr_pwrdown_dqpdn,sdr_pwrdown_auto, sdr_pwrdown_dqlow, sdr_clk_invert, sdr_clkdll_sel,}
0x08 BIT7: sdr_pwrdown_dqpdn BIT6: sdr_pwrdown_auto BIT5: sdr_pwrdown_dqlow BIT4: sdr_clk_invert BIT3-0: sdrclkdll_sel
DISPLAY TIMING 90-91 R/W out_htotal[10:0] 0x00-0x00 Horizontal total period 92-93 R/W out_hsync[9:0] 0x00-0x00 Horizontal blanking period 94-95 R/W out_hstart[9:0] 0x00-0x00 Horizontal valid start pixel 96-97 R/W out_hsize[10:0] 0x00-0x00 Horizontal valid period 98-99 R/W out_vtotal[9:0] 0x00-0x00 Vertical total period 9A-9B R/W out_vsync[8:0] 0x00-0x00 Vertical blanking period
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HX8852 Video processor for LCOS display
DATA SHEET Preliminary V02 9C-9D R/W out_vstart[8:0] 0x00-0x00 Vertical valid start line 9E-9F R/W out_vsize[9:0] 0x00-0x00 Vertical valid period A0-A2 R/W out_reset_odd[22:0] 0xFF-0xFF-0x7F VS lock count in odd field A6
R/W { vs_reset_sel, field_en}
0x00 BIT1: 0: original vs_reset logic 1: new vs_reset logic BIT0: enable for even field vs lock (only used in interlaced video source)
OSD AF R/W osd_control [1:0] 0x00 BIT1: OSD enable
BIT0: Blue/Black Screen B0 R/W osd_size [1:0] 0x00
BIT1: Font size Y 0: 18 1: 36
BIT 0: Font size X 0: 12 1: 24
B1 R/W osd_blinkrate[7:0] 0x22 BIT 7-4: Foreground ON (unit 4 Vsync) BIT 3-0: Background ON (unit 4 Vsync)
B2-B3 R/W osd_xpos[10:0] 0x00-0x00 OSD window x position (left)B4-B5 R/W osd_ypos[10:0] 0x00-0x00 OSD window y position (up)B6 R/W osd_pal_addr[4:0] 0x00-0x00 Pallete index 00h-1Fh B7-B9 R/W osd_pal_data[23:0] 0x00-0x00-0x00 BIT 7-0: pallete indirect red
value BIT 15-8: pallete indirect green value BIT 23-16: pallete indirect blue value Simultaneous write RGB to LUT Auto increment index Subaddr move back to “B7h”
BA R/W osd_font_addr[6:0] 0x00 Font index 0-127 BC W osd_font_data[7:0] - Auto increment
Subaddr move back to “BCh”
BDh R/W osd_clear_wr 0x00 BIT 0: display RAM clear BE R/W osd_disp_addr[7:0] 0x00 BIT7-0: display area index
(0~191) C0h W ATTR0[5:0] - BIT5: background
transparency enable BIT4-0: background color index
C1h W ATTR1[6:0] - BIT6: blinking flag BIT5: foreground
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HX8852 Video processor for LCOS display
DATA SHEET Preliminary V02 transparency enable BIT 4-0: foreground color index
C2h W ATTR2[6:0] - Font_addr[6:0] C3h R/W osd_type[7:0] 0x00 BIT 7-4: background alpha
BIT 3-0: foreground alpha C4h R/W font_num[6:0] 0x00 BIT 6-0: number of
1-bit/pixel font Output PLL D0h R/W pll_selpa_s 0x00 P divider A for scaler D1h R/W pll_selpb_s 0x00 P divider B for scaler D2h R/W pll_seln_s 0x00 N divider for scaler D4-D3h R/W pll_selm_s 0x00-0x00 M divider for scaler D5 R/W pll_selp_m 0x00 P divider for SDRAM D6 R/W pll_seln_m 0x00 N divider for SDRAM D8-D7 R/W pll_selm_m 0x00-0x00 M divider for SDRAM DF R/W {2’b00,
pll_rstn_s,1’b0, 2’b00, pll_rstn_m, 1’b0,
0x22 BIT5: reset for SC PLL(low reset) PLL(high power down) BIT1:reset for SDRAM PLL (low reset)
SPI Master Mode E1h-E0h R/W rom_start_addr 0x00-0x00 ROM starting address E3h-E2h R/W rom_reading_length 0x00-0x00 ROM reading length E4h R/W rom_loading 0x00 To load EEPROM
(not in power on state) E5h R rom_state 0x00 The state of EEPROM
1: Busy state 0: Idle state
System FAh R/W System control 0x80 BIT4: sys_en
High enalbe BIT3: sleep_mode High sleep_mode BIT2: clkm_test BIT1: clko_test BIT0: clkmem_test
FDh R/W outmux control 0x00 BIT1: clk_out_inv BIT0: reg_pllout
FEh R/W { reg_refclks, reg_refclkm reg_spiclk}
0x00 BIT5-4: reference clock for PLL_scaler(clk_m, clk_o) BIT3-2 reference clock for PLL_SDRAM(clk_4x) BIT1-0: the SPI clock(refclk 12M) 00: 12M 01: 6M 10: 3M 11: 1.5M
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HX8852 Video processor for LCOS display
DATA SHEET Preliminary V02 Two Wire Serial Bus Interface
The serial control port (SDA, SCL) is designed for 3.3V logic. If driven by 5V supplies, the SDA and SCL should be protected using 150-Ohms series resistors.
Bit 7 A6(MSB)
Bit6 A5
Bit5 A4
Bit4 A3
Bit3 A2
Bit2 A1
Bit1 A0
1 1 1 1 0 1 0 1 1 1 1 0 1 1
Table 6.6 Serial port address
The two wire serial bus interface is used to allow an external micro-controller to write control data to, and read control or other information from the HX8852-A registers. SCL is the serial clock and SDA is the data line. Both lines are pulled high by resistors connected to VDD. ICs communicate on the bus by pulling SCL and SDA low through open drain outputs. In normal operation the master generates all clock pulses, but control of the SDA line alternates back and forth between the master and the slave. For both read and write, each byte is transferred MSB first, and the data bit is valid whenever SCL is high. The HX8852-A is operated as a bus slave device. The most significant 6-bits are fixed. The 7-bit address field is concatenated with the read/write control bit to form the first byte during a new transfer. If the read/write control bit is high the next byte will be read from the slave device. If it is low the next byte will be a write to the slave. When a bus master drives SDA from high to low, while SCL is high, this is defined to be a start condition. After a start condition, the host then sends a byte consisting of the 7-bit slave device ID and the R/W bit. After this, the master must release the SDA line while holding SCL low, and wait for an acknowledgement from the slave.
Figure 6.38 2-Wire Protocol Data Transfer
To write the internal register of the HX8852-A, the master sends another 8-bit of data, the HX8852-A loads this to the register pointed by the internal index register. The HX8852-A will acknowledge the 8-bit data transfer and automatically increment the index in preparation for the next data. The master can do multiple writes to the HX8852-A if they are in ascending sequential order. After each 8-bit transfer the HX8852-A will acknowledge the receipt of the 8-bit with an acknowledge pulse. To end all transfers to the HX8852-A the host will issue a stop condition.
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HX8852 Video processor for LCOS display
DATA SHEET Preliminary V02 Figure 6.39 2-wire write operation
A HX8852-A read cycle has two phases. The first phase is a write to the internal index register. The second phase is the read from the data register. The host initiates the first phase by sending the start condition. It then sends the slave device ID together with a 0 in the R/W bit. The index is then sent followed by a stop condition. The second phase starts with the second start condition. The master then resends the same slave device ID with a 1 in the R/W bit to indicate a read. The slave will transfer the contents of the desired register. After transferring eight bits, the slave releases and the master takes control of the SDA line and acknowledges the receipt of data to the slave. To terminate the last transfer the master will issue a negative acknowledge and issue a stop condition.
Figure 6.40 2-wire read operation
6.3.3 Power saving mode of MIPI The following table explains the status of functional blocks during normal mode and power saving modes.
MIPI Command FRC/SDRAM Video processor LCOS I/F Normal mode OK OK OK OK
Idle mode OK OK Partial bits Partial bits Sleep mode OK Clock STOP/
Power-down Clock STOP Clock STOP
Table 6.6 Power saving mode of MIPI
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HX8852 Video processor for LCOS display
DATA SHEET Preliminary V02
7. System Block Application The application option 1 Video input port━
The application option 2 MIPI Type A interface━
HX8852-A
EEPROM (REG setting,
OSD font)
SPI
8-bit ITU-656/601 or 24-bit RGB
CLK_IN
24-bit RGB
DE CLK INV
VS/HS/DE/PCLK
Support 50Hz or 60Hz (320x240 ~ 640x480)
VGA @ 120Hz
MODE1/MODE0 = “00”
LCOS
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HX8852 Video processor for LCOS display
DATA SHEET Preliminary V02
The application option 3 MIPI Type B interface━
The application option 4 MIPI Type C━ interface
HX8852-A
8-bit/16-bit Bus
CSX,RESX,D/CX, WRX,RDX
EEPROM (REG setting,
OSD font)
CLK_IN
Support 0Hz ~ 30Hz. Support 16/18/24 bit RGB format
(320x240 ~ 800x480)
MODE1/MODE0 = “11”
24-bit RGB
DE CLK
INV
VGA @ 120Hz
LCOS
HX8852-A
8-bit/16-bit Bus
CSX,RESX,D/CX, R/WX,E
EEPROM (REG setting,
OSD font)
CLK_IN
Support 0Hz ~ 30Hz. Support 16/18/24 bit RGB format
(320x240 ~ 800x480)
MODE1/MODE0 = “10”
24-bit RGB
DE CLK
INV
VGA @ 120Hz
LCOS
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HX8852 Video processor for LCOS display
DATA SHEET Preliminary V02
8 DC Characteristics Absolute maximum ratings
Spec. Parameter Symbol Min. Typ. Max.
Unit
Power supply VDDDCORE -0.3 2.0 V Power supply VDDIOLCOS -0.3 4.0 V Power supply VDDIOMIPI -0.3 4.0 V Power supply VDDSDRAM -0.3 2.0 V Power supply VDDAPLL -0.3 2.0 V
Storage temperature TSTG -40 95 ºC
Recommended operating conditions
Spec. Parameter Symbol Min. Typ. Max.
Unit
Power supply VDDDCORE 1.35 1.5 1.65 V Power supply VDDIOLCOS 2.6 3.3 3.6 V Power supply VDDIOMIPI 1.6 1.8/2.8 3.6 V Power supply VDDSDRAM 1.7 1.8 1.95 V Power supply VDDAPLL 1.45 1.5 1.55 V
Operating temperature TOPR -30 +85 ºC
HX8852-A
16/18/24-bit RGB
CSX,RESX,SCL, SDA
EEPROM (REG setting,
OSD font)
CLK_IN
VS/HS/DE/PCLK
Support 50Hz / 60Hz. (320 ~ 640x480)
DDPPII
MODE1/MODE0 = “01”
24-bit RGB
DE CLK INV
VGA @ 120Hz
LCOS
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HX8852 Video processor for LCOS display
DATA SHEET Preliminary V02
Electrical Characteristics
Parameter Symbol Condition Min. Typ. Max. Unit
Input low current IIL No pull-up or
pull-down -1 - 1 μA
Input high current IIH No pull-up or pull-down -1 - 1 μA
Tri-state leakage current IOZ - -10 - 10 μA
Input capacitance CIN - - 3 - pF Output capacitance COUT - 3 - 6 pF Logic input low voltage VIL
(1) CMOS - - 0.3VIO V
Logic input high voltage VIH
(1) CMOS 0.7VIO - - V
Output low voltage VOL IOL=4mA - - 0.2VIO V Output high voltage VOH IOH=-4mA 0.8VIO - - V Input pull up/down resistance RI
VIL= 0V or VIH= VIO - 40 - kΩ
9 AC Characteristics 9.1 Video input mode
ITU-R BT.601 8-bit or ITU-R BT.656 8-bit PARAMETER Symbol Min. Typ. Max. Unit
CLK period tC 35 37 39 ns CLK Duty tCW 40 50 60 %
NTSC 60.1 63.5 66.9 µs NTSC - 1716 - tC PAL 60.5 64 67.4 µs HREF period tH
PAL - 1728 - tC NTSC 50.4 53.3 56.1 µs NTSC - 1440 - tC PAL 50.4 53.3 56.1 µs HREF pulse width tHD
PAL - 1440 - tC NTSC 15.8 16.6 17.5 ms NTSC - 262.5 - tH PAL 18.9 20 21 ms V123 period tV
PAL - 312.5 - tH V123 pulse width tVP 1.3 1.5 1.7 tH Data setup time tDS 10 - - ns Data hold time tDH 10 - - ns
Figure 6.41 AC timing of video input signal
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HX8852 Video processor for LCOS display
DATA SHEET Preliminary V02
ITU-R BT. 601 NTSC input timing
524 525 1 2 3 4 5 6 23
BLANKING DATADATA
22
V123
HREF
261 262 263 264 265 266 267 268 286
BLANKING
285
V123
HREF
1st Field
276 clock 1440 clockCLKIN
DATA
HREF
2nd Field
CB718 Y718 CR
718 Y719CB0 Y0 CR0 Y1Y719
Figure 6.42 NTSC input timing
ITU-R BT. 601 PAL input timing
622 623 624 625 1 2 3 4 23
BLANKING DATADATA
22
V123
HREF
309 310 311 312 313 314 315 316 336
BLANKING
335
V123
HREF
1st Field
288 clock 1440 clockCLKIN
DATA
HREF
2nd Field
CB718 Y718 CR
718 Y719CB0 Y0 CR0 Y1Y719
Figure 6.42 PAL input timing
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HX8852 Video processor for LCOS display
DATA SHEET Preliminary V02
9.2 DBI interface 9.2.1 AC Characteristic Type A interface━
Fixed E mode
Figure 8.1 AC Characteristics, Type A Interface, Fixed E Mode
Clock E mode
Figure 8.2 AC Characteristics, Type A Interface, Clocked E Mode
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HX8852 Video processor for LCOS display
DATA SHEET Preliminary V02 Signal Symbol Parameter min max Unit Description
tas Address setup time T ns R/WX or D/CX tah
Address hold time (read/write) T ns
CSX or E tcycle
System clock cycle time 5xT 79xT ns
tDS Data setup time 15 ns tDH Data hold time 25 ns tACC Data access time 10 ns
D[15:0], D[8:0], or D[7:0] tOH Output hold time 10 ns
For maximum CL = 30PF For minimum CL = 8PF
Table 8.1 AC Characteristic -- Type A Interface Note: 1. Ta = -30 to 70℃, VDDI range: according to Logic High level input voltage
classification , GND = 0V, T = 10±0.5 ns 2. Does not include signal rise and fall times.
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HX8852 Video processor for LCOS display
DATA SHEET Preliminary V02 9.2.1 AC Characteristic Type B interface━
Figure 8.3 AC Characteristics, Type B Interface
Signal Symbol Parameter min max Unit Description
tast Address setup time T - ns D/CX taht Address hold time (read/write) T - ns tcs Chip select setup time 2xT - ns trcs Chip select hold time 2xT - ns CSX tcsf Chip select wait time (read/write) 20 - ns twc Write cycle 5xT 79xT ns twrh Write control pulse H duration 3xT 63xT ns WRX twrl Write control pulse L duration 2xT 16xT ns trc Read cycle 5xT 79xT ns trdh Read control pulse H duration 3xT 63xT ns RDX trdl Read control pulse L duration 2xT 16xT ns twds Write data setup time 15 - ns twdh Write data hold time 25 - ns tracc Read access time 10 - ns
D[15:0], D[8:0], or D[7:0] trod Read out disable time 10 - ns
For maximum CL = 30PFFor minimum CL = 8PF
Table 8.2 AC Characteristics -- Type B Interface Note: 1. Ta = -30 to 70 , VDDI range: according to Logic High level input voltage classification, GND = 0V, T = ℃10± 0.5 ns 2. Does not include signal rise and fall times.
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HX8852 Video processor for LCOS display
DATA SHEET Preliminary V02
9.2.2 AC Characteristic Type C interface━
Figure 8.4 AC Characteristics, Type C Interface
Signal Symbol Parameter min max Unit Description
tcss Chip Select setup time(Write)
4xT - ns CSX
tcsh Chip Select setup time (Read)
4xT - ns
tas Address setup time T - ns D/CX
(optional)
tah Address hold time(Write/Read)
T - ns
twc Write cycle 10xT - ns twrh SCL H duration (write) 4xT - ns
SCL(write)
twrl SCL L duration (write) 4xT - ns trc Read cycle 15xT - ns trdh SCL H duration (read) 6xT - ns
SCL(read)
trdl SCL L duration (read) 6xT - ns tds Data setup time 3xT - ns DOUT or
SDA(write) tdh Data hold time 3xT - ns tacc Access time 10 ns DIN or
SDA(read) tod Output disable time T 5xT ns
For maximum CL=30pF For minimum CL=8pF
Table 8.3 AC Characteristics -- Type C Interface Note:
1. Ta = -30 to 70℃, VDDI range: according to Logic High level input voltage classification, GND = 0V, T = 10±0.5 ns
2. Does not include signal rise and fall times
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HX8852 Video processor for LCOS display
DATA SHEET Preliminary V02 9.3 AC Characteristic DPI━ -2
Figure 8.5 DPI Signal Timings
Parameters Symbol Condition min max Unit
Vsync Setup Time VSST T ns Vsync Hold Time VSHT T ns Hsync Setup Time HSST T ns Hsync Hold Time HSHT T ns Pixel Clock Duty Cycle PCLKCYC 33 67 % Pixel Clock Low Duration PCLKLT T ns Pixel Clock High Duration
PCLKHT T ns
Data Setup Time DST T ns Data Hold Time DHT T ns
Table 8.4 DPI-2 AC Characteristics
Total Number of pixels Representative display T Unit Up to 38720 pixels 176 x 220 40 ns Up to 76800 pixels 240 x 320 20 ns Up to 307200 pixels 640 x 480 10 ns Up to 384000 pixels 800 x 480 5 ns
Table 8.5 DPI-2 AC Characteristics, T-value
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HX8852 Video processor for LCOS display
DATA SHEET Preliminary V02 9.4 AC Characteristic Serial ━EEPROM interface
Table 6.6 AC timing of serial EEPROM interface
AC waveform
Figure 6.43 AC waveform of serial EEPROM interface
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HX8852 Video processor for LCOS display
DATA SHEET Preliminary V02 9.5 Input signal characteristics
9.5.1 8-bit video stream interface of DBI Type A/B 9.5.1.1 16-bit/pixel(R 5-bit, G 6-bit, B 5-bit), 65,536 Colors
Figure 8.6 16-bits/pixel (R 5-bit, G 6-bit, B 5-bit), 65,536 Colors 9.5.1.2 18-bit/pixel(R 6-bit, G 6-bit, B 6-bit), 262,144 Colors
Figure 8.7 18-bits/pixel (R 6-bit, G 6-bit, B 6-bit), 262,144 Colors
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HX8852 Video processor for LCOS display
DATA SHEET Preliminary V02 9.5.1.3 24-bit/pixel(R 8-bit, G 8-bit, B 8-bit), 16,777,216 Colors
Figure 8.8 24-bits/pixel (R 8-bit, G 8-bit, B 8-bit), 16,777,216 Colors
9.5.2 9-bit video stream interface of DBI Type A/B 9.5.2.1 18-bit/pixel(R 6-bit, G 6-bit, B 6-bit), 262,144 Colors
Figure 8.9 18-bits/pixel (R 6-bit, G 6-bit, B 6-bit), 262,144 Colors
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HX8852 Video processor for LCOS display
DATA SHEET Preliminary V02
9.5.3 16-bit video stream interface of DBI Type A/B 9.5.3.1 16-bit/pixel(R 5-bit, G 6-bit, B 5-bit), 65,536 Colors
Figure 8.10 16-bits/pixel (R 5-bit, G 6-bit, B 5-bit), 65,536 Colors
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HX8852 Video processor for LCOS display
DATA SHEET Preliminary V02 9.5.3.2 18-bit/pixel (R 6-bit, G 6-bit, B 6-bit), 262,144 Colors option 1━
Figure 8.11 18-bits/pixel (R 6-bit, G 6-bit, B 6-bit), 262,144 Colors
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HX8852 Video processor for LCOS display
DATA SHEET Preliminary V02 9.5.3.3 18-bit/pixel (R 6-bit, G 6-bit, B 6-bit), 262,144 Colors option 2━
Figure 8.12 18-bits/pixel (R 6-bit, G 6-bit, B 6-bit), 262,144 Colors
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HX8852 Video processor for LCOS display
DATA SHEET Preliminary V02 9.5.3.4 24-bit/pixel (R 8-bit, G 8-bit, B 8-bit), 16,777,216 Colors option 1━
Figure 8.13 24-bits/pixel (R 8-bit, G 8-bit, B 8-bit), 16,777,216 Colors
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HX8852 Video processor for LCOS display
DATA SHEET Preliminary V02 9.5.3.5 24-bit/pixel (R 8-bit, G 8-bit, B 8-bit), 16,777,216 Colors option 2━
Figure 8.14 24-bits/pixel (R 8-bit, G 8-bit, B 8-bit), 16,777,216 Colors
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HX8852 Video processor for LCOS display
DATA SHEET Preliminary V02
10 Package information
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HX8852 Video processor for LCOS display
DATA SHEET Preliminary V02
11. Revision History
Version EFF.DATE DESCRIPTION OF CHANGES 0.1 2007/07/23 New setup 0.2 2008/01/01 New setup
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