hpps 2008 - mattasoglio

POLITECNICO DI MILANO

Evolvable HW Evolvable HW Analysis of the Gray AreaAnalysis of the Gray Area

Literature analysis and Random Number Literature analysis and Random Number GeneratorGenerator

Dario Mattasoglio Dario Mattasoglio – dario.mattasoglio@dresd.org

Prof. Donatella Sciuto

RationaleRationaleEvolvable Hardware (EHW):

“Hardware realized on reconfigurabledevice, whose structure is modified

Using Evolutionary algorithm”

Project goal:Analyze the recent literature in order to propose a novel classification for EHW to avoid ambiguities of the present oneHardware implementation of one of the core unit of any EHW architecture: a Random Number Generator

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OutlineOutlineClassical notationState of the artGray areaProposed TaxonomyRandom number generator: an implementationConclusion

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Classical notationClassical notationEvolution level

Gate LevelFunctional Level

Solution evaluationSimulating-> Extrinsic EvaluationImplementing -> Intrinsic EvaluationMixed approach -> Mixtrinsic Evaluation

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Classical notationClassical notationEvolution unit placement

On a different device, simulated by software -> PC drivenOn the same device -> Hardware driven

Evolution processBefore implementation -> OfflineDuring the use-> online

Presence of constrains5

State of the artState of the artExtrinsic Offline Pc Driven[5][7][11]

Functional level evolution:Virtual Reconfigurable Circuits VRC[1][2][3]

Intrinsic evaluation has less performance:Data exchange[2]Porting algorithm on PPC[1][8][10]

Novel hardware solutionPOEtic[12]RISA[9]

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VRC Structure

Gray areaGray areaIntrinsic solution Hardware driven

Different implementationPPC[1][8][10]Hardware[2][3]

Same class different purposeFinding new design[2][3]Maintaining the state of the system -> homeostasis[6][11]

Some implementations permit the evolution of the connections[4][7]

Not clearly distinguishable from other solutions e.g., VRC

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The proposed classificationThe proposed classificationDistinguish at which level a classification will be applied

Higher, model levelImplementation level -> most interesting

Purpose of evolutionDesign evolution( [1][2][3][8][10])Adaptive evolution ([6][11])

At implementation level: 4 different classesPure hardware ([2][3][9][12])Pseudo hardware ([1][8][10])Dual device approach ([4])Pure simulation ([5][7][11])

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Case study: Case study:

9An EHW architecture ([2])

Random Number GeneratorRandom Number GeneratorVHDL implementation of the core

A Shifting register based architectureA polynomial function feeds the register

At each clock cycle a new random byte is extracted from the register

POSSIBLE ISSUE: correlation between bit in the subsequent byte

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ConclusionConclusionProposed a novel classificationDesign a fundamental unitFuture work:

Propose a novel architecture for EHW

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End….End….Questions?

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BibliographyBibliography1. An evolvable hardware system in Xilinx Virtex II Pro FPGA,

Zdenek Vašícek and Lukáš Sekanina2. Digital Circuit Design using Intrinsic Evolvable Hardware,

Yang Zhang, Stephen L. Smith, Andy M. Tyrrell3. An Evolvable Hardware Chip for Illumination Enhancement

in Computer Vision for Surface Roughness Estimation, M. Rajaram Narayanan , S.Gowri , A.Velayutham, S. Ravi

4. An evolved circuit, intrinsic in silicon, entwined with physics, A. Thompson

5. Particle Swarm Optimization with Discrete Recombination: An Online Optimizer for Evolvable Hardware, Jorge Pena

6. Evolvable Hardware, a Fundamental Technology for Homeostasis, Andy M. Tyrrell, Jon Timmis, Andrew J. Greensted and Nick D. Owens

7. A Novel Hardware Architecture for Self-adaptive Systems, José Antonio Casas, Juan Manuel Moreno, Jordi Madrenas, Joan Cabestany

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BibliographyBibliography8. Evolvable Reconfigurable Hardware Framework for Edge

Detection, Nader I. Rafla9. Extrinsic Evolvable Hardware on the RISA Architecture, A.

J. Greensted and A. M. Tyrrell10. A Flexible On-Chip Evolution System Implemented on a

Xilinx Virtex-II Pro Device, Kyrre Glette and Jim Torresen11. INTEGRATING THE ELECTRONICS OF THE CONTROL-LOOPS

OF THE JPL/BOEING GYROSCOPE WITHIN AN EVOLVABLE HARDWARE ARCHITECTURE, Evangelos F. Stefatos, Tughrul Arslan Didier Keymeulen, Ian Ferguson

12. POEtic Tissue: An Integrated Architecture for Bio-inspired Hardware, Andy M Tyrrell, Eduardo Sanchez, Dario Floreano, Gianluca Tempesti,Daniel Mange, Juan-Manuel Moreno, Jay Rosenberg, and Alessandro EP Villa

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