hardware accelerated software defined radio

1

Hardware Accelerated Software

Defined RadioTarik Kazaz (tarik.kazaz@intec.ugent.be)07/09/2015

Overview

Common SDR approach

Propposed approach

Hardware accelerated SDR

Use case example

Common SDR approach

Intensive signal processing is done in host PC No real time processing

Significant power and space consumption (no portability)

FPGA is seriously underutilized!

USRP

Host PC

?

Common SDR approach

Coding &Interleaving

QAM mapping

Pilot Insertion

& S/PIFFT

P/S & add CP

Pulse shaping

DAC & RF

Transmitter

Common SDR approach

Coding &Interleaving

QAM mapping

Pilot Insertion

& S/PIFFT

P/S & add CP

Pulse shaping

Baseband processing

DAC & RF

Common SDR approach

Coding &Interleaving

QAM mapping

Pilot Insertion

& S/PIFFT

P/S & add CP

Pulse shaping

Baseband processing

DAC & RF

Common SDR approach

Coding &Interleaving

QAM mapping

Pilot Insertion

& S/PIFFT

P/S & add CP

Pulse shaping

Baseband processing

DAC & RF

Common SDR approach

Coding &Interleaving

QAM mapping

Pilot Insertion

& S/P

P/S & add CP

Baseband processing

DAC & RF

IFFTPulse

shaping

Common SDR approach

Coding &Interleaving

QAM mapping

Pilot Insertion

& S/P

P/S & add CP

Baseband processing

DAC & RF

IFFTPulse

shaping

Common SDR approach

Coding &Interleaving

QAM mapping

Pilot Insertion

& S/P

P/S & add CP

Baseband processing

DAC & RF

IFFTPulse

shaping

Common SDR approach

Coding &Interleaving

QAM mapping

Pilot Insertion

& S/P

P/S & add CP

Baseband processing

DAC & RF

IFFTPulse

shaping

?

Proposed approach

Coding &Interleaving

QAM mapping

Pilot Insertion

& S/P

P/S & add CP

DAC & RF

IFFTPulse

shaping

Hardware accelerated SDR platform on top of Zynq

Xilinx Zynq

Dual Core ARM Cortex A9

GNU Radio

FPGA Accelerated

Block

Linux Kernel Device Driver

ARM to FPGA Interface

FPGA Accelerator

FPGA Fabric

ARM

TFlow

GnuRadio with HW acceleration capabilities

GReasy

ARM - FPGA

shared memory

separate control and data plane interfaces

Hardware accelerated SDR platform on top of Zynq

This concept enables

Offload of GnuRadio blocks to FPGA

Frees up processor to perform other tasks

Hardware accelerated SDR platform on top of Zynq

This concept enables

Offload of GnuRadio blocks to FPGA

Real time reconfigurability

Frees up processor to perform other tasks

Configuration

Port or ICAP

Configuration

Port Full

Bit File

Partial

Bit Files

Fu

nctio

n A

1

Fu

nctio

n B

1

Fu

nctio

n C

1F

un

ction

C2

Fu

nctio

n B

2

Fu

nctio

n A

2F

un

ction

A3

Hardware accelerated SDR platform on top of Zynq

This concept enables

Offload of GnuRadio blocks to FPGA

Whole SDR system should fit on one board

Real time reconfigurability

Frees processor to perform other tasks

Example Scenario

Different applications –different wireless standards

Our platform should support various existing and futureemerging wireless technologies at same time

IoT-CUBE HUB IoT-CUBE HUB

InternetRepository

of SDR

library and

HW ACC

802.11g

device 802.11ac

device

802.15.4

device

BLE

device

802.11ah

xyz

device

Download SDR packages from cloud Wireless as a Service

First step

Locally reconfiguring FPGA part of platform

Changing 802.15.4 Tx with 802.11g Tx

Bitstream for 802.11g is stored locally on SD memory card

Sniffing simultaneously 802.11g and 802.15.4 packets to detect reconfiguration

IoT-CUBE HUB

SD memory

card

802.11g

device

802.15.4

device

Questions?

1929/11/2016