ghdl, what’s new

GHDL, What’s new ?Tristan Gingold

Agenda

What is GHDL ?

Improvements since FOSDEM’15

Multi language simulation - Proof of concept

What is GHDL ?

What is GHDL ?

If you have missed last year presentation:

Free, open-source VHDL simulator

Generate object code (with gcc, LLVM or it’s generator)

Support VHDL 1987 till 2008

github.com/tgingold/ghdl

What is GHDL ?

Command line tool (no IDE)

Generate VCD, GHW or FST waveforms

GTKwave compatible

VHPI and VPI support

Partial support of PSL

Typical use cases

FOSS activist: use a free tool

Nightly testing

Coverage (with gcov)

What’s new ?

What’s new ?

Switch to git

Move to github

Docs on ghdl.readthedocs.org

Continuous integration on travis-ci.org

GHDL 0.33 released

For Linux x86, x86-64

generic, debian and Ubuntu

For Mac OS X

For Windows

First version with good VHDL 2008 support

New featuresMore VHDL 2008 features

Many bugs fixed

Support of VUnit

OSS unit testing framework

Support of OSVVM

Open Source VHDL Verification Methodology

Post release featuresMcode for x86-64:

Mcode is builtin code generator

Code generation is much faster than llvm or gcc

Scale very well

Easy to build (no dependencies)

Was i386 + fpu only

Now i386 or x86-64 + SSE2

Post release features

Optimizations

Better handling of signals

Explicit process state

Future work

More optimisations

Multi language simulation

Synthesis ?

Multi language simulation

VHDL + SystemC

Purpose: simulate both VHDL and SystemC

Using GHDL

Why SystemC ?And not Verilog ?

SystemC is simpler

Simulation cycle is like VHDL

Use the same compilation model as GHDL

Object files

Final link

Proof of Concept

TestBench (SC)

Counter (SC)

TestBench (SC)

Counter (VHDL)

Unmodified

Standard

VHDL

Proof of concept: constraints

Main is SystemC

No change in test bench or VHDL code

No change in SystemC kernel

Proof of concept: simplifications

Only one VHDL module

Multi-language semantic weakly defined

Can change GHDL code

Proof of Concept

Proof of Concept: Adapter

TestBench (SC)

Adapter

Counter (VHDL)

Adapter

Initialize GHDL simulator

Instantiate the VHDL blocks

Convert values between SystemC and VHDL

GHDL initialization

VHDL instantiation

C representation of the VHDL entity, as compiled by GHDL

Pseudo process for Inputs

Value Conversions: input

Ask SystemC to run GHDL kernel

So if an input change, it is propagated to VHDL

Kernel interleaving

Need a new delta cycle

So VHDL kernel is run in case of event

Value Conversions: Output

So if a VHDL signal change, a method is called

Value Conversions: Output

Convert from a VHDL signal to a SystemC signal

Proof of concept: Conclusions

Just of Proof of Concept but:

It works!

required only changes in GHDL runtime (kernel)

need to split the simulation loop

Proof of concept: Future

Generate the adapter automatically

Mapping is not obvious

Avoid delta-cycles between SC and VHDL

Need to modify SystemC kernel

Multiple VHDL instances

Instantiation of SC by VHDL blocks