embedded processing portfolio for ultrasound
Post on 16-Oct-2021
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Embedded Processing Portfolio for Ultrasound
High performance, programmable platform
Processor performancespeeds image analysis –faster, clearer results
Power/size efficientprocessors enable portability – point of care imaging
Programmable DSPs enable software upgrades –extend product life
Complete line of Code compatible devices –provides scalable platform to address portable through high-end cart-based systems
TI Confidential – NDA Restrictions
TI DSP SolutionsTI DSP Enables
TI’s Medical Imaging ProcessorsMission: to enable performance imaging every doctor demands
C66x™
C64x™
Integra™
Advances in medical processing
Latest algorithmsImproved image quality
More accurate diagnosis
Emerging Features
Innovative applicationssafer, non-invasive
Real-time diagnosis
Product differentiation
• Longer battery life
• Smaller form factor
Complete product line of high performance DSPs
Software programmable Flexible
Adaptable
Upgradeable
Real-time performance 1.25GHz single core
320GMACs/160GFlops multi-core
Medical driven roadmap
Portable medical applications
Low power processors and SOCs
• Highly integrated• Power efficient• C64x+ & C66x core DSP• OS, GUI, MMI, display• High connectivity
3
Sitara™
C6-Integra™
Davinci™
Ultrasound system – Where DSP fits
DSPRF Demodulation
B-Mode
Color Flow
Spectral Doppler
Scan Control
SOC (DSP+MPU)Scan Conversion
Speckle Reduction
System Control
O/S
Display
Storage
Multi-core DSP
Console Ultrasound Solution
5
• FPGA beam forms and routes data to DSP via SRIO
• C6657 (2-core) for scan control & back end image processing algorithms.
• PC performs system control, MMI, interface to PACs
• Lower power & system cost solution
C6657 (~3.5w)
SPI
DDR
3
64-bit1.33GHz
DDR3
control
data
66x (x2)1GHzL1P: 32 KBL1D: 32KBL2: 512KB
Multicore Navigator
DAC
McB
SP
SR
IOx
4Probe
MSMC
Shared L2: 4MB
HL 50
MMIPACs i/fMode SwitchCineloop Mgmt
.
System Ctrl
lanesBeam-former
1 to 4
PCIe
AFE
DetectionCompression Velocity Est
Power EstScan Conv
FFTPeak/Mean Est
B-Mode Color Doppler
Scan Conv
Wall FilterRF Demod
.
Decimation
Speckle Red
PC
Multi-core DSP
Portable Ultrasound Solution
6
• FPGA beam forms and routes data to DSP via SRIO
• C6657 (2-core) implements mid-back end image processing algorithms
• AM3874 performs system control, MMI, interface to PACs
• C6657 + AM3874 = ~4w total
C6657 (~3.5w)
SPI
DDR3
64-bit1.33GHz
DDR3
control
data
DDR 2/3
DISPLAY
Storage
PACs
AM 3874 (~1w)ARM®
Cortex™-A8800 MHz L1P: 32KBL1D: 32KBL2 : 256KB
SATA
DSS
GEm
ac
PCIe
32-bit333/666 MHz
66x (x2)1GHzL1P: 32 KBL1D: 32KBL2: 512KB
DDR
LCD
Multicore Navigator
Graphics Engine
Image Engine
USB
Printer
DAC
McB
SP
GPMC
Flash
Switch FabricSR
IOx
4
16-bit 200 MHz
Probe
MSMC
Shared L2: 4MB
HL 50
MMIPACs i/fMode SwitchCineloop Mgmt
.
System Ctrl
lanesBeam-former
1 to 4
PCIe
AFE
DetectionCompression Velocity Est
Power EstScan Conv
FFTPeak/Mean Est
B-Mode Color Doppler
Scan Conv
Wall FilterRF Demod
.
Decimation
Linux
.
O/S
AndroidQT
Speckle Red
DM814x
TI Confidential – NDA Restrictions
SOC Based
Ultra-Portable Ultrasound Solution
7
DAC
control
data
DDR 2/3
DISPLAY
Storage
PACs
DM8148
ARM®
Cortex™-A81GHz L1P: 32KBL1D: 32KBL2 : 256KB
SATA
DSS
GEm
ac
PCIe
32-bit333/666 MHz
674x+750MHz L1P: 32KBL1D: 32KBL2 : 256KB
DD
R
LCD
Graphics Engine
Image Engine
USB
Printer
McA
SP
GPMC
Flash
Switch Fabric
16-bit 200 MHz
Probe
O/S MMIPACs i/fMode SwitchCineloop Mgmt
Speckle RedScan Conv
Velocity EstPower Est
.
Scan Conv
FFTPeak/Mean Est.
B-Mode Color DopplerFront End
BeamformingDetectionCompounding
System Ctrl
Wall Filter
FPGA
Beam-former
RF Demod
AFE
• FPGA beam-former + RF demod and routes data to SOC via PCIe
• ARM Cortex A8 performs system control, MMI, interface to PACs
• DSP performs back end image processing
• Video & Graphics h/w accelerator
AM387x
TI Confidential – NDA Restrictions
Multi-core DSP Based Performance Ultrasound Solution
8
• FPGA beam forms and routes data to DSP via SRIO
• C6678 standard mid processing + 3D/4D, Elastography, & Speckle Reduction
• AM3874 performs system control, MMI, interface to PACs
control
data
Flash
64-bit1.33GHz
DDR3
DDR 2/3
DISPLAY
Storage
PACs
ARM®
Cortex™-A8800 MHz L1P: 32KBL1D: 32KBL2 : 256KB
SATA
DSS
GEm
ac
PCIe
32-bit333/666 MHz
DD
R
LCD
Graphics Engine
Image Engine
USB
Printer
DAC
GPMC
Switch Fabric
16-bit 200 MHz
Probe
MMIPACs i/fMode SwitchCineloop Mgmt
.
System Ctrl
lanesBeam-former
1 to 4
AFE
DetectionCompression Velocity Est
Power EstScan Conv
FFTPeak/Mean Est
B-Mode Color Doppler
Scan Conv
Wall FilterRF Demod
.
Linux
.
O/S
AndroidQT
C66x
SPI
DD
R3
66x (x8)1GHzL1P: 32 KBL1D: 32KBL2: 512KB
Multicore Navigator
SR
IOx
4
MSMC
Shared L2: 4MB
HL 50 PCIe x2
Mc BSP
3D/4DElastographySpeckle Red
AM 3874 DM814x
9TI Confidential – NDA Restrictions 9
TI Confidential – NDA Restrictions
C6655/ C6657 (Sample Now!)
New C66x Core
– 2 C66x Cores @ 1.0GHz nominal (1.4GHz max)
– C6657 (2 Core), C6655 (1 core)
– High Performance Fixed & Floating Point DSP Cores
Power Optimized Design
– Target 3.5W for 2 Core, 2.5W for 1 Core implementation (85c case @ 1Ghz)
Keystone Multi-Core Architecture
– Multicore Navigator, TeraNet, Hyperlink
Memory Architecture
– 1MB Local L2 per Core
– 1MB Multicore Shared Memory (MSM)
– Boot ROM,DDR3-1600MHz (32-bit)
– Address Translation & ECC
Interfaces
– 4x RapidIO rev 2.1 (1x4, 2x2, 1x2+2x1)
– 2 lanes PCIe Gen II
– 10/100/1000 Mbps Ethernet SGMII ports
– Universal Parallel Port (16-bit) Muxed with EMIF -16
– I2C, SPI, 2x McBSP (Mux), 32 GPIO, 2 x UART, 4x Timers64, Semaphore
Other
– 2x VCP2, 1x TCP3d
– Multicore debugging (embedded trace per core / chip)
– 0.8 mm pitch flip chip package
– 21x21 package
– Ext Temp Range: -55C to 105C
– 40nm High Performance Node
– Smart reflex
Multicore Navigator
Te
raN
et
C66X
DSP
L1 L2
SRIO
x4
PCIe
x2
EMIF
16
I2C
SPIUART
Peripherals & IO
SGMII
2x VCP2
TCP3d
Communications
CoProcessors
Power Management
Debug
Multicore Shared Memory Controller
(MSMC)
Shared Memory 1MB
DDR3-
32b
EDMA
SysMon
System Elements
Memory Subsystem
Hyp
erL
ink
C66X
DSP
L1 L2
McBSP
uPP
Shannon (TMS320C6678) – Block Diagram
10
Multicore Navigator
Te
raN
et
C66x
DSP
L1 L2
C66x
DSP
L1 L2
C66x
DSP
L1 L2
C66x
DSP
L1 L2
C66x
DSP
L1 L2
C66x
DSP
L1 L2
C66x
DSP
L1 L2
C66x
DSP
L1 L2
8 x CorePac
SRIO
x4
PCIe
x2
EMIF
16
TSIP
2x
I2C
SPIUART
Peripherals & IO
GbE
Switch
SGMIISGMII
IP Interfaces
Crypto
Packet
Accelerator
Network
CoProcessors
Power Management
Debug
Multicore Shared Memory Controller
(MSMC)
Shared Memory 4MB
DDR3-
64b
EDMA
SysMon
System Elements
Memory Subsystem
• Multi-Core KeyStone SoC
• Fixed/Floating CorePac• 8 CorePac @ 1.25 GHz
• 4.0 MB Shared L2
• 320G MAC, 160GFLOP, 60G DFLOPS
• ~10W
• Navigator• Queue Manager, Packet DMA
• Multicore Shared Memory
Controller• Low latency, high bandwidth memory access
• 3-port GigE Switch (Layer 2)
• PCIe gen-2, 2-lanes
• SRIO gen-2, 4-lanes
• HyperLink• 50G Baud Expansion Port
• Transparent to Software
Hyper
Link
50
Switched Central Resource (SCR)
Peripherals
Memory Interfaces
DM8148
USB
2.0
x2
GPIOGMAC
Switch
PCIe McASP
x6
SPDIF
McBSP
I2C/
SPI
x4
UART
x6DCAN
x2
DDR3
x2
SDIO
/SD
x3
Async
EMIF/
NAND
SATA2
Display
On-Screen Display
Resizer
SD DAC (x2)
HDMI PHY
HD Video I/O (x2)
Video I/O
HD Video
Coprocessor
(x1)
3D Graphics
Engine
ARM micro-
processor
Fixed/Floating
point DSP
ARM
Cortex
A8 TM
C674x
DSP
Core
DM8148 ProcessorCores ARM Cortex A8™ (MPU) up to 1 GHz C674x™ Floating Point DSP Core up to 750 MHz
Memory ARM: 32KB L1I-Cache, 32KB L1 D-Cache, 256K L2 DSP: 32KB L1I-Cache, 32KB L1 D-Cache, 256K L2 Two DDR-800 Controllers
Coprocessors/Subsystem HD VICP 2.0 Accelerator at 320 MHz
– Real-Time HD Encode /Decode 3D Graphics engine Display Subsystem
Peripherals Gigabit EMAC Switch USB 2.0 Ctlr/PHY x 2 PCIe 2.0
SATA 3.0Gbps DDR3 – 800 x2 SD/SDIO x3 McASP x6, McBSP SPI, GPIO, I2C, UART, DCAN
Power Total Power – Typical <4 W
Package 23x23, 0.8mm pitch, 684 ball BGA
• Via Channels enable low cost design rules -- 4 mil traces and 10/20 mil escape vias
Back to: DM roadmap | product positioning
Using DSPs & SOCs in Ultrasound Systems
• TI’s C6678 DSP with new C66x floating point core provides high
performance signal processing capabilities at low power
– C6657 dual core DSP can perform processing for mid-range system
– Upgrade to 4 or 8 core C6674/C6678 for more advanced algorithms
• C66x DSPs are well suited for processing such as:
– B-Mode (Detection, Compression)
– Color (Wall Filter, Velocity & Power estimation)
– Doppler (FFT, Peak Mean estimation)
– Scan Conversion
– 3D/4D, Elasto-graphy, Speckle Reduction
• Combining an FPGA for beam formation/routing and Sitara ARM SOC
C66x DSPs can provide a flexible, low-power solution for digital
ultrasound systems.
– High Level Language “Eclipse” development environment
– On-Chip DMA & Multicore Navigator for data movement.
– McBSP ports address I/O needs for CW Doppler & audio
Using DSPs & SOCs in Portable Ultrasound Systems
• TI’s low-power Davinci SoCs allow flexibility on the back-end SoC for
various display options, image filtering and target identification on a
single chip:
– C674x DSP (fixed-/floating-point DSPs)
– Cortex-A8 for peripheral and communications control
– 3D graphics engine for rich UIs
– Rich display sub-system for multiple HD displays
– HD video encode/decode accelerators (Davinci devices only)
• High system connectivity with peripherals such as:
– Gigabit ethernet
– PCIe
– USB
– SATA
– SPI/GPIOs/more…
LINUX
Scalable BSP/SDKReleases
ARM® MPU
ARM® MPU + DSP
ARM® MPU + DSP+ Video Accelerator Engine
DAVINCI™
C6-INTEGRA™
SITARA™
FREE Development license to use our Linux, Android, or WinCE Board FREESupport Packages (BSP) / Software Development Kits (SDK)
* For use on our ARM, ARM+DSP, and ARM+DSP+Multimedia Processors* Each release seamlessly and scalable works across all products
Complete DSP & ARM MPU Software Solutions by TI
Periph Libraries and Stacks
Multimedia Codecs
Middleware/Frameworks
Common IDE/Tools
Example SW & Demos
“Instant Expert” SW Development Kits
Medical Software Toolkit 2.0
Optimized implementations of commonly used C64x+/C66x DSP processing blocks
Source Code:
Ultrasound:
• B-mode (Envelop Detection & Compression)
• DAS Receive Beam-forming
• Doppler Processing
• RF Demodulation and Decimation
• Scan Conversion
Optical Coherence Tomography
• Cubic Spline Interpolation
• Optimized FFT
3D Rendering
• Affine Warp
Request download at: http://focus.ti.com/docs/toolsw/folders/print/s2meddus.html
TI OMAP3530 Mistral EVM
Medical Ultrasound Demo (MIDAS) Rev. 2All B-Mode, Color Flow, and Scan Conversion Processing on OMAP3530!
Display 640x480 @20fps
B-mode Estimation
Color Flow
Tissue Flow
& Blending
Scan
Conversion
Scan
ConversionFlow
Estimation
Wall
Filter
Ensemble
Aggregation
CompressionEnvelope
Detection
C64x+ DSP 430MHz
ARM Cortex A-8600MHz
DDR
• Runs Linux O/S
• User Interface , Control, Display
• Runs Ultrasound Algorithms
Input Data Size (Post RF Demod) Scan
Lines
Samples/
Scan Line
Bytes/
Sample
Ensemble kB/
frame
B-mode + Scan Conversion 128 416 4 - 208
Color Flow + Scan Conversion 64 256 4 8 512
Loading DSP ARM ms/fm
B-Mode 19% 6% 15
B-Mode+
Color Flow46% 21% 28
https://gstreamer.ti.com/gf/project/med_ultrasound/
TI Confidential – NDA Restrictions
Medical Imaging DSP Value Proposition
C64x+™
Sitara™
C66x™
New & innovative algorithms in softwareImproved image quality & emerging features
Field upgrades, Flexibility, Adaptive coding
Deterministic signal processing architectureSupports latest real-time O/S for predictable & reliable performance
Portable imaging applicationsLow power SOC’s replace PC. (DSP+ARM, Graphics, Video accl…)
Longer battery life. Smaller form factor.
Scalable platforms: PortableValuePremiumCode compatible family of products
R&D SavingsReuse (code, hardware, development environment)
No hardware spins, eco’s, & timing closure bottlenecks
Time to MarketState of the art development tools: (Compilers, trace, emulation)
Develop & debug in high level language
Imaglib & Medical Software toolkit, 3d parties
Roadmap & Product continuityLong term supplier, Full product line: Analog, DSP, Power, etc…
10GHz-320GMACs/160GFlop DSP’s today,
Application support (Field, Factory, domain white papers & app notes)
17
C6-Integra™
Davinci™
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