ee 330 lecture 32 - iowa state university
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EE 330
Lecture 32
• High Gain Amplifiers
• Current Source Biasing
• Current Sources and Mirrors
• The Cascode Configuration
• The Differential Amplifier
Can use these equations only when small signal circuit is EXACTLY like that shown !!
Review from Last Lecture
B
E
C
VDD
Vin
RC
Vout
RE
VEE
B
E
C
VSS
VDD
Vin
RE
Vout
B
E
C
VDD
Vin
RC
Vout
VEE
B
E
C
VBB
VDD
Vin
RC
Vout
CE/CS
CC/CD
CB/CG
CEwRE/
CSwRS
Basic Amplifier Characteristics Summary
• Reasonably accurate but somewhat small gain (resistor ratio)
• High input impedance
• Moderate output impedance
• Used when more accurate gain is required
• Large noninverting gain
• Low input impedance
• Moderate (or high) output impedance
• Used more as current amplifier or, in conjunction with CD/CS to form
two-stage cascode
• Gain very close to +1 (little less)
• High input impedance for BJT (high for MOS)
• Low output impedance
• Widely used as a buffer
Review from Last Lecture
• Large inverting gain
• Moderate input impedance
• Moderate (or high) output impedance
• Widely used as the basic high gain inverting amplifier
Example:
VIN
Q1
VDD
VEE
VOUT
Q1
R1
RS R2
R4
R3 R5R6
R7
R8
C1 C3
C2
C4
Q1
RS
R1//R2
R7
R6//R8
R3//R5
Q2
Vin
Vout
VBVA
out out B AV V2 V1 V0
in B A in
A = A A A V V V V
V V V V
Will calculate AV by determining the three ratios (not voltage gains of dependent source):
Review from Last Lecture
Example:
Q1
RS
R1//R2
R7
R6//R8
R3//R5
Q2
Vin
VoutVBVA
CE with RE
out 6 8V2
B 7
R //RA =
R
V
V
Rin2
in2 7R βR
Review from Last Lecture
Example:
R7
R6//R8
Q2
Vout
One-Port
Rin2
in2 7R βR
Rin2
Review from Last Lecture
Example:
Q1
RS
R1//R2
R7
R6//R8
R3//R5
Q2
Vin
VoutVBVA
CE with RE
out 6 8V2
B 7
R //RA =
R
V
V
Rin2
in2 7R βR
Rin2
Review from Last Lecture
Example:
Rin2
Q1
RS
R1//R2R3//R5Vin
VBVA
Q1
RS
R1//R2 R3//R5//Rin2Vin
VBVA
CE Config B
V1 m1 3 5 in2 A
A = g R //R //R V
V
in1 1R r
Rin1
Review from Last Lecture
Example:
Q1
R3//R5//Rin2
VB
Rin1
Rin1
Review from Last Lecture
Example:
Q1
RS
R1//R2 R3//R5//Rin2Vin
VBVA
Rin1
A 1 2 in1V0
in S 1 2 in1
R //R / /RA =
R R //R / /R
V
V
Review from Last Lecture
Example:
A 1 2 in1
in S 1 2 in1
R //R / /R
R R //R / /R
V
V
Q1
VEE
RS
R1//R2
R7
R6//R8
R3//R5
Q2
Vin
Vout
VAVB
out out B AV
in B A in
A = V V V V
V V V V
Bm1 3 5 in2
A
g R //R //R V
V
in1 1R r
out 6 8
B 7
R //R
R
V
V
in2 7R βR
Thus we have
where
Review from Last Lecture
Example:
Q1
VEE
RS
R1//R2
R7
R6//R8
R3//R5
Q2
Vin
Vout
VAVB
Observation: By working from the output back to the input we were able to
create a sequence of steps where the circuit at each step looked EXACTLY
like one of the four basic amplifiers even though stages were not unilateral.
Engineers often follow a design approach that uses a cascade of the basic
amplifiers and that is why it is often possible to follow this approach to analysis.
gmVBEVBE
iB
gπg0 gmVBEVBE
iB
gπg0 gmVBEVBE
iB
gπg0
RB2 RB3 RL
RB1
Vin
VOUT
Stage 1 Stage 2 Stage 3
Will formalize what we have done (consider 3-stage unilateral cascade)
Exactly same approach when not unilateral
Formalization of cascade circuit analysis working
from load to input: (consider 3-stage unilateral cascade)
OUT 3 OUT 1 2
IN IN 1 2 3
V V VV V
V V V V V
gmVBEVBE
iB
gπg0 gmVBEVBE
iB
gπg0 gmVBEVBE
iB
gπg0
RB2 RB3 RL
RB1
Vin
VOUT
Stage 1 Stage 2 Stage 3V2V1 V3
gmVBEVBE
iB
gπg0 gmVBEVBE
iB
gπg0 gmVBEVBE
iB
gπg0
RB2 RB3 RL
RB1
Vin
VOUT
Stage 1 Stage 2 Stage 3V3V2V1
Formalization of cascade circuit analysis working
from load to input: (consider 3-stage unilateral cascade)
gmVBEVBE
iB
gπg0 gmVBEVBE
iB
gπg0 gmVBEVBE
iB
gπg0
RB2 RB3 RL
RB1
Vin
VOUT
Stage 1 Stage 2 Stage 3V3V2V1
gmVBEVBE
iB
gπg0
RL
Stage 3 VOUTV3
OUT 3 1 2
IN IN 1 2
OUT
3
V VV V
V V V V
V
V
Starting at output stage obtain:
Formalization of cascade circuit analysis working
from load to input: (consider 3-stage unilateral cascade)
gmVBEVBE
iB
gπg0 gmVBEVBE
iB
gπg0 gmVBEVBE
iB
gπg0
RB2 RB3 RL
RB1
Vin
VOUT
Stage 1 Stage 2 Stage 3V3V2V1
gmVBEVBE
iB
gπg0 gmVBEVBE
iB
gπg0
RB2 RB3
RB1
Vin
Stage 1 Stage 2Stage 3
V3V2V1
RIN3
gmVBEVBE
iB
gπg0
RB3
Stage 2 V3V2
RIN3
OUT OUT 1 2
IN IN 1 3
3
2
V VV V
V V V V
V
V
Replace Stage 3 with RIN3
Analyze Stage 2:
Formalization of cascade circuit analysis working
from load to input: (consider 3-stage unilateral cascade)
gmVBEVBE
iB
gπg0 gmVBEVBE
iB
gπg0 gmVBEVBE
iB
gπg0
RB2 RB3 RL
RB1
Vin
VOUT
Stage 1 Stage 2 Stage 3V3V2V1
Replace Stage 2 with RIN2
Analyze Stage 1:
gmVBEVBE
iB
gπg0
RB2
RB1
Vin
Stage 1 V2V1
RIN2
gmVBEVBE
iB
gπg0
RB2
Stage 1 V2V1
RIN2
OUT 3 OUT 1
IN IN 2 3
2
1
V V VV
V V V V
V
V
Formalization of cascade circuit analysis working
from load to input: (consider 3-stage unilateral cascade)
gmVBEVBE
iB
gπg0 gmVBEVBE
iB
gπg0 gmVBEVBE
iB
gπg0
RB2 RB3 RL
RB1
Vin
VOUT
Stage 1 Stage 2 Stage 3V3V2V1
Replace Stage 1 with RIN1
Analyze Stage 0:
RB1
Vin
V1
RIN1
OUT 3 OUT 2
IN 1 2 3
1
IN
V V VV
V V V V
V
V
Example:
Q1
VEE
RS
R1//R2
R7
R6//R8
R3//R5
Q2
Vin
Vout
VAVB
Two other methods could have been used to analyze this circuit
What are they?
Observation: By working from the output back to the input we were able to
create a sequence of steps where the circuit at each step looked EXACTLY
like one of the four basic amplifiers. Engineers often follow a design approach
that uses a cascade of the basic amplifiers and that is why it is often possible
to follow this approach to analysis.
Example:
Q1
VEE
RS
R1//R2
R7
R6//R8
R3//R5
Q2
Vin
Vout
VAVB
Two other methods could have been used to analyze this circuit
1. Create a two-port model of the two stages
(for this example, since the first-stage is unilateral, it can be shown that )
out iX1 L1 iX2 LV V01 V02
in iX1 S L1 iX2 0X1 L 0X2
R R //R RA A A
R +R R //R +R R +R
V
V
AV01 and AV02 are open-loop two-port gain and are different than what used above
Example:
Q1
VEE
RS
R1//R2
R7
R6//R8
R3//R5
Q2
Vin
Vout
VAVB
Two other methods could have been used to analyze this circuit
2. Put in small-signal model for Q1 and Q2 and solve resultant
circuit
(not too difficult for this specific example )
Example: outV
in
A = ?V
V
M1
M2
Q3
M4
I1Vin
Vout
RL
-VSS
VDD
RDRB1
RB2
RC
C1 C2
Express in terms of small-signal parameters
Example:
M1
M2
Q3
M4
I1Vin
Vout
RL
-VSS
VDD
RDRB1
RB2
RC
C1 C2V2V1
11 out 2 1 m1
V m4 D L
2 1 in m2 3 B1 B2
-gA = -g R / /R
g + β R / /R
V V V
V V V
Note: Even though the second stage has a resistor in the collector, the
gain expressions developed for the common collector amplifier still apply
High-gain BJT amplifierm
V m C0 C
-gA -g R
g G
B
E
C
VDD
Vin
RC
Vout
VEE
To make the gain large, it appears that all one needs
to do is make RC large !
CQ CV m C
t
-I RA -g R
V
But Vt is fixed at approx 25mV and for good signal
swing, ICQRC<(VDD-VEE)/2
DD EEV
t
V VA
2V
If VDD-VEE=5V,
100V5V
A2 25mV
• Gain is practically limited with this supply voltage to around 100
• And in extreme case, limited to 200 with this supply voltage with
very small signal swing
High-gain MOS amplifierm
V m D0 D
-gA -g R
g G
G
S
D
VDD
Vin
RD
Vout
VSS
To make the gain large, it appears that all one needs
to do is make RD large !
DQ DV m D
EB
-2I RA -g R
V
But VEB is practically limited to around 100mV and
for good signal swing, IDQRD<(VDD-VSS)/2
DD SSV
EB
V VA
V
If VDD -VSS=5V and VEB=100mV,
50V5V
A100mV
Gain is practically limited with this supply voltage to around 50
Are these fundamental limits on the gain of the BJT and MOS Amplifiers?
High-gain amplifier
VIN
VOUT
Q1
VDD
VEE
IB
VIN
VOUT
Q1
mV
-gA
0
gmVBEVBE
iB
gπVIN
VOUT
This gain is very large !
Too good to be true !
Need better model of MOS device!
High-gain amplifier
VIN
VOUT
Q1
VDD
VEE
IB
VIN
VOUT
Q1
mV
0
-gA
g
gmVBEVBE
iB
gπg0VIN
VOUT
CQ AFV
t CQ AF t
-I VA -
V I /V V
8000AFV
t
V 200VA -
V 25mV
This gain is very large (but realistic) !
But how can we make a current source?
And no design parameters affect the gain
High-gain amplifier
VIN
VOUT
Q1
VDD
VEE
IB
8000VA
How can we build the ideal current source?
What is the small-signal model of an actual current source?
Before addressing the issue of how a current source is
designed, will consider another circuit that uses current source
biasing
The Basic Differential Amplifier
V2
AV(V2-V1)
V1
VOUT
If AV is large
Operational Amplifier (Op Amp)
Example: Determine the voltage gain of the
following circuit
gm1VBE1VBE1
iB1
gπ1 gm2VBE2 VBE2
iB2
gπ2
RC1 RC1Vin
Vout
VE
Q1
Vin
-VEE
RC1
Q2
RC1
VDD
IEE
VOUT
AE1=AE2
Vout
Q1
Vin
RC1
Q2
RC1
AE1=AE2
VE
1 22
m mg g EE
t
I
V=
EEC1 C2
II = I
2=
Since symmetric when VIN=0
Example: Determine the voltage gain of the
following circuit
gm1VBE1VBE1
iB1
gπ1 gm2VBE2 VBE2
iB2
gπ2
RC1 RC1Vin
Vout
VE
1 1OUT C m IN ER g V V V
1 1 1 1 2E IN m IN E m Eg g g g g V V V V V 1 2 1 2 1 1E m m IN mg g g g g g V V
1 1
1 2 1 2
m
E IN
m m
g g
g g g g
V V
1 1
1 1
1 2 1 2
1m
OUT C m IN
m m
g gR g
g g g g
V V
1 2 1 2 1 1
1 1
1 2 1 2
m m m
OUT C m IN
m m
g g g g g gR g
g g g g
V V
Example: Determine the voltage gain of the
following circuit
gm1VBE1VBE1
iB1
gπ1 gm2VBE2 VBE2
iB2
gπ2
RC1 RC1Vin
Vout
VE
1 2 1 2 1 1
1 1
1 2 1 2
m m m
OUT C m IN
m m
g g g g g gR g
g g g g
V V
2
1 1
1 2
mOUT C m IN
m m
gR g
g gV V
1 1
2
C mOUT IN
R gV V
2OUTV
1 12
2
C mOUT IN
R gV V
Differential amplifier
Q1
Vin1
-VEE
RC1
Q2
RC1
VDD
IEE
VOUT1
AE1=AE2Vin2
VOUT2
1 11 1 2
2
C mOUT IN IN
R gV V V
1 12 1 2
2
C mOUT IN IN
R gV V V
• Very useful circuit
• This is a basic Op Amp
• Uses a current source and VDD for biasing (no biasing resistors or caps!)
• But – needs a dc current source !!!!
High-gain amplifier
VIN
VOUT
Q1
VDD
VEE
IB
8000VA
How can we build the dc current source?
What is the small-signal model of an actual current source?
Model of Current Source
V1
I1
Current
Source
LARGE
SIGNAL
SRXXI V1
i1
Current
Source
SMALL
SIGNAL
INR
“Reasonable Current Source”
IXX independent of V1 and RS large
Small-signal model of
current source
want RIN large
Ideal Current Source
V1
I1
Current
Source
LARGE
SIGNAL
XXI V1
i1
Current
Source
SMALL
SIGNAL
IXX independent of V1 INR =
Current Sources/Mirrors
Q0
VCC
R
Q1
AE0 AE1
Lo
ad
I1I0
Q0
VCC
R
Q1
AE0 AE1
Lo
ad
I1I0
V1
I1
Current Source
Will show circuit in red behaves as a current source
Current Sources/Mirrors
Q0
VCC
R
Q1
AE0 AE1
Lo
ad
I1I0
CC0
V -0.6VI
R
If the base currents are neglected
Current Sources/Mirrors
Q0
VCC
R
Q1
AE0 AE1
Lo
ad
I1I0
V1
CC0
V -0.6VI
R
If the base currents are neglected
BE0
t
V
V0 S E0I =J A e
BE1
t
V
V1 S E1I =J A e
since VBE1=VBE2
1E1
0E0
AI I
A
Behaves as a current source ! So is ideal with this model !!
Actually termed a “sink” current since coming out of load
Note I1 is not a function of V1
0 6CCE1
E0
V . VA
A R
And does not require an additional dc voltage source !!!
Current Sources/Mirrors
Q0
VCC
R
Q1
AE0 AE1
I1I0 I1
• Multiple Outputs Possible
• Can be built for sourcing or sinking currents
• Also useful as a current amplifier
• MOS counterparts work very well and are not plagued by base current
Current Sink
Current Sources/Mirrors
Q0
VCC
R
Q1
AE0 AE1
I1I0 I1
Current SinkKey Block
Biasing Circuit
End of Lecture 32
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