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Digital Processing Unit 1/16
PACS IBDR 27/28 Feb 2002
DPU PRESENTATION
R.Orfei & S. PezzutoCNR- IFSI
Digital Processing Unit 2/16
PACS IBDR 27/28 Feb 2002
Design status (1/2)
-Design Completed for the HW boards (contracted to Carlo Gavazzi Space): - CPU Board - I/F Board - DC/DC Converter Board - Motherboard-First set of boards delivered beginning of November 2000-DC/DC Converter to be delivered on 25-2-’02
Digital Processing Unit 3/16
PACS IBDR 27/28 Feb 2002
DESIGN STATUS (2/2)
• Cabling between Motherboard and Front Wall Connectors finished
• Design and manufacture of the box finished• AVM SW:
S/C IF (nominal mode): 100%(burst mode): under testingController: 100%HK monitoring: 100%Procedure handling: 100% (coding single proc.)1355 I/F: porting drivers under VIRTUOSO
Digital Processing Unit 4/16
PACS IBDR 27/28 Feb 2002
OBS ARCHITECTURE DESIGN
Digital Processing Unit 5/16
PACS IBDR 27/28 Feb 2002
BUDGETS FOR FM (1/2)(ACTUAL MASS INFERRED FROM AVM BOARDS)
• Box weight (mechanics): 3037 g CPU Boards (2 of): 960 g I/F Boards (2 of): 640 g DC/DC Boards (2 of) (E): 1000 g Motherboard: 520 g Screws etc.: 100 g Cabling (E): 300 g
Conformal coating (E): 420 g
TOTAL (E) 6977 g (+-200 g)
Digital Processing Unit 6/16
PACS IBDR 27/28 Feb 2002
BOX INTERFACE CONTROL DRAWING
Digital Processing Unit 7/16
PACS IBDR 27/28 Feb 2002
BUDGETS FOR FM (2/2)
TOTAL ESTIMATED POWER (DC/DC CONVERTER EFFICIENCY = 70%): 14.6 W
I W I W I W I W
CPU BOARD ONLY - DATA MEMORY (DM) TEST 1,050 5,250 0,015 0,038 0,000 0,000 0,000 0,000 5,288
MB + CPU + I/F - STAND BY 1,150 5,750 0,030 0,075 0,010 0,150 0,090 1,350 7,325
MB + CPU + I/F - DATA MEMORY TEST 1,400 7,000 0,030 0,075 0,010 0,150 0,090 1,350 8,575
MB + CPU + I/F - DM TEST + FSDL (EMPTY) FIFO READ 1,500 7,500 0,030 0,075 0,010 0,150 0,090 1,350 9,075
MB + CPU + I/F - DM TEST + 1553 TRANSMISSION 1,250 6,250 0,030 0,075 0,010 0,150 0,250 3,750 10,225
PRELIMINARY-DPU-AVM POWER CONSUMPTION
MEASUREMENT CONFIGURATION/DESCRIPTION TOTAL(W)
+5V SUPPLY +2,5V SUPPLY +15V SUPPLY -15V SUPPLY5 2,5 15 15
Digital Processing Unit 8/16
PACS IBDR 27/28 Feb 2002
CPU BOARD
DSP 21020
RAM
FPGA
EPROM
20 MHz
1355
MEZZANINE
JTAG
Digital Processing Unit 9/16
PACS IBDR 27/28 Feb 2002
I/F BOARD
FIFOS
FIFOS
S/S I/Fs A/D Conv.
16 MHz1553B (S/C I/F)
Long Stub Trafos“A” and “B”FPGA
Digital Processing Unit 10/16
PACS IBDR 27/28 Feb 2002
CPU+I/F+Motherboard assembled during preliminary tests at CGS
JTAG In Circuit Emulator (ICE)
ICE Computer Monitor
Power Supplie
s
Motherboard
Digital Processing Unit 11/16
PACS IBDR 27/28 Feb 2002
Assembly withcabling andconnectors
Boards fromcontractor
S/C SimulatorS/S Simulators
(IFSI)
Preliminary inhouse testsHW & LowLevel SW
Transfer LayerProtocol
EGSE (PACS)S/S Simulators
(IFSI)
Assemblywith
mechanics
Environmentaltests
Delivery toPACS
Full Integrationtests: HW &
SW
EGSES/S (OR S/SSimulators)
(PACS)
Tests commonto the wholeinstrument
AIV FLOW
Digital Processing Unit 12/16
PACS IBDR 27/28 Feb 2002SCHEDULES (1/4)
ID Task Name Duration Start Finish220 PACS OBS Development 126,8 wks Wed 03/01/01 Mon 09/06/03
221 S/C I/F task 48,8 wks Tue 30/01/01 Fri 04/01/02
222 S/C I/F study & S/W design 129 days Tue 30/01/01 Fri 27/07/01
223 S/C I/F task dvlpmt & integr.with VIRTUOSO 55 days Mon 30/07/01 Fri 12/10/01
224 S/C I/F task development under Windows 78 days Tue 31/07/01 Thu 15/11/01
225 S/C I/F task testing 36 days Fri 16/11/01 Fri 04/01/02
226 S/S I/F Tasks 36 wks Tue 27/03/01 Mon 03/12/01
227 S/S I/F study & S/W des. 44 days Tue 27/03/01 Fri 25/05/01
228 S/S I/F task dvlpmt& integr. 101 days Fri 25/05/01 Fri 12/10/01
229 S/S I/F task testing 36 days Mon 15/10/01 Mon 03/12/01
230 DPU OBS simulators 13,6 wks Mon 18/06/01 Wed 19/09/01
231 DPU S/Ss simulators 68 days Mon 18/06/01 Wed 19/09/01
232 OBS Controller Prototype 30 wks Wed 03/01/01 Tue 31/07/01
233 OBS Contr. Requ. study & task arch. 75 days Wed 03/01/01 Tue 17/04/01
234 Pototype development 45 days Wed 30/05/01 Tue 31/07/01
235 OBS Controller 22,4 wks Tue 31/07/01 Wed 02/01/02
236 OBS Controller development & integr. 54 days Tue 31/07/01 Fri 12/10/01
237 OBS Controller testing 58 days Mon 15/10/01 Wed 02/01/02
238 S/Ss Monitoring 13,6 wks Mon 01/10/01 Wed 02/01/02
239 S/S monitoring development & integr. 10 days Mon 01/10/01 Fri 12/10/01
240 S/S monit. testing 58 days Mon 15/10/01 Wed 02/01/02
241 OBS Architecture ready - AD Review 1 day Fri 28/09/01 Fri 28/09/01
242 AVM issue 0 0,2 wks Mon 15/10/01 Mon 15/10/01
243 PFM development 321 days Mon 18/03/02 Mon 09/06/03
S.Molinari[5%]
S.Molinari[10%]
S.Molinari[10%]
S.Molinari[20%
S.Pezzuto[10%]
S.Pezzuto[30%]
S.Pezzuto[15%]
S.Pezzuto[5%]
i Giorgio[10%];S.Pezzuto[10%]
A.Di Giorgio[10%]
S.Pezzuto[20%]
S.Pezzuto[20%]
S.Pezzuto[20%]
S.Pezzuto[20%]
15/10
May Jun Jul Aug Sep Oct Nov Dec Jan Feb2002
Digital Processing Unit 13/16
PACS IBDR 27/28 Feb 2002
ID Task Name Duration Start Finish244 SW Documentation 88,6 wks Wed 05/07/00 Fri 15/03/02
245 URD - User Requir. Doc 130 days Wed 05/07/00 Tue 02/01/01
246 SSD - SW Spec. Doc 56,4 wks Tue 02/01/01 Wed 30/01/02
247 Architecture 282 days Tue 02/01/01 Wed 30/01/02
248 OBS DDD - Detail design doc 52 days Thu 03/01/02 Fri 15/03/02
249 SVVP-SW Val &Ver. Plan 120 days Mon 01/10/01 Fri 15/03/02
250 OBS User Manual Draft 52 days Thu 03/01/02 Fri 15/03/02
251 DPU-OBS Integraftion 17,2 wks Tue 06/11/01 Tue 05/03/02
252 J-TAG DPU <=> S/S-Sim Test 30 days Tue 06/11/01 Mon 17/12/01
253 J-TAG DPU <=> S/C-Sim Test 19 days Thu 20/12/01 Tue 15/01/02
254 EGSE DPU-OBS Test 33 days Wed 16/01/02 Fri 01/03/02
255 Box Assembly 2 days Mon 04/03/02 Tue 05/03/02
256 PACS AVM delivery to MPE 1,69 wks Tue 05/03/02 Fri 15/03/02
A.Di Giorgio[10%];S.Pezzuto[10%]
S.Pezzuto[10%]
S.Pezzuto[10%]
S.Pezzuto[5%]
S.Pezzuto[5%]
S.Molinari[5%]
S.Molinari[10%];S.Pezzuto[45%]
P.Baldetti;A.Morbidini
S.Pezzuto;R. Orfei
Jul Aug Sep Oct Nov Dec Jan Feb Mar Apr May Jun Jul2002
SCHEDULES (2/4)
Digital Processing Unit 14/16
PACS IBDR 27/28 Feb 2002
ID Task Name Duration Start Finish258 PACS EQM 38,6 wks Wed 06/02/02 Fri 01/11/02
259 PACS EQM Acceptance Tests at CGS 38,6 wks Wed 06/02/02 Fri 01/11/02
260 Electrical Tests 1 day Tue 25/06/02 Tue 25/06/02
261 S/C I/F Signals 0,2 wks Wed 26/06/02 Wed 26/06/02
262 S/S I/F Signals 1 day Thu 27/06/02 Thu 27/06/02
263 SW Tests 1 day Fri 28/06/02 Fri 28/06/02
264 CPU+I/F+DC/DC + MB Boards at IFSI 1 day Mon 01/07/02 Mon 01/07/02
265 Mechanical mfg 4 wks Wed 06/02/02 Tue 05/03/02
266 Cabling 18 days Tue 02/07/02 Thu 25/07/02
267 DPU-OBS Integration 9 wks Fri 26/07/02 Thu 26/09/02
268 S/W Review 2 days Fri 06/09/02 Mon 09/09/02
269 Box Assembly 1 day Fri 27/09/02 Fri 27/09/02
270 Envir. Tests 5 wks Mon 30/09/02 Fri 01/11/02
271 PACS EQM Delivery to MPE 0,8 wks Mon 04/11/02 Thu 07/11/02
R. Orfei;R. Cerulli
R. Orfei;R. Cerulli
R. Orfei;R. Cerulli
R. Orfei;R. Cerulli
01/07
rbidini
A. Pavoni
S.Pezzuto[80%];R. Cerulli[10%];S. Molinari[10%]
S. Pezzuto;R. Cerulli;S. Molinari
A. Morbidini;P. Baldetti
R. Orfei[80%];R. Cerulli[20%];S. Pezzuto[20%]
R. Orfei;S. Pezzuto
May Jun Jul Aug Sep Oct Nov Dec Jan Feb Mar Apr May2003
SCHEDULES (3/4)
Digital Processing Unit 15/16
PACS IBDR 27/28 Feb 2002SCHEDULES (4/4)
ID Task Name Duration Start Finish273 PACS FM 80,6 wks Wed 06/03/02 Fri 19/09/03
274 DPU CDR 0,2 wks Thu 12/09/02 Thu 12/09/02
275 Mechanical mfg 4 wks Wed 06/03/02 Tue 02/04/02
276 Burn of Flight PROMs 2 wks Tue 27/05/03 Mon 09/06/03
277 Electrical Tests 1 day Tue 10/06/03 Tue 10/06/03
278 S/C I/F Signals 1 day Wed 11/06/03 Wed 11/06/03
279 S/S I/F Signals 1 day Thu 12/06/03 Thu 12/06/03
280 SW Tests 1 day Fri 13/06/03 Fri 13/06/03
281 CPU+I/F+DC/DC Conv. MB Boards at IFSI 1 day Mon 16/06/03 Mon 16/06/03
282 Cabling 18 days Tue 17/06/03 Thu 10/07/03
283 DPU-OBS Integration 5 wks Fri 11/07/03 Thu 14/08/03
284 Box Assembly 1 day Fri 15/08/03 Fri 15/08/03
285 Envir. Tests 5 wks Mon 18/08/03 Fri 19/09/03
286 PFM S/W TRR 0,2 wks Tue 16/09/03 Tue 16/09/03
287 PACS FM Delivery to MPE 1 wk Tue 23/09/03 Mon 29/09/03
R. Orfei;R. Cerulli
R. Orfei;R. Cerulli
R. Orfei;R. Cerulli
R. Orfei;R. Cerulli
16/06
A. Pavoni
S.Pezzuto[80%];R. Cerulli[10%];S. Molinari[10%]
A. Morbidini;P. Baldetti
R. Orfei[80%];R. Cerulli[20%];S. Pezzuto[20%]
S. Pezzuto;R. Cerulli;S. Molinari
R. Orfei;S. Pezzuto
Mar Apr May Jun Jul Aug Sep Oct Nov Dec Jan Feb2004
Digital Processing Unit 16/16
PACS IBDR 27/28 Feb 2002PA/QA ACTIVITIES
• ALL COMPONENTS ARE BOUGHT THROUGH THE CO-ORDINATED PARTS PROCUREMENT
AGENCY
• FOR INDUCTORS AND TRANSFORMERS RELEVANT RFAs AND PADs ARE ISSUED
• NO RE-FLOW SOLDERING IS FORESEEN: ALL HAND MADE SOLDERS BY ESA QUALIFIED
PERSONNEL
• ENVIRONMENTAL QUALIFICATION TESTS ARE SCHEDULED FOR QM UNITS
• ENVIRONMENTAL ACCEPTANCE TESTS ARE SCHEDULED FOR FM UNITS
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