digitally assisted analog circuits · 2015. 7. 29. · boris murmann department of electrical...

Digitally Assisted Analog Circuits

Bernhard BoserBoris Murmann

Department of Electrical EngineeringUniversity of California, Berkeley

„Moore‘s Law“ for Digital Circuits

2x every1.9 years

≈10,000 MIPS0.3 MIPSLead µP Peformance

2x every1.8 years≈200 Million5000Lead µP

Transistors/die

0.7x every2-3 years0.13µm6µmTransistor

Feature Size

Rate of Change20021974

[Moore, ISSCC 2003]

„Moore‘s Law“ for Analog Circuits

1.0E+08

1.0E+09

1.0E+10

1.0E+11

1.0E+12

1.0E+13

1.0E+14

1985 1990 1995 2000 2005

Ban

dwid

th x

Res

olut

ion

[Hz-

LSB

]

Lead µP Slope (2x/1.9years)

Lead ADC: 2x/4.7 yearsAll ADCs: 2x/6.1 years

50x

Perf

orm

ance

Impact of Moore’s Law

Digital circuitry:o Cost/function decreases by 29% each yearo That’s 30X in 10 years

Analog circuitry:o Cost/function is constanto Dropping supply voltages threaten feasibility

Transition to DSP is inevitable!

Ref: International Technology Roadmap for Semiconductors, http://public.itrs.net

Digitally Assisted Analog Circuits

Concept:o Relax analog domain precisiono Recover accuracy in digital domain

Benefits:o Improve compatibility with fine line technologyo Reduced power consumption

Examples:o Nonlinear amplification in A/D converterso Digital pre-distortion in power amplifierso Nonlinear equalization

Outline

Pipelined analog-to-digital converterAnalog errors and digital correctionCorrection parameter estimationResults

Pipelined ADC

Dominant topology for wide performance range: 10-14 bits, 10-200MHz

Σ

A/D D/A-

D

VresVin

STAGE 1 STAGE N-1 STAGE NS/H

R bits

Vin

2R

D=0 D=1

⇒

V res

Vin

(e.g. R=1)

Σ

A/D D/A-

D

VresVin

2R

Relax Analog Precision?

Redundancy (RSD arithmetic) helps tolerate

large sub A/D errors[Lewis, 1987]

“Digital calibration“ removes D/A and linear gain error by

adjusting digital weights[Karanicolas, 1993]

Σ

A/D D/A-

D

VresVin

2R

Relax Analog Precision?

Remaining challenge: Fast, highly linear gain element50-70% of total pipeline ADC power is consumed by interstage amplifiers

Redundancy (RSD arithmetic) helps tolerate

large sub A/D errors[Lewis, 1987]

“Digital calibration“ removes D/A and linear gain error by

adjusting digital weights[Karanicolas, 1993]

Conventional Gain Element

Electronic feedback linearizes, stabilizesHigh gain requirement costs headroom and/or additional stages ⇒ power penaltySemiconductor technology trend: Decreasing VDD and low intrinsic device gain!

E.g. [Kelly, ISSCC 2001]

Open-loop Amplification“Open loop“

☺ Power ↓↓Precision ↓↓

Sensitivity ↑↑

Precision Amplifier

Digital Correction

Digital Post-Processor ADC

VinDraw Dcorrected

Issues:Analog domain errors Digital correction mechanismError measurement and tracking

Amplifier Nonlinearity

Vi

ISS

R R

Vo

-1.5 -1 -0.5 0 0.5 1 1.5-1.5

-1

-0.5

0

0.5

1

1.5

Vi/Vdsat

Vo/(I

SS*

R)

Diff. Pair TFTangent

?2max

=

⋅

dsat

i

VV

Pipeline Stage Error Model

Σ

A/D D/A-

D

VresVin a1Σ

Vos

a2Vx2

a3Vx3

Σ

2R⇒

How can we linearize the ADC digitally ?

Vresb1 Σ A/D

b3Vx3

b3Vx3

-

Dres

Linearization Concept

• Problem: amplifier input is an analog signal

Vresb1 Σ A/D

b3Vx3

Σ-

e(Vres)

Dres

Linearization Concept

0:

2712

cos31

3cos

312)( 3

1

33

3

1

3<=

−⋅+−−= −

bbpwith

p

Vp

VVe resresres

π

Vresb1 Σ A/DD'res

b3Vx3

Σ-

e(Dres)

Dres

Digital Linearization

Single-parameter correction function can be pre-computed and stored in look-up table (ROM)Small ROM size achievable through continuous data compression methods

Calibration Concept

Correction parameters depend on temperature, etc.Classical “foreground calibration“ unfeasibleNeed continuous “background calibration“ during normal A/D operation

Classical Approach: Problem:

Time

ChipTemp. IdlePower-Up

Bad timeto calibrate!

Calibratenow?

A/DVin

CalibrationCircuit

Dout

TestSignal Param.

Approach: Two-Residue Pipeline StageΣ

A/D D/A-

D

VresVin

Σ

SHIFT

-1 -0.5 0 0.5 1-1

-0.5

0

0.5

1

Vres

/Vre

f

-1 -0.5 0 0.5 1-1

-0.5

0

0.5

1

Vres

/Vre

f

⇒

Add: Digital SHIFT signal, redundant A/D and D/A statesCan carry out conversion on “red“ or “black“ segments

Digitized Segment

Idea: Measure h1, h2 and force difference ∆h to 0How measure ∆h without interrupting A/D operation?Solution: Statistics based measurement

0 0.1 0.2 0.3 0.4 0.5Vi/Vref

Dre

s (0

...2B -1

)

h2h1

no calibration: h1<h2

0 0.1 0.2 0.3 0.4 0.5Vi/Vref

Dre

s (0

...2B -1

)

perfect calibration: h1=h2

h2h1

Dre

s (0

...2B -1

)

"Red" withProb. 1/2

"Black" withProb. 1/2

Input Samples Vin(k)

Distance Estimation (1)

For each input sample “fair coin toss“ decides red/black

Distance Estimation (2)

Dre

s (0

...2B -1

)

f(Vin(k))

vinvq

q CHref(q)

Simple input model: stationary random processCount # of codes ≤ q in “black channel“→ cumulative histogram CHref(q)

Distance Estimation (3)

Dre

s (0

...2B -1

)

f(Vin(k))

vin

h

CHref(q)

CH(j)CH(j-m)

CH(j+m)

vq

H*

Place counter array in “red channel“After n samples, find “red“ count that is closest to CHref (q) ⇒ Distance Estimator H*

LMS Loop

Vini Vresi A/DD'resDresi

Σ-

e(D'res)

p3

STAGE i

DistanceEstimation

Σ

H1 H2

Accum. µ

-

b

Accumulator forces average ∆h = H2-H1 to zeroStraightforward extension to track offset and gain errors

Die Photograph

“Proof of concept“: 12bit, 75MHz ADC, 0.35µmRe-used commercial part (Analog Devices AD9235)Digital post-processor off-chip (FPGA)

REFERENCEAND BIAS

PIPELINEBACKEND

STAGE1SHA

CLK

LOGIC

Measurement Results: Linearity

0 1000 2000 3000 4000-1

-0.5

0

0.5

1(b) with calibration

C d

0 1000 2000 3000 4000

-10

0

10

(a) without calibration

Code

INL

[LSB

]

RNG=0RNG=1

0 1000 2000 3000 4000

-10

0

10

(b) with calibration

Code

INL

[LSB

]

Stage1 Power Savings

0

10

20

30

40

50

Power [mW]

AD9235 Prototype

Sub-A/DBiasingAmplifierPost-Processor*

(*simulated, 0.35µm)

Incl. Post-Processor

Excl. Post-Processor

-52%-74%

-36%-48%

Stage1 PowerAmplifier Power

Digital Post-Processor

Area=1.4mm2 (18%) Power=10.5mW (3.6%)

• 8400 Gates, 64 bytes RAM, 64kBit ROM• Implementation in 0.35µm technology:

Pipelined ADC(7.9 mm2)

Post-Processor0

10

20

30

40

AmplifierSavings

Post-Processor

Pow

er [m

W]

Conclusions

Digital versus analog scalingo Digital circuit performance improves faster than analog

o Digital circuits benefit from scaling

o Voltage scaling jeopardizes analog circuit feasibility

Digitally assisted analog circuitso Reduced sensitivity to analog imperfections

o Compatibility with fine-line CMOS

o Benefit from technology scaling

Digitally assisted ADCo Open-loop interstage amplification

o ~50% amplifier power reduction

o Advantages increase at reduced feature size