development of an implantable radio identification tag for steller sea lion pups hamid meghdadi...

Development of an Implantable Radio Identification Tag For

Steller Sea Lion Pups

Hamid Meghdadi

Summer 2006

Simon Fraser University

Headlines

Simon Fraser University Introduction Tool and Utilities Tests and Measurements Conclusion

Simon Fraser University

Location: Vancouver, BC, Canada Established: September 1965 Students: 25000 Annual expenses: $300 million School of engineering science:

Since 1983M.Eng, M.Sc, Ph.D

Introduction

Steller Sea Lions: Endangered species Unknown mortal rate Unknown immigration

pattern

Existing Tags: Glued: fall off Large Surgically invasive Limited life span

Design an Implantable Radio Identification Tag

Introduction

Design Targets: 2-3 years life span (power

management) Identity Biocompatible Report rate (1/hr) 3 x 6.5 x 0.3 cm Radio tag $100

Implanted tag will be on for 1 ms every hr

Reporting base station

Introduction

Tag:

Wakes up every hour

Sends its identification code

Receiver:

Receives the information

Detects the tag

Sends data to computer

Computer:

Receives the information

Analyses data

Saves reports for biologist

Base Station

Tag

RF Identification Tags

Substrate

Electronic components Loop

antenna

Loop

Antenna

Matching

Network

IA4420

Transceiver

MSP430

Microcontroller

JTAG Interface

RF Identification Tags

JTAG Interface

Microcontroller

Transceiver

Antenna and matching network

Base Station

Final Robust Construction Link budget (?) Placement(?)

=> Research

Prototype (Test) Receive data Save log Evaluate tag’s

efficiency Use available

components

Tools and utilities

MSP430 μ-Controller IA 4420 Transceiver MSC-DKLB1 Board StratixII FPGA Board LabVIEW

TI MSP430 Family: Ultra-low-power 16 bit RISC CPU Integrated peripherals

USART ADC ...

Flexible clock system Internal External

Integrated E²PROM, RAM and Flash memories.

Tools and utilities

MSP430 μ-Controller IA 4420 Transceiver MSC-DKLB1 Board StratixII FPGA Board LabVIEW

Integration’s IA4420: Multi-channel FSK transceiver Unlicensed use in 315, 433, 868, 915

MHz Low-power SPI Interface VDI, ARSSI Wake-up timer Interrupts:

POR Wake-up timeout TX Empty or RX Full …

Tools and utilities

MSP430 μ-Controller IA 4420 Transceiver MSC-DKLB1 Board StratixII FPGA Board LabVIEW

MSC-DKLB1 Evaluation Board Interface between PC and IA chip Serial RS232 Interface to PC PC End utility:

Any terminal simulator program (Hyper Terminal)

WDS (User Friendly Interface) Capable of:

Sending SPI commands to the chip Driving chip inputs high or low Monitoring chip outputs Reading RX FIFO and Status Registers

Tools and utilities

MSP430 μ-Controller IA 4420 Transceiver MSC-DKLB1 Board StratixII FPGA Board LabVIEW

StratixII DSP Development Board Development platform for high-

performance DSP design Components:

A/D and D/A VGA Output Audio CODEC RS-232 Interface Dual 7 Segment display Switches and LEDs …

Tools and utilities

MSP430 μ-Controller IA 4420 Transceiver MSC-DKLB1 Board StratixII FPGA Board LabVIEW

NI LabVIEW Programming tool G-Code based Built-in functions Applications:

Instrumentation Industrial control systems

Tests and Measurements

Communicating with IA4420 DC Power Requirements Power Consumption Test Transmission Efficiency Test 1 Transmission Efficiency Test 2 Bit Error Rate Test

Communicating with IA4420

IA4420

nSEL

SCK

SDI

nIRQ

(Transmitter Mode)

FSK

Two Transmission Modes: FSK Input Active

Data at FSK input is transmitted Bit rate controlled manually TX register not used

TX Register Buffered FSK input must be high Data delivered to chip via SPI link Bit rate controlled internally

Communicating with IA4420

IA4420

nSEL

SCK

SDI

nIRQ

(Transmitter Mode)

FSK Configuration Setting Command Power Management Command Data Rate Command Status Read Command

Communicating with IA4420

IA4420

nSEL

SCK

SDI

nIRQ

(Transmitter Mode)

FSK Configuration Setting Command Frequency Band Oscillator load capacitor

Power Management Command Data Rate Command Status Read Command

Communicating with IA4420

IA4420

nSEL

SCK

SDI

nIRQ

(Transmitter Mode)

FSK Configuration Setting Command Power Management Command

Receive/Transmit Wake-up timer PA, XTAL, …

Data Rate Command Status Read Command

Communicating with IA4420

IA4420

nSEL

SCK

SDI

nIRQ

(Transmitter Mode)

FSK Configuration Setting Command Power Management Command Data Rate Command Status Read Command

Communicating with IA4420

IA4420

nSEL

SCK

SDI

nIRQ

(Transmitter Mode)

FSK

Interrupt Events: TX register ready POR TX register overflow Wake-up timer timeout Low Battery Detect

Communicating with IA4420

IA4420

nSEL

SCK

SDI

nIRQ

(Receiver Mode)

FSK

Two Reception Modes: FIFO not used

FSK: Received data DCLK: Data clock RX FIFO not used

FIFO Mode Data is stored in a 16 bit FIFO FIFO can be read by SPI link

DCLK

VDIARSSI

Communicating with IA4420

IA4420

nSEL

SCK

SDI

nIRQ

(Receiver Mode)

Interrupt Events: FIFO Full POR FIFO overflow Wake-up timer timeout Low Battery Detect

FSK

DCLK

VDIARSSI

Communicating with IA4420

IA4420

nSEL

SCK

SDI

nIRQ

(Receiver Mode)

Data Detection: VDI

Valid Data Indicator Digital signal Slow

ARSSI Analog Received Signal Strength

Indicator Fast

FSK

DCLK

VDIARSSI

DC Power Requirements

DC

out

DCDDDC

P

P

IVP

Objective: Determine the best supply voltage for the tag

Power

SupplyTag

Spectrum

Analyzer

POut

IDC

VDD

DC Power Requirements

VDD=2.2 V

Power Consumption Test

Objective: Power consumption of tag in its different states

3 Bytes 3 Bytes 3 Bytes

2 Sec 2 Sec

The Tag will wake up every 2 seconds

On each wake-up event, tag will transmit 24 bits

The current pass through the tag is measured continuously

Power Consumption Test

Main Program

Interrupt Service routine

(Wake-up event activated)

Power Consumption Test1) Wake-up timer expires

2) Micro reads interrupt → Interrupt released

3) Micro enables transmission

5) PA on, transmission starts → Max power (I=22 mA)

6) One byte is transmitted, TX is empty

7) Micro sets next byte for transmission, TX no longer empty

8) Transmission finished

9) Tag goes back to sleep mode

Transmission Efficiency Test 1Objective: Evaluate tag’s efficiency and reliability

3 Bytes 3 Bytes 3 Bytes

2 Sec 2 Sec

The Tag will wake up every 2 seconds

On each wake-up event, tag will transmit 24 bits

Base station waits for a valid packet and creates a report

0xAA0xDB0, 1, 2, .., 255, 0, 1, …

8 bits of preamble8 bits of synchronization8 bits of data

Valid Packet: VDI = High Preamble & Sync Correct

Transmission Efficiency Test 1

Programming phase: Programming tag Programming FPGA Configuring IA evaluation board

RS-232

JTAGUSBUSB

JTAG

GND, VDI, CLK, DATA

RS-232

Base Station

Tag

Running phase: Tag transmits a packet every 2 seconds IA board receives data and provides DATA, CLK, VDI FPGA reads these lines, detects packet, Sends to PC LabVIEW reads from RS-232, saves report

Transmission Efficiency Test 1Search Communicate

Searches for a packet Timer counts

Max → LED

Data byte → 7 Segment Timer reset to zero Send character to PC

Transmission Efficiency Test 1

Valid data“= 01010“ ”11011011? ”

DATA_IN0…67…19…23

LSBData (23 downto 0)MSB

Transmission Efficiency Test 1LabVIEW Program

Transmission Efficiency Test 1

3 Bytes 3 Bytes 3 Bytes

Results not very good Range ≈ 1m Efficiency < 90%

VDI too slow A better VDI is required

VDI

FPGA will not detect

this packet

Transmission Efficiency Test 2

Transmission Efficiency Test 20xAA0xAADB55590, 1, 2, .., 255, 0, 1, …

8 bits of preamble32 bits of synchronization8 bits of data

Final test postponed CVDI more reliable Results much better

Range ≈ 1 km Efficiency > 95% Improvements

possible

Bit Error Rate Test

Objective: Estimate the BER of the link Tag will transmit continuously Base station will:

Receive the data Compare received data with expected data Count the number of erred bits Display the BER estimation on request

0x1F0xAA0x000x010x02…0x1E0x1F0xAA

Previous packet

AligningData bytes (32 bytes = 256 bits)Next packet

One Packet

The tag will transmit this pattern:

Bit Error Rate TestFPGA state machine:

Bit Error Rate Test

Bit error

calculation

circuit

Seven

Segment

Display

Circuit

Transmission Efficiency Test 2LabVIEW Program

Conclusion

Next steps for project: A more efficient antenna for

base station Evaluate efficiency of

implanted tags when animal moves in different environments

Battery selection Using an array antenna and

diversity techniques in base station

Characterize the link budget by the range and environment

Personal advantages: Autonomy Telecommunications

knowledge Antenna matching Fading effect FSK mod/dem Bit rate & deviation vs. quality

FPGA and microprocessors knowledge

Apply basic electronics theory

Thank you