designing systems in chips interconnect fabric · puneet gupta (puneet@ee.ucla.edu) sudhakar...
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Designing Systems in CHIPS Interconnect Fabric
Puneet Gupta (puneet@ee.ucla.edu) Sudhakar Pamarti
Ankur Mehta
Chip
Package
Board
CHIPS Design System Vision
Architecture, RTL, Synthesis
IP integration, physical design
IO, functional, physical, noise,
power , thermal
verification
Package/substrate architecture exploration
Package pin location, routing
Timing, noise, power, assembly, IO verification
Architecture, RTL, Synthesis
IP integration, physical design
IO, functional, physical, noise,
power verification
Interconnect Fabric Thermal/Electrical/Mechanical
Integrated Design System Assembly of pre-verified dielets
on a package-free substrate
SOC Design SOC Fabrication and Hardware Test
System Integra
tion
Dielet Assembly on
IF
IF Fab and Test
TODAY
PROPOSED
3 years
3 months 6 months
3 months 1 year
Package pin location, routing
Timing, g, gnoise, pe, p, power, assesseembly, IIIOO Overive ficatiotiontt
Architectecee tureturetureu , RTL,TL,TL, Syn SynSynSynthesthesthesth is
Iphy
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on a packaaaagegegege-ffrff eeeeeee ss ssububububstrate
SOSOSOOCC Design
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IF FIF FabFabFabFa andandandand TesTesTesTestttt
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month
Overall SIF Design Flow
• Key elements – System-level thermal modeling and
thermally-aware dielet floorplanning – Dielet assembly timing/noise/power
analyses to integrate multiple PDKs (from heterogeneous dielets) • Resistive rather than transmission line
behavior of interconnect – Simplified parallel I/Os for dielets
and appropriate I/O selection • Build upon existing SoC design
infrastructure
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ing/noise///pppooowwweeeerrr grate muuullltttiiipppleee PPPPDDDKKKsss
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SIF Design Components • Dielets – Pre-fabricated bare die – Hard IP with perimeter IO
• automated redistribution layer design – Discrete components
• Interconnect substrate – Fine pitch on rigid substrate
• Need tolerance to unreliable bonding – Flexible substrate
• Need to model flex stresses and failures
tribution layeeerrr dddeeesssiiigggnnn
eeeddd ttttooooo mmmmmooooodddddeeeeellll fffffllllleeeeexxxxx steeeesssss
Electrical Environment in SIF • Numerous I/Os
– Potentially complex electromagnetic crosstalk • Numerous supply domains to power the various dielets
– Significant isolation/coupling concerns • Several clock domains
– Different frequencies and performance – Clock domain crossing and synchronization concerns
• Elaborate “dielet management” tasks – Selective sleep/wakeup of individual or groups of dielets
• Individual dielet failure – self-test, self-healing, and redundancy requirements
• Interconnect variability and resilience
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coupling cooonnnccceeerrrnnns
quencies aaaaannnnddd perrrfffooorrrmannnccccceeeee
Standardized Interfaces: Enabler for Fast IF-based System Design
• Physical standardization – pad/bump sizes, wire pitches
• Electrical standardization – voltage/current levels, resistive/capacitive load
• Functional standardization – Communication interfaces e.g., multi-Gb/s digital I/O, Z-controlled
analog I/O, etc. – Dielet health monitor interfaces
• Temperature, state info, error/mismatch info etc. • Facilitate system tuning, self-healing, self-testing
– Control interfaces • Dielet configuration, etc
• Test standardization – Continuity tests, JTAG-like infrastructure for BIST
resistive/capppaaaccciiitttiiivvveee llloooad zation
on interfaceeeeesss eee.g., mmmuuulti-GGGbbbb/////sssss ddddiiiiigggggiiiitttttaal I/,,, eeeeettttcccc...
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Active IF: Getting to Plug-n-Play Dielet Assembly
• Active Interconnect Fabric – Library of dielets to handle necessary interface tasks
• Regulator dielets, I/O dielets, clock dielets, test dielets … – Library cells available as hard IP
All green blocks are interface dielets� active interconnect fabric
32-bit multi-core microprocessor
e.g. Leon3
Regulator Dielet
I/O Dielet Local Clock Dielet
I/O
Die
let
SRAM Cache
I/O
Die
let
Local Clock Dielet
Regulator Dielet
SRAM Cache
I/O Dielet
Local Clock Dielet
Regulator Dielet
FLASH Memory
I/O Dielet
Local Clock Dielet
Regulator Dielet
I/O Dielet
ADC16b, 65MSPS I/
O D
iele
tLocal Clock Dielet
Regulator DieletRegulator Dielet
Master Clock Dielet
SuppliesClockSignal I/O
Logic
Translator (AMS)
MemoryMemory
3rd party AMS
Supply & Clock Connections to Translator Dielets Not Shown
GaN LNA
Regulator Dielet
Analog I/O
Dielet
Anal
og I/
O
Diel
et
GaN
Other blocks are application specific dielets (ASDs)
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Local Clock Dielet
I/O
Die
let
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O
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SRAM Caccchehehe
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ReRegRe ulatototor DDDielettt
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Regulator Dieletttt
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Eventual Push-Button SIF Design • Secure dielet repository
– Inventory – Design description (behavioral, timing views, etc) – Models (thermal, PDK, etc)
• A visual hardware description system – Easy to use, cloud hosted to proliferate use in educational
and Maker communities – Automated dielet selection from repository – Automated dielet assembly and verification
• “SIF in a day” with limited hardware design background
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MMaaaakkkkkeeeeerrrr cccccooooommmmmmmmmmuuuunnnniiiittttiiieeeeesssssutommmmmaaaaattttteeeeeddddd dddddiiiiieeeeellllleeeeettttt ssssseeeeellllleeeeecccccttttiiiioooon ffffrom
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Next Frontier: Cyberphysical Systems on IF
• Cyber-physical dielet capabalities – RF – Optics – MEMS
• Additional design constraints – Structural (SIF weight) – Geometric (SIF shape)
• Interdisciplinary design automation – Electrical + mechanical + software subsystems
• “Robot in a day” with limited hardware design background
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