design methodology using verilog models

Design Methodology Using Verilog Models

Ignatius BezzamArasan Chip Systems

San Jose, CA, USA

Topics

IntroductionDesign Methodology FlowLibrary FeaturesCase Study: USB3.0 Analog PHY• Transmitter Model

• Loop Filter• Receiver Model

Simulation ResultsConclusions

December 9, 2009 Arasan Confidential Page 2

Introduction

Design of Complex Analog Circuits• Large number of simulations – computation intensive and

time consuming• Susceptible to changes in process parameters

• Can lead to redesigning of blocks and simulations• Leads to increased TTM

Modeling Analog Blocks using HDLs• Digital Circuit Simulations are quick

• Reduces design and simulation times• Reduces actual analog design iterations if modeled

accurately• Bridges the gap between analog and digital design flows

Design Methodology FlowMSOffice1

Slide 4

MSOffice1 spello libraTry , 11/25/2009

Analog Model Library Features

Basic Blocks – PLL(VCO, Charge Pump, PFD, Frequency Divider), ADCs, Multipliers, AddersModels of completely analog blocks are realized using

• I/O Transfer Characteristics eg., VCO• Solving Transfer Functions eg., Filters

Full digital blocks are realized in RTL eg., Multipliers, Adders etc.,All models must be parameterizable for easy customizationAll models must be able to adopt to process parameter changes

USB 3.0 Analog PHY Model

A‐PHY

Transmit driverD-PHYLink Data Path

Link status state m/c

Transmit PLL

Power managementPHY

management interface

Device function processor

CDR A/D

AnalogDigital

MSOffice3

Slide 6

MSOffice3 No A/D but Serializer , 11/25/2009

USB 3.0 Transmitter Model

PFD, Divider and Sigma-Delta modulator are purely digital blocksCharge pump, VCO and Loop Filter are purely analog blocks

Spread Spectrum ClockPLLfref

Retiming Block:Parallel to Serial

ConverterData

D+

D-

TXDriver

clockphases

SSC PLL

Loop Filter

R1

C1

C2

+n0/d0

n1/d0

n2/d0

Z-1

Z-1

-(d1/d0)

-(d2/d0)

Z-1

Z-1

)(1)(

211212

11

CCsRCCsCsRsH

+++

= 22

110

22

110)( −−

−−

++++

=zdzddznznnzH

Bilinear

Transformation

USB 3.0 Receiver Model

ADC, CDR PLL can be purely analog modelsEqualizer can be purely digital modelHigh speed digital blocks can be optimized by pipelining

ADC Equalizer

Phase Detector

CDR PLL

CommaDetector

D+

D-

RecoveredData

RecoveredClock

Simulation Results

Transmitter Waveforms

Simulation Reults

Transmitter Waveforms

Simulation Results

Transmitter Waveforms

ConclusionsAny new logic to be added can be modeled first in verilog, proven by simulating and then incorporated in the actual circuit design processAny changes in process parameters which might lead to design changes can be predicted without actual circuit design

• Maintaining libraries for different process and different process corners

Verilog models can act like catalysts for the analog design processArchitecture Optimization time is reduced

• Specially for digital assisted analog techniques in deep sub-micronModels must be made parameterizable for easy customization