design automation for rf system-on-package design using ltcc

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Design Automation for RF System-on-Package Design

using LTCC

• 盧信嘉 助理教授• leonardo@cc.ee.ntu.edu.tw

• 台灣大學電子工程學研究所

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Outline

• What is RF-SoP? • LTCC • Basic building elements

– Lump elements– Distributed elements

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Outline (cont’)

• Design flow– Automatic Component Synthesis– Design Rule Check (DRC)– Layout vs. Schematic (LVS)

• Conclusion

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A PC-card WLAN card reference design

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RF-SoP approaches

• Replace discrete components with embedded ones for size and area reduction.

• Addition of more functional blocks, such as an antenna or filters to the module.

• Optimize performance by replacing on-chip passives with high-Q passives embedded in package.

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LTCC

• LTCC: low temperature cofire ceramic• Multi-layer, vias, blind vias, buried resistors• Metal: Cu, Ag, Au• Passive elements, transmission lines can be

placed inside or on surface of LTCC.• Active elements on surface

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Making the tape

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Tile manufacture

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•Highly integrated LTCC components

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Basic building blocks

• Lump elements: – Capacitors– Inductors

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Multilayer inductors

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•One-port and two-port equivalent circuits for LTCC inductors.

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Multilayer capacitors

• 0.49 fF/mil square for 3.6mil substrate

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•One-port and two-port equivalent circuits for LTCC capacitors.

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Design flow

• Substrate selection: cost, loss, process resolution …

• Specification participation• EM simulation of building elements• Circuit simulation and iteration with EM

simulation

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Design flow (cont’)

• EM tools: – 2.5D: Sonnet, Agilent ADS Momentum,

Ansoft Designer, Zeland IE3D– 3D: Ansoft HFSS, XFDTD, Zeland Fidelity

• Circuit simulator: Agilent ADS, Microwave office, Cadence Spectre RF.

• DRC (Design Rule Check), LVS (Layout versus Schematic)

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Multilayer filter: image rejection for Bluetooth

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D inner=30mile D outer=72mile W=8mile

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Target value of 3D inductor

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3D structure

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Simulation result @ 4nH

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Design Rule Check (DRC)Via cover pad

(V2)Via to partedge spacing

(C2&C3)Conductor topart edge

(C1)Line spacing

(C1)Line width

(V4)Via cover pad toconductor spacing

(V1)Via pitch

Ground plane

(V7)Via size

(V9)Via cover paddiameter(cofired)

(C5)Via pass through largh area plane

Top view layout of LTCC design

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Design Rule Check (DRC)

Cross-Section of LTCC design

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Design Rule Check (DRC)

• Use the engine in Calibre or other IC DRC tools

• Rewrite the rule for LTCC process

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Layout vs. Schematic (LVS)

• Complex 3D structure• The designer have to modify the layout to

tune the performance.• It is highly possible to miss place vias or miss

some conductors in modification process.• The LVS checker must be able to correctly

correlate the modified physical layout to schematic

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Conclusion

• Design automation tool to reduce design time and human effort.

• Verification tool to increase yield and prevent design errors.

• Some EM feeling is required, but you do not have to solve Maxwell equation.