datorteknik delayedbranch bild 1 delayed branch all problems solved? no, what will happen if...... b...

Datorteknik DelayedBranch bild 1

Delayed Branch

All problems solved?

NO, what will happen if......

b loop

add $4 $6 $1

..

.

loop sub

Datorteknik DelayedBranch bild 2

Branch

logic

Sgn/Ze

extend

Zero ext.

ALU

A

B

31

0

4+

+

= =

= =

B loopAdd

Datorteknik DelayedBranch bild 3

Branch

logic

Sgn/Ze

extend

Zero ext.

ALU

A

B

31

0

4+

+

= =

= =

B loopAdd sub

Datorteknik DelayedBranch bild 4

Delayed Branch

- Throughput might decrease, (nop).

- Assembler/Compiler dependent.

+ Keep critical path short

Datorteknik DelayedBranch bild 5

All problems solved now?

NO, what will happen if......

..

bal loop

add $4 $6 $1

xor ....

loop: sub ...

..

j $ra

Datorteknik DelayedBranch bild 6

Branch

logic

Sgn/Ze

extend

Zero ext.

ALU

A

B

31

0

4+

+

= =

= =

> ADDR 0x00400000 bal loop

bal loop

ADDR 0x00400004

Datorteknik DelayedBranch bild 7

Branch

logic

Sgn/Ze

extend

Zero ext.

ALU

A

B

31

0

4+

+

= =

= =

ADDR 0x00400000 bal loop

> ADDR 0x00400004 add

ADDR 0x00400004

bal loopadd

Datorteknik DelayedBranch bild 8

Branch

logic

Sgn/Ze

extend

Zero ext.

ALU

A

B

31

0

4+

+

= =

= =

ADDR 0x00400004

ADDR 0x00400004

bal loopadd

ADDR 0x00400000 bal loop

ADDR 0x00400004 add >loop: sub

sub

Datorteknik DelayedBranch bild 9

Branch

logic

Sgn/Ze

extend

Zero ext.

sub

.. .. j $ra

ALU

A

B

31

0

4+

+

= =

= =

ADDR 0x00400004

jr $ra

Datorteknik DelayedBranch bild 10

Branch

logic

Sgn/Ze

extend

Zero ext.

Oooh not again!!!

ALU

A

B

31

0

4+

+

= =

= =

0x00400004 add

Datorteknik DelayedBranch bild 11

Branch

logic

Sgn/Ze

extend

Zero ext.

ALU

A

B

31

4

4+

+

= =

= =

ADDR 0x00400004

ADDR 0x00400008

Continue at 0x00400008bal loopadd sub

Datorteknik DelayedBranch bild 12

Branch

logic

Sgn/Ze

extend

Zero ext.

sub

.. .. j $ra

ALU

A

B

31

0

4+

+

= =

= =

ADDR 0x00400008

jr $ra

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All Hazards Fixed but:

One “delayed branch” slot

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What about “delayed Branch”

Can we avoid it? How?

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IM

Reg DM Reg

Delayed Branch

Direct Branch

BranchLogic

IM

Reg DM Reg

BranchLogic

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Branch

logic

Sgn/Ze

extend

Zero ext.

ALU

A

B

31

0

4+

+

= =

= =

Delayed Branch

Datorteknik DelayedBranch bild 17

Branch

logic

Sgn/Ze

extend

Zero ext.

ALU

A

B

31

0

4+

+

= =

= =

Branch

logic

Direct Branch

Datorteknik DelayedBranch bild 18

What about the instruction set?

beq $t0 $t0 label? jr $ra? NO, DE is not in path! b label? OK, but the new branch logic needs an ALU

to compute the address

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Different branch logic?

Can both branch types coexist? Yes, no problem, but: Old type still uses “delay slot”