conception d’un processeur dsp faible énergie en logique ternaire
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Conception d’un processeur DSP faible
énergie en logique ternaire
O. SENTIEYS, M. ALINE, E. KINVI-BOH Université de Rennes - ENSSAT
IRISA
sentieys@enssat.fr
FTFC 2003, Paris, 14-16 Mai 2003
2
Outline MotivationsMVL implementation with SUS-LOC
Principle of SUS-LOC structures Characterization at the transistor-level Characterization at the gate-level
Design of a ternary DSP structureExperimental results and comparisonsConclusion and future works
3
Multiple Valued Logic (MVL)Currently, computers and other
electronic devices run as 101101… binary logic with 2 logical states: 0, 1
MVL can offer: Many logical states: 0, 1, 2, 3, … More complex functions
in less time, power and area than binary ?
MVL circuit structure ?
4
MVL Circuits StructuresCurrent-Mode CMOS Logic (CMCL) [3]Voltage-Mode nMOS technology [16]QCD or CCD technology [1][2]
Supplementary Symmetrical Logic Circuit Structure (SUS-LOC) [8][11] Voltage-Mode (i.e. CMOS) Energy Efficient A new promising structure
5
Technical advantages of SUS-LOC MVL circuits and devices
A decrease of passive parasitic values
A decrease in required power (dynamic and static)
Ability to perform multiple logic functions in one operation e.g. (A+B) AND D
Security, confidentiality
An increase in data density
Interconnections e.g. 40 bits become 25
terts1 (37.5% reduction), or 20 4L-digits
More bandwidth with a reduced clock rate 16 bits f 10 terts 1 Mbit/s 750 ktert/s
Reduced package size
1 terts stands for ternary digits
6
SUS-LOC structures Principle
Ternary case: radix r = 3 Logic states: {0,1,2}
r-1 different sources of power e.g. {0V, 1.25V, 2.5V}
r-1 independent controllable paths
SUS-LOC principleSUS-LOC principle
VHDL Performancemodeling
VHDL Performancemodeling
Transistor libraryTransistor library
CharacterizationProcess
CharacterizationProcess
Output
V0 V1 V2Inputs
N0 N1 N2
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SUS-LOC structuresExample: ternary inverter
Truth Table
N(x) = <2 1 0>
SUS-LOC principleSUS-LOC principle
VHDL Performancemodeling
VHDL Performancemodeling
Transistor libraryTransistor library
CharacterizationProcess
CharacterizationProcess
0
1
2
2
1
0
X S
F
02
11
2
0
8
MbreakPD
MbreakP
MbreakP+
MbreakND
MbreakN
MbreakN+
Id(Vgs)
Transistor LibraryUse of depleted and enhanced
MOS transistorsSPICE models
0.25 technolgy 2 SOI technolgy (UCL)
Vdd = 2.5V Vdd = 2VMbreakP+ -1.625 -1.3MbreakN+ 1.625 1.3MbreakP -0.375 -0.3MbreakN 0.375 0.3
MbreakPD 0.875 0.7MbreakND -0.875 -0.7
ENH
DEP
VTH (V)Transistor type
Mode
ENH
SUS-LOC principleSUS-LOC principle
VHDL Performancemodeling
VHDL Performancemodeling
Transistor libraryTransistor library
CharacterizationProcess
CharacterizationProcess
9
Logic FunctionsTernary CGAND
Complementing Generalized AND CGAND(X,Y) = N(MAX(x,y))
A 0 1 2
0 2 2 2
1 2 1 1
B
2 2 1 0
A
BSCGAND
3
SUS-LOC principleSUS-LOC principle
VHDL Performancemodeling
VHDL Performancemodeling
Transistor libraryTransistor library
CharacterizationProcess
CharacterizationProcess
10
A B S = 0 x = 2 x = 0 = 2
= 1 1 = 1 1 = 1 = 1 = 2 = 2 = 0
CGAND
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CGAND
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Transistor-level ValidationDelay and Power Characterization
Characterization
XCIRCUIT MVLStim
ELDO Hierarchicalnetlist
MVLCara Reportfile
SUS-LOC principleSUS-LOC principle
VHDL Performancemodeling
VHDL Performancemodeling
Transistor libraryTransistor library
CharacterizationProcess
CharacterizationProcess
13
Transistor-level Validation Delay and Power Characterization
e.g. Ternary vs Binary Inverter
Characterization
SUS-LOC principleSUS-LOC principle
VHDL Performancemodeling
VHDL Performancemodeling
Transistor libraryTransistor library
CharacterizationProcess
CharacterizationProcess
Input slope [ps] Input slope [ps]100 400 100 400
Binary HTL 66.9 675 168 272Binary LTL 69 90 62.8 117Ternary (0 to 2) 78.6 72.6 133 237Ternary (0 to 1) 29.3 30.6 138 176
Energy [fJ] Delay [ps]
14
Design of a ternary standard cell library
CGAND, CGOR, Inverters, …Mux, Tri-state LATCH, D Flip-FlopSRAM memory cell and sense amp.Arithmetic components
HA, Pi, Gi, CLA, multiplier 1T-Shifter
15
Gate-level VHDL package for simulation
STD_TERNARY_LOGIC
VHDL set of tools for architecture- and gate-level estimations Power, Delay Gate-level simulation
SUS-LOC principleSUS-LOC principle
VHDL Performancemodeling
VHDL Performancemodeling
Transistor libraryTransistor library
CharacterizationProcess
CharacterizationProcess
VHDL Package
ELDO simulationReport file
Description.vhd
VHDL Gate level simulation
Power consumption
Delay
16
Outline MotivationsMVL implementation with SUS-LOCDesign of a ternary DSP structureExperimental results and comparisonsConclusion and future works
17
A ternary vs. binary DSP
T register
DB
MUX MUX
Multiplier
Adder
MUX
MUX
A(H) B(H)
ALU
MUX MUX MUX
Barrel shifter
Legend : A Accumulator A B Accumulator B C CB data bus D DB data bus E EB data bus M MAC unit S Barrel shifter T T register U ALU
T D AA
C D
A B0
AM
U B
A B CT
D S
S
B
CB
EB L
L
L
N
H
H
H
H
H
E
Bus width : L : 16 bits, 10 terts N : 32 bits, 20 terts H : 40 bits, 25 terts
H
L
C DA
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InterconnectionsBus structure
16 bits become 10 terts 40 bits become 25 terts
Activity of wires Binary: Ternary:
102.. VddCE loadi
20
221
2
10
2
4
3
4αVddα
Vddα
Vdd.C'E loadi
19
SRAM MemoryTransistor equivalent, faster access timeUp to 50% in energy reduction
22
BINARY (40 bits) RCA CLA SKLANSKYDelay (ps) 19000 17308 4421Transistor cost 1440 2280 3680Consumption (nJ) 348.03 522.45 536.94TERNARY (25 terts) RCA CLA SKLANSKY
Delay (ps) 26250 21090 4675Transistor cost 2175 3375 4296Consumption (nJ) 399.72 486.66 190.40
Arithmetic structurese.g. 40-bit vs. 25-tert Sklansky Adder
100 vs. 54 Brent and Kung cells
24
Conclusion and future worksSUS-LOC concepts for a ternary DSP
Experiments on representative modules Comparison: SUS-LOC vs. CMOS circuits High energy efficiency
Future works Prototype chip with an SOI technology 3L and 4L SRAM and Flash memories Optimization of arithmetic structures …
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