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William Stallings Computer Organization and Architecture8th Edition

Chapter 10 & 11Instruction Sets

T1 10.1-10.5, 11.1-11.4R1- 2.2 (Memory Locations & Addresses), 2.5 (Addressing Modes)

Instruction Set • 10.1 Machine Instruction Characteristics• 10.2 Types of Operands• 10.3 Intel x86 Data Types• 10.4 Types of Operations• 10.5 Intel x86 Operation Types

• 11.1 Addressing• 11.2 x86 Addressing Modes• 11.3 Instruction Formats• 11.4 x86 Instruction Formats• Summary

Objectives • To program a computer in machine or

assembly language one must know about CPU registers, memory structure, supported data types, data access methods, operations supported by the ALU, and elements of the instructions & its size etc.

• The treatment is more generic but 8086 ISA can be use as an example.

What is an Instruction Set?• The complete collection of instructions

that are understood by a CPU• Machine Code• Binary• Usually represented by assembly codes

Elements of an Instruction• Operation code (Op code)

—Do this• Source Operand reference

—To this• Result Operand reference

—Put the answer here• Next Instruction Reference

—When you have done that, do this...

Instruction Representation• In machine code each instruction has a

unique bit pattern• For human consumption (well, programmers

anyway) a symbolic representation is used—e.g. ADD, SUB, LOAD

• Operands can also be represented in this way—ADD A,B

Simple Instruction Format

Instruction Types• Data processing• Data storage (main memory)• Data movement (I/O)• Program flow control

3-, 2-, 1-, & 0-Address

• The classification is based on arithmetic instructions that have no. of operands and one result

• 3-address instruction specifies memory addresses for both operands and the result R Op1 op Op2

• A 2-address instruction overwrites one operand in memory with the result Op2 Op1 op Op2

• A 1-address instruction has a processor, called the accumulator register, to hold one operand & the result Acc Acc op Op1

• A 0-address + uses a CPU register stack to hold both operands and the result TOS TOS op SOS

• The 4-address instruction, hardly ever seen, also allows the address of the next instruction to specified explicitly

3-Address Instruction Format

• 3 addresses—Operand 1, Operand 2, Result—a = b + c;—May be a forth - next instruction (usually implicit)—Not common—Needs very long words to hold everything

Memory

Op1Addr:Op2Addr:

Op1

Programcounter

Op2

ResAddr:

NextiAddr:

Bits: 8 24 24Instruction format

24

Res

Nexti

CPU

Where to findnext instruction

24

add, Res, Op1, Op2 (Res Op2 + Op1)

add ResAddr Op1Addr Op2AddrWhich

operationWhere toput result Where to find operands

2-Address Instruction Format• 2 addresses

—One address doubles as operand and result—a = a + b—Reduces length of instruction—Requires some extra work

– Temporary storage to hold some results

Memory

Op1Addr:

Op2Addr:

Op1

Programcounter

Op2,Res

NextiNextiAddr:

Bits: 8 24 24Instruction format

CPU

Where to findnext instruction

24

add Op2, Op1 (Op2 Op2 + Op1)

add Op2Addr Op1AddrWhich

operation

Where toput result

Where to find operands

1-Address Instruction Format

• 1 address—Implicit second address—Usually a register

(accumulator)—Common on early machines

Need instructions to load and store operands:LDA OpAddrSTA OpAddr

Memory

Op1Addr: Op1

NextiProgramcounter

Accumulator

NextiAddr:

Bits: 8 24Instruction format

CPU

Where to findnext instruction

24

add Op1 (Acc Acc + Op1)

add Op1AddrWhich

operationWhere to find

operand1

Where to find operand2, and

where to put result

0-Address or Stack Instruction Format

• 0 (zero) addresses—All addresses implicit—Uses a stack— Computer must have a 1-address instruction to push and pop operands to and from

the stack

Memory

Op1Addr:

TOSSOSetc.

Op1

Programcounter

NextiAddr: Nexti

Bits:

Format

Format

8 24

CPU

Where to findnext instruction

Stack

24

push Op1 (TOS Op1)

Instruction formats

add (TOS TOS + SOS)

push Op1AddrOperation

Bits: 8

addWhich operation

Result

Where to find operands, and where to put result

(on the stack)

e.g. push a push b add pop cc = a + b

Expression Evaluation for 3-, 2-, 1-, and 0-Address Machines

• Number of instructions & number of addresses both vary

• Discuss as examples: size of code in each case

3 - a d d r e s s 2 - a d d r e s s 1 - a d d r e s s S t a c kadd a, b, cmpy a, a, dsub a, a, e

load a, badd a, cmpy a, dsub a, e

load badd cmpy dsub estore a

push bpush caddpush dmpypush esubpop a

Evaluate a = (b+c)*d - e

Problems• Write 0-, 1-, 2- and 3- address machine

programs to compute X = (A+B*C) / (D-E*F).

• Write 0-, 1-, 2- and 3- address machine programs to compute ROOT = √ ((b2 -4ac)/2a)0 1 2 30start: PUSH A PUSH 2 MUL PUSH C PUSH A PUSH 4 MUL MUL PUSH B PUSH B MUL SUB DIV POP SQRT(ROOT) End

1Start: LOAD AMUL #2STORE T1LOAD #4MUL AMUL CSTORE T2LOAD BMUL BSUB T2DIV SQRTSTORE ROOTEnd

2Start: MUL B, BMOV T1, AMUL A, #4MUL A, CSUB B, AMUL T1, #2DIV B, T1SQRT B, BMOV ROOT, B End 

3Start: MUL T1, B, BMUL T2, A, CMUL T3, T2, #4 MUL T4, A, #2SUB T5, T1, T3DIV T6, T5, T4SQRT ROOT, T6End

How Many Addresses• More addresses

—More complex (powerful?) instructions—More registers

– Inter-register operations are quicker—Fewer instructions per program

• Fewer addresses—Less complex (powerful?) instructions—More instructions per program—Faster fetch/execution of instructions

Design Decisions• Operation repertoire

—How many ops?—What can they do?—How complex are they?

• Data types• Instruction formats

—Length of op code field—Number of addresses

• Registers—Number of CPU registers available—Which operations can be performed on which registers?

• Addressing modes (later…)

• RISC v CISC

Types of Operand• Addresses• Numbers

—Integer/floating point• Characters

—ASCII etc.• Logical Data

—Bits or flags• (Aside: Is there any difference between numbers and

characters? Ask a C programmer!)

x86 Data Types• 8 bit Byte• 16 bit word• 32 bit double word• 64 bit quad word• 128 bit double quadword• Addressing is by 8 bit unit• Words do not need to align at even-

numbered address• Data accessed across 32 bit bus in units of

double word read at addresses divisible by 4

• Little endian

SIMD Data Types• Integer types

— Interpreted as bit field or integer

• Packed byte and packed byte integer— Bytes packed into 64-bit quadword or 128-bit double

quadword• Packed word and packed word integer

— 16-bit words packed into 64-bit quadword or 128-bit double quadword

• Packed doubleword and packed doubleword integer— 32-bit doublewords packed into 64-bit quadword or 128-bit

double quadword• Packed quadword and packed qaudword integer

— Two 64-bit quadwords packed into 128-bit double quadword

• Packed single-precision floating-point and packed double-precision floating-point— Four 32-bit floating-point or two 64-bit floating-point values

packed into a 128-bit double quadword

x86 Numeric Data Formats

Types of Operation• Data Transfer• Arithmetic• Logical• Conversion• I/O• System Control• Transfer of Control

Data Transfer• Specify

—Source—Destination—Amount of data

• May be different instructions for different movements—e.g. IBM 370

• Or one instruction and different addresses—e.g. VAX

Arithmetic• Add, Subtract, Multiply, Divide• Signed Integer• Floating point ?• May include

—Increment (a++)—Decrement (a--)—Negate (-a)

Shift and Rotate Operations

Logical• Bitwise operations• AND, OR, NOT

Input/Output• May be specific instructions• May be done using data movement

instructions (memory mapped)• May be done by a separate controller

(DMA)

Systems Control• Privileged instructions• CPU needs to be in specific state

—Ring 0 on 80386+—Kernel mode

• For operating systems use

Transfer of Control• Branch

—e.g. branch to x if result is zero• Skip

—e.g. increment and skip if zero—ISZ Register1—Branch xxxx—ADD A

• Subroutine call—c.f. interrupt call

Branch Instruction

Nested Procedure Calls

Use of Stack

Stack Frame Growth Using Sample Procedures P and Q

Byte Order (A portion of chips?)• What order do we read numbers that

occupy more than one byte• e.g. (numbers in hex to make it easy to

read)• 12345678 can be stored in 4x8bit

locations as follows

• i.e. read top down or bottom up?

Address Value (1) Value (2)184 12 78185 34 56186 56 34187 78 12

Byte Order Names• The problem is called Endian• The system on the left has the least

significant byte in the lowest address• This is called big-endian• The system on the right has the least

significant byte in the highest address• This is called little-endian

Example of C Data Structure

Standard…What Standard?• Pentium (x86), VAX are

little-endian• IBM 370, Moterola 680x0

(Mac), and most RISC are big-endian

• Internet is big-endian—Makes writing Internet

programs on PC more awkward!

—WinSock provides htoi and itoh (Host to Internet & Internet to Host) functions to convert

Alternative View of Memory Map

Addressing Modes• Immediate• Direct• Indirect• Register• Register Indirect• Displacement (Indexed) • Stack

Immediate Addressing• Operand is part of instruction• Operand = address field• e.g. ADD 5

—Add 5 to contents of accumulator—5 is operand

• No memory reference to fetch data• Fast• Limited range

OperandOpcode

Instruction

Direct Addressing• Address field contains address

of operand• Effective address (EA) = address

field (A)• e.g. ADD A

—Add contents of cell A to accumulator

—Look in memory at address A for operand

• Single memory reference to access data

• No additional calculations to work out effective address

• Limited address space

Address AOpcode

Instruction

Memory

Operand

Indirect Addressing• Memory cell pointed to by address field

contains the address of (pointer to) the operand

• EA = (A)—Look in A, find address (A) and look there for

operand• e.g. ADD (A)

—Add contents of cell pointed to by contents of A to accumulator

Indirect Addressing Diagram

Address AOpcode

Instruction

Memory

Operand

Pointer to operand• Large address space • 2n where n = word length• May be nested, multilevel,

cascaded—e.g. EA = (((A)))

– Draw the diagram yourself• Multiple memory accesses

to find operand• Hence slower

Register Addressing• Operand is held in register named in

address filed• EA = R• Limited number of registers• Very small address field needed

—Shorter instructions—Faster instruction fetch

Register Addressing Diagram

Register Address ROpcode

Instruction

Registers

Operand

• No memory access• Very fast execution• Very limited address space• Multiple registers helps

performance—Requires good assembly

programming or compiler writing—N.B. C programming

– register int a;• c.f. Direct addressing

Register Indirect Addressing

Register Address ROpcode

Instruction

Memory

OperandPointer to Operand

Registers

• C.f. indirect addressing

• EA = (R)• Operand is in

memory pointed to by contents of register R

• Large address space (2n)

• One fewer memory access than indirect addressing

Displacement Addressing

Register ROpcode

InstructionMemory

OperandPointer to Operand

Registers

Address A

+

• EA = A + (R)• Address field hold two values

—A = base value—R = register that holds displacement—or vice versa

Relative Addressing• A version of displacement addressing• R = Program counter, PC• EA = A + (PC)• i.e. get operand from A cells from current

location pointed to by PC• c.f locality of reference & cache usage

Base-Register Addressing• A holds displacement• R holds pointer to base address• R may be explicit or implicit• e.g. segment registers in 80x86

Indexed Addressing• A = base• R = displacement• EA = A + R• Good for accessing arrays

—EA = A + R—R++

Combinations• Postindex• EA = (A) + (R)

• Preindex• EA = (A+(R))

• (Draw the diagrams)

Stack Addressing• Operand is (implicitly) on top of stack• e.g.

—ADD Pop top two items from stackand add

x86 Addressing Modes• Virtual or effective address is offset into segment

—Starting address plus offset gives linear address—This goes through page translation if paging enabled

• 12 addressing modes available—Immediate—Register operand—Displacement—Base—Base with displacement—Scaled index with displacement—Base with index and displacement—Base scaled index with displacement—Relative

x86 Addressing Mode Calculation

Logical to Physical Address CalculationThe 8086 microprocessor has 20-bit address lines. All the registers in 8086 are 16-bits in length. Hence to obtain 20-bit addresses from the available 16-bit registers, all 8086 memory addresses are computed by summing the contents of a segment register and a effective memory address.1. Given that the EA of a datum is 2359 H and the DS = 490B H, what is the physical address of the datum?

DS: 490B0 HEA: 2359 H Physical add. 4B409

2. If a physical branch address is 5A230 H when (CS) = 5200 H, what will be PA if the (CS) are changed to 7800 H.

CS: 52 0 0 EA: XXXX Physical add. 5A2 3 0 H

Hence EA = Physical add - (Segment address displaced by 4-bits) EA = 5A230 - 52000 = 8230 H If the CS is changed to 7800 H the Physical address will be 78000 + 8230 = 80230

Instruction Formats• Layout of bits in an instruction• Includes opcode• Includes (implicit or explicit) operand(s)• Usually more than one instruction format

in an instruction set

Instruction Length• Affected by and affects:

—Memory size—Memory organization—Bus structure—CPU complexity—CPU speed

• Trade off between powerful instruction repertoire and saving space

Allocation of Bits• Number of addressing modes• Number of operands• Register versus memory• Number of register sets• Address range• Address granularity

x86 Instruction Format

Summary • Machine Instruction Characteristics• Types of Operands• Intel x86 Data Types• Types of Operations• Intel x86 Operation Types• Addressing• x86 Addressing Modes• Instruction Formats• x86 Instruction Formats