chapter 8 test standards - ncu
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Chapter 8Test Standards
Jin-Fu LiDepartment of Electrical EngineeringNational Central UniversityJungli, Taiwan
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 2
1149.1 standard for system-on-board 1500 standard for system-on-chip
Outline
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 3
Overview System-on-Board System-on-Chip
1149.1
1500
System-on-Chip
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 4
• Purpose of the standard Let test instructions and test data be serially
fed into a component-under-test (CUT) JTAG can operate at chip, PCB, & system
levels Let system interconnect be tested separately
from components Let components be tested separately from
wires
1149.1 (JTAG) Standard
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 5
System Test Logic
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 6
Instruction Register Loading
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 7
System View of Interconnect
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 8
Boundary Scan Chain View
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 9
Elementary Boundary Scan Cell
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 10
Serial Board/MCM Scan
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 11
Parallel Board/MCM Scan
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 12
Independent Board/MCM Scan
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 13
• Test Access Port (TAP) includes these signals: Test Clock Input (TCK) -- Clock for test logic
Can run at different rate from system clock Test Mode Select (TMS) -- Switches system from
functional to test mode Test Data Input (TDI) -- Accepts serial test data and
instructions -- used to shift in vectors or one of many test instructions
Test Data Output (TDO) -- Serially shifts out test results captured in boundary scan chain (or device ID or other internal registers)
Test Reset (TRST) -- Optional asynchronous TAP controller reset
Signals of the TAP Controller
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 14
State Diagram of the TAP Controller
Load InstructionTest Application
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 15
Purpose: bypasses scan chain with 1-bit register
Mandatory Instruction – Bypass
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 16
Mandatory Instruction – Sample/Preload
Purpose: Get snapshot of normal chip output signals (Sample)
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 17
Mandatory Instruction – Sample/Preload
Purpose: Put data on boundary scan chain before next instruction (Preload)
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 18
Mandatory Instruction – Extest Purpose : Test off-chip circuits and board-level
interconnections
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 19
Mandatory Instruction – Intest Purpose :
Shifts external test patterns onto component External tester shifts component responses out
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 20
Advances in IC design methods and manufacturing technologies allow to integrate complete systems onto a single IC, called system on chip (SOC)
Compared with traditional multi-chip equivalents, SOC offers advantages such as Higher performance, lower power consumption, and
smaller volume and weight Many SOCs are designed by embedding large
reusable building blocks, called cores Design reuse speeds up the design and allows
import of external expertise
System On Chip
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 21
Design reuse becomes an indispensable condition to the design productivity optimization
The same is valid for efficient test of non-mergeable cores, because this would require test reuse
The test of these cores can become a challenge, with various types of difficulties including automation and test plug-and-play
A core-level solution to facilitate test integration and test reuse is required Standardization
Test Reuse
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 22
1500 Test Wrapper
Core
WBY
WIR
WB
R
WB
R
WSC
Functional data
Test stimuli
Functional data
Test response
WSOWSI
WPI WPO
Source: Y. Zorian, et al.-JETTA2002
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 23
1500 Wrapper Component
Wrapper Instruction Register (WIR) Controls operation of Wrapper Controlled directly from WIP signals Instruction loaded via WSI-WSO
Wrapper Bypass Register (WBY) Mandatory bypass for serial TAM (between
WSI-WSO) Wrapper Boundary Register (WBR) Controllability/obervability on core terminals Test data loaded from WSI-WSO or WPI-WPO Built from library of wrapper cells
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 24
Wrapper Interface Ports [Y. Zorian, et al.,ITC03]
Core
Wrapper
WPI
WPC
WPO
WSI WSO
WSC
WrapperParallel Input
WrapperParallel Output
WrapperParallel Control
WrapperSerial Input
WrapperSerial Control
WrapperSerial Output
Optional WrapperParallel Port (WPP)
Standardized Portfor Plug & Play
User Defined Portfor Test Flexibility
Required WrapperSerial Port (WSP)
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 25
Wrapper Interface Ports Functional I/Os
Core’s functional inputs/outputs
Wrapper Serial Control (WSC) A 7-bit control port for WIR and Wrapper
Wrapper Serial Port (WSP) Mandatory serial interface is used for two purposes
Wrapper control: loading instructions into the WIR Low-bandwidth test data access to WBR
Wrapper Parallel Control (WPC) User defined port for test flexibility
Wrapper Parallel Port (WPP) Optional parallel interface is used for test data access to
WBR with user-defined, scalable bandwidth
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 26
Wrapper Operation Modes
Core Normal Mode Core Test Mode (Internal test) Core Interconnection Test Mode (External
test) Core Isolation Mode
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 27
Wrapper Serial Control (WSC) WSC functions:
Control the operation of the WIR Control together with the WIR instruction the
operation of the wrapper
Core
WRSTWCLK
SelectWRCapture
ShiftUpdate
Transfer
WSCControls& Clock
Wrapper
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 28
WSC Signals
WRST
WCLK
SelectWR
Capture
Shift
Update
Transfer
“Wrapper clock”, dedicated P1500 clock signalfor WIR, WBY, and WBR
“Wrapper reset”, dedicated P1500 reset signalfor WIR
Select WIR as register between WSI-WSO
Enable shift operation for selected register
Enable capture operation for selected register
Enable update operation for selected register
Enable transfer operation for selected register
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 29
Serial Interface Layer (SIL) SIL architecture
WBR
CDR 1-N
Bypass
WIR
GnG1
WSI
WSC
SelectWIR
WSO
Core DataRegisters
WDRs
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 30
An Example of Wrapper Cell
SEshift
wclk
cti
cfi
Shift Normal
cfo
cto
Mode: Normal mode: normal=1Shift mode : shift=1
Controllability: normal=>value in SE is driven onto CFOObservability: shift=>value at CFO is captured into SE
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 31
Wrapper Instruction Set [Y. Zorian, et al.,JETTA02]
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 32
Wrapper in Normal Mode [Y. Zorian, et al.,JETTA02]
Scan chain 0
Scan chain 1
m8
m7
m6
m11
m12
m9
m10
m1
m2
m3
m5
m6
Coreq[0]
q[1]
q[2]
d[0]
d[1]d[2]
d[3]d[4]
sc clk
WIP
WBY
WIR
WPI[2:0]WPO[2:0]
WSIWSO
SelectWIR
d[0]
d[1]d[2]
d[3]d[4]
q[0]
q[1]
q[2]
Wrapper
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 33
Wrapper in Bypass Mode [Y. Zorian, et al.,JETTA02]
Scan chain 0
Scan chain 1
m8
m7
m6
m11
m12
m9
m10
m1
m2
m3
m5
m6
Coreq[0]
q[1]
q[2]
d[0]
d[1]d[2]
d[3]d[4]
sc clk
WIP
WBY
WIR
WPI[2:0]WPO[2:0]
WSIWSO
SelectWIR
d[0]
d[1]d[2]
d[3]d[4]
q[0]
q[1]
q[2]
Wrapper
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 34
Wrapper in WCoreTestS [Y. Zorian, et al.,JETTA02]
Scan chain 0
Scan chain 1
m8
m7
m6
m11
m12
m9
m10
m1
m2
m3
m5
m6
Coreq[0]
q[1]
q[2]
d[0]
d[1]d[2]
d[3]d[4]
sc clk
WIP
WBY
WIR
WPI[2:0]WPO[2:0]
WSIWSO
SelectWIR
d[0]
d[1]d[2]
d[3]d[4]
q[0]
q[1]
q[2]
Wrapper
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 35
Wrapper in WExTestS [Y. Zorian, et al.,JETTA02]
Scan chain 0
Scan chain 1
m8
m7
m6
m11
m12
m9
m10
m1
m2
m3
m5
m6
Coreq[0]
q[1]
q[2]
d[0]
d[1]d[2]
d[3]d[4]
sc clk
WIP
WBY
WIR
WPI[2:0]WPO[2:0]
WSIWSO
SelectWIR
d[0]
d[1]d[2]
d[3]d[4]
q[0]
q[1]
q[2]
Wrapper
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 36
Wrapper in WCoreTest [Y. Zorian, et al.,JETTA02]
Scan chain 0
Scan chain 1
m8
m7
m6
m11
m12
m9
m10
m1
m2
m3
m5
m6
Coreq[0]
q[1]
q[2]
d[0]
d[1]d[2]
d[3]d[4]
sc clk
WIP
WBY
WIR
WPI[2:0]WPO[2:0]
WSIWSO
SelectWIR
d[0]
d[1]d[2]
d[3]d[4]
q[0]
q[1]
q[2]
Wrapper
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 37
Wrapper in WExTestP [Y. Zorian, et al.,JETTA02]
Scan chain 0
Scan chain 1
m8
m7
m6
m11
m12
m9
m10
m1
m2
m3
m5
m6
Coreq[0]
q[1]
q[2]
d[0]
d[1]d[2]
d[3]d[4]
sc clk
WIP
WBY
WIR
WPI[2:0]WPO[2:0]
WSIWSO
SelectWIR
d[0]
d[1]d[2]
d[3]d[4]
q[0]
q[1]
q[2]
Wrapper
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