automated risc-v verification flow for the connected world your application is unique, so why...

PROCESSORS FOR THE CONNECTED WORLDYour application is unique, so why isn’t your processor?

AUTOMATED RISC-V VERIFICATION FLOWUtilizing Simulation, Formal, and Emulation Technologies

FLEXIBLE RISC-V ISA�1 RISC-V ISA standard ð many RISC-V HW architecture variants:�Base is only integer instruction set ("I /E")�Can be enhanced by standard extensions: integer multiplication and division

("M"), atomic instructions for handling real-time concurrency ("A"), IEEE floating point ("F") with double-precision ("D") and quad-precision ("Q")�Can have compressed instructions (“C")�Can have different number of the registers (16 or 32) of different sizes (32 or 64

bits).

�We do not verify only 1 processor but many of its variants with enabled/disabled extensions!

OVERVIEW�Codix Berkelium processors from Codasip

�Automated generation of SDK, tests, RTL, UVM by Codasip Studio

�Mentor formal, simulation, VIP, emulation tools

�Resulting productivity

CODIX CORES

CODIX BK3 – IP VARIANTS

I

E

I

E

M

I

E

C

I

E

C

M

Bk3

Standard ISA:I = integer ISA, 32 GPRsE = integer ISA, 16 GPRsM = multiplication extensionC = compressed instructions

Codasip HW extensions:U = user mode with memory protectionP = parallel multiplier/dividerj = branch predictiond = JTAG debug

CODIX BK5 – IP VARIANTS

I

E

I

E

M

I

E

F

I

E

F

M

Bk5

Standard ISA:I = integer ISA, 32 GPRsE = integer ISA, 16 GPRsM = multiplication extensionF = floating-point ISA

Codasip HW extensions:U = user mode with memory protectiond = JTAG debug

UNIQUE AUTOMATION TECHNOLOGY

Processor Modeling Software analysis SDK Synthesis RTL Synthesis Verification

Berkelium Microarchitecture

Codix Cycle Accurate Models Codix RTL ModelsCA Simulator, Profiler, Debugger

Application(s)/Programs(s)

C/C++ Compiler

Assembler

Linker

IA Simulator, Profiler, DebuggerCodix InstructionAccurate Models

Codix CodAL Models

RISC-V Instruction Set

UNIQUE AUTOMATION TECHNOLOGY

Processor Modeling Software analysis SDK Synthesis RTL Synthesis Verification

Berkelium Microarchitecture

Codix Cycle Accurate Models Codix RTL ModelsCA Simulator, Profiler, Debugger

Application(s)/Programs(s)

C/C++ Compiler

Assembler

Linker

IA Simulator, Profiler, DebuggerCodix InstructionAccurate Models

Codix CodAL Models

RISC-V Instruction SetReference Models

UVM Verification

MORE VERIFICATION, BETTER PRODUCTS

RTL and Questa Autocheck

Verification Plan and Questa VRM

UVM and Questa Sim + Questa VIP

Regressions and Veloce Emulation

RTL and Questa Autocheck

Verification Plan and Questa VRM

UVM and Questa Sim + Questa VIP

Regressions and Veloce Emulation

RTL and Questa Autocheck

Verification Plan and Questa VRM

UVM and Questa Sim + Questa VIP

Regressions and Veloce Emulation

RTL and Questa Autocheck

Verification Plan and Questa VRM

UVM and Questa Sim + Questa VIP

Regressions and Veloce Emulation

RTL and Questa Autocheck

Verification Plan and Questa VRM

UVM and Questa Sim + Questa VIP

Regressions and Veloce Emulation

0:01:31

2:06:55

21:08:11

0:01:52 0:33:13

5:17:35

0:00:00

2:24:00

4:48:00

7:12:00

9:36:00

12:00:00

14:24:00

16:48:00

19:12:00

21:36:00

0:00:00

Totaltestingtimefor1randomprogram

Totaltestingtimefor100randomprograms

Totaltestingtimefor1000randomprograms

Time[h:m:s]

Totaltestingtimefor1,100and1000programs

Simulator(QuestaSim) Emulator(Veloce)

0:00:15

0:01:16

0:01:33

0:00:19

0:00:00

0:00:17

0:00:35

0:00:52

0:01:09

0:01:26

0:01:44

CompilationofRTLfiles Simulation/emulationof1randomprogram(~100000instructions)

Time[hh:mm:ss]

Maindifferencesbetweensimulationandemulation

Simulator(QuestaSim) Emulator(Veloce)

Comparisonoftotaltimeneededfortesting

(differenttimescale!)

SHORTENING DEVELOPMENT TIME

0

50

100

150

200

250

300

350

400

450

500

550

600

ADLprocessormodel SDK RTL UVMenvironment ISAtests Micro-architecturaltests

Verificationanddebugging

Man-days

Sub-variant/Extension-variantofRISC-Vcore+acceleratedverification(reuse)

InitialdevelopmentflowbyCodasip+fullverification

StandardRISC-Vprocessordevelopmentflow

125 days

570days

30days

SUMMARY�When we want to make RISC-V successful, strength is in maximizing

automation in generating RTL and verification!

�Codasip automates most processes from single high-level description, including RTL, SDK and UVM generation

�Long-term partnership with Mentor increases quality of Berkelium cores every day J

�

� ¬

Thank you for your attention!

zachariasova@codasip.com, Shakeel_Jeeawoody@mentor.com+420 541 141 475 (CZE) www.codasip.com, www.mentor.com