aug-151 浅谈多核处理器与系统软件研发 -- 实例研究 : 思科 quantumflow...
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04/19/23 1
浅谈多核处理器与系统软件研发
-- 实例研究 : 思科 QuantumFlow 处理器与系统软件结构
陈怀临《弯曲评论》
www.tektalk.cn
04/19/23 2
× 《弯曲评论》
× 系统软件
× 工业动态
× 系统理解
× 实例研究:思科 QuantumFlow
× 结束语
提纲
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× 目标:非盈利性智库机构
× 领域:× 科技跟踪
× 专题分析
× 人物报道
× 学术打假
《弯曲评论》( www.tektalk.cn )
04/19/23 4
最近工作总结: × 专题分析
《思科 Quantum 处理器与战略研究》
《对中国系统软件的思考与建议》
《对华为系统软件的战略思考(上)》
《对华为系统软件的战略思考(下)》
《《对国防科大麒麟操作系统研发的思考》
《中国计算机发展史略 (1956-2006) 》
《弯曲评论》( www.tektalk.cn )
04/19/23 5
最近工作总结: × 科技书籍:
《 PowerPC and Linux Kernel Inside 》
《 Linux 核 心》( The Linux Kernel) (下)
《 Linux 核 心》( The Linux Kernel) (中)
《 Linux 核 心》( The Linux Kernel) (上)
《 MIPS CPU 体系结构概述, Linux/MIPS 内核》(下)
《 MIPS CPU 体系结构概述, Linux/MIPS 内核》(上)
《 See MIPS Run 》
《弯曲评论》( www.tektalk.cn )
04/19/23 6
最近工作总结:
× 人物评述:
《邓稼先传》
《海外学人》
《计算的美丽 - 图灵奖的第一个四十年》(上)
《计算的美丽 - 图灵奖的第一个四十年》(下)
《弯曲评论》( www.tektalk.cn )
04/19/23 7
× 操作系统× 桌面操作系统× 服务器操作系统× 嵌入式操作系统
× 编译器与工具链( gcc, binutil, gdb…)
× 编程环境,中间件×PVM , MPI , OpenMP×Mapreduce , Hadoop×CORBA , DCOM
系统软件
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× 嵌入式操作系统
- 传统分时系统: Linux , FreeBSD
- 微内核: QNX/Neutrino , L4 , Mach
- 大型通信操作系统:—华为 /VRP— 思科 /IOS , IOS-XR , IOS-XE
系统软件
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通信业工业研发动态
× 多核系统的持续应用
× 多核系统的多样化
×微观分布式并行计算系统
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工业动态
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× 系统( System )与操作系统( Operating System),核心( Kernel) 的关系
×计算单元的多样化( ASIC , FPGA , CPU , NP)
×互连网络的多样化( Bus , Switch Fabric , Interconnect )
×数据报文( Packet )驱动,调度。
×中断,异常处理的简化
×性能的考量,牺牲层次性和透明性
系统理解
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实例研究:思科 QuantumFlow
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实例研究:思科 QuantumFlow
× 项目启动时间: 2002 年 Q3 或 Q4 【笔者注: SPP 是 2002 年流片的。 CRS-1是 2004 年推出的。】× 研发耗资: 1 亿美金× 芯片主要定位:边缘( Edge )路由器,企业路由器。× 芯片解决问题: Stateful Service 与转发( Forwarding) 合一。 × 首发系统: ASR1000× 主频: 1.2GHZ 【笔者注: ESP-5G:900MHz. ESP-10G:900MHz.ESP-20G:1.2GHz 】× 晶体管数目: 8 亿× ( PFE )内存: DDR2 。 × 数据报文内存( Packet Buffer ): ESP-5G:64M.ESP-10G:128M.ESP-20G:256m*CAM: 外挂 TCAM 【笔者注: ESP-5G:10M. ESP-10G:10M.ESP-20G:40M 】× 功耗: 80 瓦× 多核: 40 , 4 Way-Thread 。来自 Tensica 的 Xtensa 。× 片内互联( Interconnect ): Crossbar Switch× 片外互联: ESI 【笔者注:在将来的新 QFPzhong ,将是 Interlaken 】× 数据报文接口: 4 个 10GBPS SPI4.2 。× 工艺: 90nm× 流片:德州仪器
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实例研究:思科 QuantumFlow
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实例研究:思科 QuantumFlow
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实例研究:思科 QuantumFlow
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实例研究:思科 QuantumFlow
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实例研究:思科 QuantumFlow
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实例研究:思科 QuantumFlow
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实例研究:思科 QuantumFlow
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实例研究:思科 QuantumFlow
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SPA Slots
# of ESP Slots# of RP Slots# of SIP SlotsIOS RedundancyBuilt in GigEHeightBandwidthPerformanceAir FlowPower Supply (Watts)
3-slot1
Integrated (RP1)Integrated (SIP10)
S/W4
3.5” (2RU)5-10 Gbps4-8 Mpps
Front to Back470
8-slot112
S/Wn/a
7” (4RU)10-40+ Gbps8-16+ Mpps
Front to Back765
12-slot223
H/Wn/a
10.5” (6RU)10-40+ Gbps8-16+ Mpps
Front to Back1275
Aggregated Services & ScaleAggregated Services & Scale
2 RU2 RU
4 RU4 RU
6 RU6 RUCisco ASR 1000 Series
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ASR1000 ILT – Naming
CPP = Cisco Packet Processor now known as the QuantumFlow Processor (QFP)
CC = CarrierCard now known as the SPA Interface Processor (SIP)
FP = Forwarding Processor now known as the Embedded Services Processor (ESP)
FRU = Field Replaceable Unit
RP = Route Processor
IOSd = IOS daemon, IOS process running on RP
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Chassis Options: ASR1006
RP1 (in slots “r0” & “r1”)
ESP10
SIP10
SPAs
Rack Mounts and Cable Mgt not shown
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System Architecture - Dataplane
Route Processor (standby)
RP
Interconn.
Embedded ServicesProcessor
(active)
FECP
Interconn.
SP
I4.2
CPP subsys-
temCrypto assist
Embedded ServicesProcessor(standby)
FECP
Interconn.
SP
I4.2
CPP subsys-
temCrypto assist
SPASPA
IOCPSPA
Agg.
…
Interconn.
SPASPA
IOCPSPA
Agg.
…
Interconn.
SPASPA
IOCPSPA
Agg.
…
Interconn.
Midplane
Route Processor
(active)
RP
Interconn.
SPA-SPI, 11.2GbpsHypertransport, 10Gbps
ESI, 11.5Gbps
• All data forwarding is through FP
• Exception: Punt path for Legacy protocols – handled by the RP
• Interconnect ASIC in each of the functional elements provides the backplane connection through ESI links
• ESI (Enhanced Services Interface) links are used for Data forwarding
• SPA-SPI links connect to the backplane through the SPA-Agg ASIC
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DDR2-500 SDRAM
MiniDIMM
2.5” Hard disk or
Solid-state drive
USB Interface
USB 2.0 controller
Stratum-3 Network clock circuit
Console and Aux
DDR2-500 SDRAM
MiniDIMM
Mgmt ENET
FP1FP0
GE Switch
4 CC’s FP0 FP1
Output clocks
Other RP
I2C Mux
bootflash :
1GB
(Bulk Storage, NVRAM)
Temp Sensor
Power Ctlr
EEPROM
RTC
USB
PowerPC CPU(SC854x SOC PowerQUICC III)
Interconn.
SIPs ESPs RP SIPs ESPs RPESPsMisc.Ctrl
SATA controller
nvarm: 32MB x 2
(part of bootflash: device)
BITS
SIPs SIPs
In ref clocks
RP
RP1 Block Diagram
GE, 1Gbps
I2C Inter-IC
SPA Control
SPA Bus
ESI, 11.2Gbps
SPA-SPI, 11.2Gbps
Hypertransport, 10Gbps
Other
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ESP10 Block Diagram
GE, 1Gbps
I2C
SPA Control
SPA Bus
ESI, 11.2Gbps
SPA-SPI, 11.2Gbps
Hypertransport, 10Gbps
Other
FECP
(SC854x SOC
PowerQUICC III)
Temp Sensor
Power Ctlr
EEPROM
Boot Flash (OBFL, …)
JTAG Ctrl
DDR2-500 SDRAM
MiniDIMM
Interconn.Interconn.
Reset / Pwr Ctrl
Pkt Buffer DRAM
(128MB)
Part Len/ BW
SRAM
Resource DRAM
(512MB)
SPI MuxCrypto
RPs RPs RPsESP SIPs
TCAM4 (10Mbit)
E-RP*PCI*
E-CSR
SA table DRAM
Processor pool
PPE0PPE0PPE0PPE1
PPE0PPE0PPE0PPE6
PPE0PPE0PPE0PPE2
PPE0PPE0PPE0PPE5
PPE0PPE0PPE0PPE3
… PPE0PPE0PPE0PPE40
PPE0PPE0PPE0PPE4
Buffer, queue, schedule (BQS)
QFP
Buffer, queue, schedule (BQS)
Buffer, queue, schedule (BQS)
Dispatcher/Pkt Buffer
ASR System BWASR System BW
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SIP10 Block Diagram
IOCP
(SC854x SOC)
Temp Sensor
Power Ctlr
EEPROM
Boot Flash (OBFL, …)
JTAG Ctrl
DDR2-500 SDRAM
MiniDIMM
Reset / Pwr Ctrl
RPs RPs
Interconn.
Ingress classifier
Ingress Scheduler
Egress Buffer Status
GE, 1Gbps
I2C
SPA Control
SPA Bus
ESI, 11.2Gbps
SPA-SPI, 11.2Gbps
Hypertransport, 10Gbps
Other
4 SPAs 4 SPAs
…
Ingress Buffers (per port)
…
Egress Buffers (per port)
ESPs
4 SPAs
C2W
EV-FC
EV-RP
Network clock
distribution
In ref clocks
Network clocks
4 SPAs 4 SPAs
RPs RPs
SPA Agg.
SPA Aggregation
ASIC
SPA Aggregation
ASIC
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IOS-XE
IOS XE Virtual Machine
IOS Upgrade
ASR 1002 & 1004 (No HW Redundancy)
Zero Packet Loss
IOS Upgrade
Zero Packet Loss
IOS Upgrade
ISSU ISSUIOS XE
Virtual MachineIOS XE
Virtual Machine
IOS Active
IOS Standby
IOS Active
IOS Standby
IOS Standby
IOS Active
Step 1
Step 2
Software Virtualization
Industry first, delivering hitless upgrades without costly hardware redundancy
Capable of broad scope of services: SP and enterprise, hosted or managed
Decreases OpEx, increases return on training investment
Feature Benefit
Combines rich edge feature set of IOS
Provides IOS command line, common look and feel for transparency to operator
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Software Architecture – IOS XE
Embedded Services Processor
Route Processor
SPA Interface Processor
Control Messaging
Kernel Kernel
Kernel
QFPClient/Driver
IOS XE = IOS + IOS XE Middleware + Platform Software
Operational Consistency - same look and feel as IOS Router
IOS runs as its own Linux process for control plane (Routing, SNMP, CLI etc). Capable of 64bit operation.
Linux kernel with multiple processes running in protected memory for
– Fault containment
– Re-startability
– ISSU of individual SW packages
ASR 1000 HA Innovations
– Zero-packet-loss RP Failover
– <50ms ESP Failover
– “Software Redundancy”
Chassis Chassis ManagerManager
InterfaceInterfaceManagerManager
ForwardingForwardingManagerManager
SPADriver
SPADriver
SPADriver
SPADriver
IOS
(Standby)
ForwardingForwarding ManagerManager
ChassisChassis ManagerManager
IOS
(Active)
IOS XE Platform Adaptation Layer (PAL)
InterfaceInterface ManagerManager
ChassisChassis ManagerManager
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Software Architecture – IOS XE
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Software Architecture – IOS XE
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Software Architecture – IOS XE
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Software Architecture – IOS XE
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Software Architecture – IOS XE
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Software Architecture – IOS XE
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Software Architecture – IOS XE
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结束语
谢谢大家!
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