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Volume 92, Number 6, November-December 1987 Journal of Research of the National Bureau of Standards
A Low Noise Cascode Amplifier
Volume 92 Number 6 November-December 1987
Steven R. Jefferts
Joint Institute for Laboratory Astrophysics
We describe the design, schematics, and performance of a very low noise FET cascode input amplifier. This ampli-
Key words: cascode amplifier; low bias current amplifier; low noise FET amplifier; noise analysis; noise current; noise voltage.
University of Colorado and National Bureau of Standards Boulder, CO 80309
and
fier has noise performance of less than 1.2 nV IVHz and 0.25 fA;VHz over the 500 Hz to 50 kHz frequency range. The amplifier is presently being used in conjunction with a Penning ion trap but is applicable to a wide variety of uses requiring low noise gain in the I Hz to 30 MHz frequency range,
F. L. Walls National Bureau of Standards Boulder, CO 80303
Introduction
A low noise amplifier has been designed using a 2SKI17 N channel J-FET as the input device in a cascode [1] configuration. Noise measurements on this amplifier yield a low frequency noise current of 0.25 fA/YHz and a voltage noise of less than 1.2 nV /YHz in the 500 Hz to 50 kHz region. Bloyet et al. [2] suggest a figure of merit of the product of the noise voltage and current as being appropriate for amplifiers of this type. This amplifier has a figure of merit of - 3 X lO-H W 1Hz, which is almost two orders of magnitude smaller than other amplifiers reported elsewhere. [2]
The amplifier described here is presently being used in conjunction with a Penning trap to detect small image currents ( -0.01 pA) induced by ion motion in the trap. [3] This amplifier also appears to be well suited for use in noise thermometry experiments. [4]
383
Accepted: June 8, 1987
This paper discusses some general design criteria for cascade amplifiers and draws some conclusions concerning the optimum choice of FETs for such amplifiers. A particular design having the noise performance described above is presented and anaIyzed. Variations of the design which either have much larger bandwidth, 30 MHz, or draw extremely low input bias current, less than 0.01 pA, are briefly discussed.
Equivalent Circuit for Noise Analysis
The schematic of the amplifier is shown in figure 1. The biasing scheme used for Q2, the common base portion of the cascode, is attractive for its simplicity and inherent low noise. However, to work properly it requires that Idss [5] of Q2 be larger than I dss of Q I .
Volume 92, Number 6, November-December 1987 Journal of Research of the National Bureau of Standards
Ikn INPUT
(!;'--....-
soon soon v+
'* IOI' F iI2-30V)
IMn OP-27180I'F
'----+ OUTPUT
19kn :t 2kn
200F
'------.w..-_I I kn Rs IMn
Fillllre 1. Schematic diagram of the low noise preamplifier. NOTE: I) All resistors I % metal film. 2) All capacitors are tantalum. 3) V + must be well filtered. 4) The OP-27 power supply leads should
be bypassed with 10 nand 0.1 F close to the OP-AMP.
The gain of the cascode input stage is large, about 50. Hence, the noise in this stage is the dominant noise mechanism in the amplifier, and we will therefore confine our analysis to the cascode input stage and the associated biasing circuitry. The signal frequency equivalent circuit of the input stage is illustrated in figure 2. From figure 2 we can proceed to draw the noise equivalent circuit as shown in figure 3. Using this model, we can write the equivalent input noise, En;, as [6]
2 2 2 2 Z2 ( I ) 2 E ni = E nRg + E nQI +
1 nQ! g + Ko!
where Kt = gmlRd and KQ! = -gm1/gm2 is the gain of the common source component of the cascode. Zg is the impedance presented to the gate of Q 1 formed by the parallel combination of Cg, the gate capacitance, and Rg, the gate bias resistor. The choice of Q2 is governed by a tradeoff between
OUTPUT
INPUT
10n
Fillllre 2. Signal frequency equivalent circuit of the cascode inp ut stage.
384
bootstrapping Cgd of Ql for lowest input capacitance and gain in Q 1 suppressing voltage noise in Q2 relative to Q1. This suggests that the choice of identical FETs for Ql and Q2 may not be optimum. For this amplifier, we chose Q2 to be a 2N4416, yielding gm1/gm2 - 4, which suppresses the voltage noise of Q2 well below that of Q 1 and still provides a reduction of input capacitance from -44 to -11 pF.
Noise Measurements
The amplifier noise was determined by first measuring the transfer function of the amplifier on a spectrum analyzer (see fig. 4). The input capacitance was then obtained by using a known value of the capacitor in series with the input of the amplifier and measuring the change in apparent amplifier gain as a function of capacitance. In order to measure the input current noise, the gate bias. resistor, Rg, was increased to 7 X lOll n so that the term I;Q! zi would dominate in eq (I ). A measurement of the noise from 1.5 to 10 Hz coupled with the known input capacitance, Cg, allows one to write
(2)
where Eni (j) is the equivalent noise at frequency / at the input of Q1. Using a linear regression analysis to find the slope, m, of the 1/ En; vs / line, we can then write
1 _ 21TCg nQ! - m (3)
This analysis holds, assuming that the thermal noise current of Rg does not swamp the noise current of QI and that the perturbation of 1// noise is small. The first assumption is easily checked as our
Volume 92, Number 6, November-December 1987 Journal of Research of the National Bureau of Standards
gm2 VGS2 OUTPUT - D2
EnQI 52
INPUT
gm1 InQ2
VGS1
EnQ2 G2
Figure 3. The noise equivalent circuit of the cascode input state.
7X lO" n resistor used for Rg generates only 0.15 fA/VHz noise current which is of the same order of magnitude as the noise current associated with Q1. The 1// contribution of current noise in both the input FET and Rg was measured to be less than 10-16 A/VHz at 1.5 Hz.
1000
I z -<[ (.!)
lOO
10 10 102 103 104 105
F REQUENCY (Hz)
Figure 4. Measured transfer function of the amplifiers.
EnQI> the 'voltage noise associated with QI, was measured by replacing the 7 X 10" n resistor used for Rg with a 10 n resistor. This makes the IQI Zi term in eq (1) insignificant and the equation can then be rewritten to yield:
385
If the noise associated with Q2, gm1/gm2, and the output noise are measured, one can infer the noise associated with Q I.
Results
Measurements using three different 2SK 117 FETs for QI and a variety of different 2N4116 FETs for Q2 give the following results for the amplifier
En; = I . I nV /VHz In; = 0.25 fA/VHz . (5)
Figure 5 shows the measured voltage noise as a function of frequency for the amplifier. Independent measurements with 2N4416 FETs show that the noise voltaassociated with them is approximately 3 nV /VHz. Using this value and eq (5) we can infer a noise voltage for the 2SK 117 of about 0.8 nV /VHz. It is interesting to compare this to the theoretical result derived by van der Ziel: [7]
_ (4KT) 1/2 enQI - 3 gm! . (6)
Using gm! I 60 n' the transconductance of the
Volume 92, Number 6, November-December 1987 Journal of Research of the National Bureau of Standards
2SK 117 at 3 mA drain current, we obtain enQI = 0.82 nV Iv'Hz which is in agreement (possibly fortuitous) with the measured result.
...... > .5 W UI 0 Z W C) Cl I-..J 0 >
100
10
10 102 103 FREQUENCY (Hz'
104
Figure 5. Measured input voltage noise.
..... Cl
10 !:. w 0 Z
I I-Z W It: a: :::> u
If one measures the gate current of the input FET in a version of this amplifier in which Q2, the common gate portion of the cascode, is shorted, making the input of the amplifier a common source stage, an interesting effect occurs. The gate current, as measured by the voltage drop across Rg, decreases and finally changes sign with increasing drain current. A measurement of the noise current in this region suggests that in fact two (at least) competing currents are responsible, as the noise current is monotonically increasing in the region of apparently zero gate bias current. This is as would be expected for the noise from two competing processes. Thus, this effect is potentially useful in an application in which the amplifier must draw a minimal bias current through the gate. However, a drawback to this circuit is that the input capacitance is - 50 pF as opposed to - 11 pF for the cascode configuration. The cascode amplifier also exhibits very low input bias current, typically less than 0.3 pA for drain currents in the 3 mA range, but it does not exhibit an apparent vanishing of this bias current as does the common source configuration. It should be noted that this effect prevents us from inferring that the noise current in Ql is due to shot noise in the measured gate current ofQl, since the true gate current is not a well determined quantity in the presence of these competing currents.
The bandwidth of the amplifier as shown in figure 1 is limited to about 500 kHz. This bandwidth limitation is, however, due to the limited bandwidth of the op-amp used for the output stage. If additional bandwidth is required, Rc and Rd should be reduced and a video amplifier should be used as the output stage.
386
Conclusion
We have discussed the design and test of a FET cascode input amplifier with extremely low voltage noise, less than 1.2 nV Iv'Hz, and extremely low current noise, 0.25 fA/v'Hz.
This amplifier also has a low input capacitance of II pF. Thus it can be used to provide useful low noise gain from I Hz to more than 30 MHz. Another significant attribute is the very low bias current drawn by the amplifier, less than 0.3 pA; a modified version of this amplifier draws even less input bias current. A short discussion of design criteria and noise mechanisms in cascode amplifiers is also provided.
Acknowledgments
The authors are grateful to John Hall and David Howe for their many useful comments and suggestions. Steven R. Jefferts would also like to thank Gordon Dunn for his support and encouragement on this project.
About the Authors: Steven R. Jefferts is with the Joint Institute for Laboratory Astrophysics University of Colorado and the National Bureau of Standards. F. L. Walls is a physicist with the Time and Frequency Division in the NBS Center for Basic Standards.
References
[I) The term cascode amplifier refers, in a historical sense, to a
pair of triode vacuum tubes operated as a grounded cathode amplification stage followed by a grounded grid amplification stage. In the case of bipolar transistors it
refers to a common emitter stage followed by a common
base stage and in FETs it is a common source-common gate pair as used here. Hybrid cascode amplifiers using a common source FET followed by a common base bipolar
transistor are also common. See, for example, R. Q. Twiss and Y. Beers, in Vacuum Tube Amplifiers, MIT Radiation LABS Series edited by G. E. Valley Jr. and M. Wall man (Boston Technical Lithographers, 1963), Ch. 13.
(2) Bloyet, D., Lepaisant, J., and Varoquaux, E., Rev. Sci. Instrum. 56, 1763 (1985).
(3) Barlow, S. E., Luine, J. A., and Dunn, G. H., Int. J. Mass.
Spectrom. Ion Proc. 74, 97 (1986).
(4) Anderson, P. T., and Pipes, P. B., Rev. Sci. Instrum. 45, 42 (1974).
(5) ldss is the value of the saturated drain-source current in a
FET operated at zero gate source voltage. (6) Motchenbacher, C. D., and Fitchen, F. c., in Low Noise
Electrical Design (Wiley, New York, 1973), p. 231. (7) van der Ziel, A., Proc. IEEE 50, 1808 (1962).
2N4416A2N4416A
Document Number 3631
Issue 1
Semelab plc. Telephone +44(0)1455 556565. Fax +44(0)1455 552612.
E-mail: sales@semelab.co.uk Website: http://www.semelab.co.uk
Semelab Plc reserves the right to change test con-ditions, parameter limits and package dimensions without notice. Information furnished by Semelab is believed to be both accurate and reliable at the time of
going to press. However Semelab assumes no responsibility for any errors or omissions discovered in its use. Semelab encourages customers to verify that
Semelab plc. Telephone +44(0)1455 556565. Fax +44(0)1455 552612.
E-mail: sales@semelab.co.uk Website: http://www.semelab.co.uk
10mA
300mW
2.4mW / °C
–55 to 150°C
–55 to 200°C
SMALL SIGNAL
N–CHANNEL J–FET THAT IS
DESIGNED TO PROVIDE HIGH
PERFORMANCE AMPLIFICATION AT
HIGH FREQUENCIES
FEATURES
• EXCELLENT HIGH FREQUENCY GAINS
• CECC SCREENING OPTIONS
• SPACE QUALITY LEVEL OPTIONS
APPLICATIONS:
The 2N4416 and 2N4416A are N-ChannelJFETs designed to provide high-performanceamplification, especially at high-frequency.
VGD Gate – Drain Voltage
VGS Gate – Source Voltage
IG Gate Current
PD Power Dissipation
Derate
Tj Operating Junction Temperature Range
Tstg Storage Temperature Range
–30V
–30V
–35V
–35V
MECHANICAL DATA
Dimensions in mm (inches)
TO-72(TO-206AF)
ABSOLUTE MAXIMUM RATINGS
(Tamb = 25°C unless otherwise stated)
PIN 1 - Case
PIN 3 -Drain
PIN 2 - Gate
PIN 4 - Source
0.48 (0.019)0.41 (0.016)
dia.
4.95 (0.195)4.52 (0.178)
4.95 (0.195)4.52 (0.178)
5.3
3 (
0.2
10)
4.3
2 (
0.1
70)
12.7
(0.5
00)
min
.
1
2
3
4
2.54 (0.100)Nom.
2N4416 2N4416A
2N4416A2N4416A
Document Number 3631
Issue 1
Semelab plc. Telephone +44(0)1455 556565. Fax +44(0)1455 552612.
E-mail: sales@semelab.co.uk Website: http://www.semelab.co.uk
Semelab Plc reserves the right to change test conditions, parameter limits and package dimensions without notice. Information furnished by Semelab is believed
to be both accurate and reliable at the time of going to press. However Semelab assumes no responsibility for any errors or omissions discovered in its use.Semelab encourages customers to verify that datasheets are current before placing orders.
Parameter Test Conditions Min. Typ. Max. Unit
ELECTRICAL CHARACTERISTICS (TA= 25°C unless otherwise stated)
VDS = 0V 2N4416
IG = –1µA 2N4416A
VDS = 15V 2N4416
ID = 1nA 2N4416A
VDS = 15V VGS = 0V
VGS = –20 VDS = 0V
Tamb = 125°C
VDG = 10V ID = 1mA
VDS = 10V VGS = –10V
IG = 1mA VDS = 0V
VGS = 0V ID = 1mA
VDS = 15V VGS = 0V
f = 1kHz
VDS = 15V VGS = 0V
f = 1MHz
VDS = 10V VGS = 0V
f = 1kHz
V(BR)GSS Gate – Source Breakdown Voltage
VGSS(off) Gate – Source Cut–off Voltage
IDSS* Saturation Current
IGSS Gate Reverse Current
IG Gate Operating Current
ID(off) Drain Cut–off Current
VGS(F) Gate – Source Forward Voltage
RDS(on) Drain – Source On Resistance
gfs Common – Source Forward
Transconductance
gos Common – Source Output
Transconductance
Ciss Common – Source Input Capacitance
Common – Source Reverse TransferCrss
Capacitance
Common – Source OutputCoss
Capacitance
_en Equivalent Input Noise Voltage
–30 –36
–35 –36
–3 –6
–2.5 –3 –6
5 10 15
–2 –100
–4 –100
–20
2
0.7
150
4.5 6 7.5
15 50
2.2 4
0.7 0.8
1 2
6
V
mA
pA
nA
pA
V
Ω
ms
µs
pF
nV √Hz
STATIC CHARACTERISTICS
DYNAMIC CHARACTERISTICS
Pulse Test; PW = 300µs, Duty Cycle # 3%
2SK117
2003-03-25 1
TOSHIBA Field Effect Transistor Silicon N Channel Junction Type
2SK117
Low Noise Audio Amplifier Applications
• High |Yfs|: |Yfs| = 15 mS (typ.) (VDS = 10 V, VGS = 0)
• High breakdown voltage: VGDS = −50 V
• Low noise: NF = 1.0dB (typ.)
(VDS = 10 V, ID = 0.5 mA, f = 1 kHz, RG = 1 k)
• High input impedance: IGSS = −1 nA (max) (VGS = −30 V)
Maximum Ratings (Ta ==== 25°C)
Characteristics Symbol Rating Unit
Gate-drain voltage VGDS −50 V
Gate current IG 10 mA
Drain power dissipation PD 300 mW
Junction temperature Tj 125 °C
Storage temperature range Tstg −55~125 °C
Electrical Characteristics (Ta ==== 25°C)
Characteristics Symbol Test Condition Min Typ. Max Unit
Gate cut-off current IGSS VGS = −30 V, VDS = 0 −1.0 nA
Gate-drain breakdown voltage V (BR) GDS VDS = 0, IG = −100 µA −50 V
Drain current IDSS
(Note) VDS = 10 V, VGS = 0 1.2 14 mA
Gate-source cut-off voltage VGS (OFF) VDS = 10 V, ID = 0.1 µA −0.2 −1.5 V
Forward transfer admittance Yfs VDS = 10 V, VGS = 0, f = 1 kHz 4.0 15 mS
Input capacitance Ciss VDS = 10 V, VGS = 0, f = 1 MHz 13 pF
Reverse transfer capacitance Crss VGD = −10 V, ID = 0, f = 1 MHz 3 pF
NF (1) VDS = 10 V, RG = 1 kΩ
ID = 0.5 mA, f = 10 Hz 5 10
Noise figure
NF (2) VDS = 10 V, RG = 1 kΩ
ID = 0.5 mA, f = 1 kHz 1 2
dB
Note: IDSS classification Y: 1.2~3.0 mA, GR: 2.6~6.5 mA, BL: 6~14 mA
Unit: mm
JEDEC TO-92
JEITA SC-43
TOSHIBA 2-5F1D
Weight: 0.21 g (typ.)
2SK117
2003-03-25 2
2SK117
2003-03-25 3
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