a 60-ghz cmos direct-conversion wireless transceiver

Ryo MinamiAdvisor: Kenichi Okada

Co-Advisor: Akira Matsuzawa

Tokyo Institute of Technology, Japan

Matsuzawa& Okada Lab.

A 60-GHz CMOS Direct-Conversion Wireless Transceiver

1

2

Outline

• Motivation• RF Front-end

─ 60GHz injection-locked oscillator(ILO) with 20GHz phase lock loop(PLL)

─ 60GHz transmitter(Tx)─ 60GHz receiver(Rx)

• Measurement and Comparison• Conclusion

3

Outline

• Motivation• RF Front-end

─ 60GHz injection-locked oscillator(ILO) with 20GHz phase lock loop(PLL)

─ 60GHz transmitter(Tx)─ 60GHz receiver(Rx)

• Measurement and Comparison• Conclusion

4

Motivation

57.24GHz - 65.88GHz 2.16GHz/ch x 4channels QPSK 3.5Gbps/ch 16QAM 7Gbps/ch

IEEE 802.11ad specification

• 60GHz CMOS direct-conversion transceiver for multi-Gbps wireless communication

57 58 59 60 61 62 63 64 65 66fGHz

240MHz

120MHz

1 2 3 4

1.76 GHz

2.16 GHz

5

Challenges for mmW Transceivers

• Target– a low-power direct-conversion RF

front-end with 4-channel coverage– very low phase noise

• Design complexity– 2.4GHz vs 60GHz (25x)– 20MHz-BW vs 2.16GHz-BW (108x)

6

Phase Noise RequirementFor 16QAM direct-conversion, -90dBc/Hz@60GHz is required.

0

1

2

3

4

5

-100 -98 -96 -94 -92 -90 -88 -86 -84

AM-AM of PA

16QAM

QPSKR

equ

ired

CN

R [

dB

]

Phase noise [dBc/Hz] @ 1MHz offset

• 60GHz QVCO[1]

• Low Q for capacitors

• 30GHz push-push VCO[2]

• 2nd harmonic• 90 degree hybrid

LO Topologies 1

7

Poor Phase Noise

I/Q mismatch

90 degree hybrid

[1] K. Scheir, et al., ISSCC 2009 [2] C. Marcu, et al., ISSCC 2009

Proposed Topology

8

• 20GHz PLL + 60GHz Quadrature Injection Locked Oscillator• Good tradeoff between phase noise & tuning range

• Target : 20dB improvement of phase noise

9

Outline

• Motivation• RF Front-end

─ 60GHz injection-locked oscillator(ILO) with 20GHz phase lock loop(PLL)

─ 60GHz transmitter(Tx)─ 60GHz receiver(Rx)

• Measurement and Comparison• Conclusion

10

Block Diagram

Tx Output

LNA

I Mixer

RF Amp.Rx input

PFD

20GHz PLL19.44GHz, 20.16GHz,20.88GHz, 21.60GHz

Q Mixer

I Mixer BB Amp.

LO Buf.

BB Amp.

RF Amp.

RF Amp.PA

Q MixerRx input

RF Amp.

36MHz

LO Buf.

CP LPF

÷4 CML÷5÷(27,28,29,30)

LogicChannel selectionGain controlPower managementTDD control

Controlsignals

I+

I-

Q+

Q-

I+

I-

Q+

Q-

Ref.Clk

60GHz QILO

BB Amp.

BB A

• Tx : 4-stage PA, Active mixer,• Rx : 4-stage LNA, Passive mixer• LO : 60GHz ILO, 20GHz PLL

11

60GHz Quadrature LO

36MHz ref.

PFD CP LPF19.44GHz20.16GHz20.88GHz21.60GHz 58.32GHz

60.48GHz62.64GHz64.80GHz

IQ

20GHz PLL 60GHz QILO

• Wide frequency tuning range• Phase noise improvement by injection locking

4 CML5(27,28,29,30)

VDD VDD

Q-

Q+I+

I-

12

Quadrature Injection Locked Osc.

• 60GHz QILO works as a tripler with 20GHz PLL.• Full 4-channel coverage is realized

with < -95dBc/Hz@1MHz-offset.

20GHz

20GHz

Phase noise

-95dBc/Hz@1MHz-offset has been realized in all channels.

-120

-110

-100

-90

-80

-70

-60

-50

-40

0.001 0.01 0.1 1 10

Ph

ase

no

ise

[dB

c/H

z]

Offset frequency [MHz]

-120

-110

-100

-90

-80

-70

-60

-50

-40

0.001 0.01 0.1 1 10

Ph

ase

no

ise

[dB

c/H

z]

Offset frequency [MHz]

-120

-110

-100

-90

-80

-70

-60

-50

-40

0.001 0.01 0.1 1 10

Ph

ase

no

ise

[dB

c/H

z]

Offset frequency [MHz]

-120

-110

-100

-90

-80

-70

-60

-50

-40

0.001 0.01 0.1 1 10

Ph

ase

no

ise

[dB

c/H

z]

Offset frequency [MHz]

Ch3:

62.64[GHz]Ch4:

64.80[GHz]

Ch1:

58.32[GHz]Ch2:

60.48[GHz]

13

Performance comparison （ 60GHz PLL ）

TargetThis Work

(PLL+QILO)

[1](60GHz QVCO)

[2](30GHz VCO+90o hybrid)

fref[MHz] - 36.0 100.0 117VCO range

[GHz] 58.3 ~ 64.8 57.8 ~ 65.0 57.0~66.0 59.6~64

Phase noise@1MHz[dBc/

Hz]<90.0 -96.3 -75.0 -72.3

Power[mW] - 106.3 78.0 63.1

Output type Quadrature Quadrature Quadrature Quadrature

[1] K. Scheir, et al., ISSCC 2009 [2] C. Marcu, et al., ISSCC 2009 14

15

Tx Blocks4-stage PA MIM TL

Up-conversion mixer

from LO

to antenna

from BB I/Q

MIM TLTL

capacitive cross-coupling [3]

[3] W. Chan, et al., JSSC 2008

16

Rx Blocks4-stage CS-CS LNA

Down-conversion mixer

Parallel-line trans.

to BB I/Q

from LO

from antenna

W=1m x40 1m x40 2m x20 2m x20

ESD protection

17

Outline

• Motivation• RF Front-end

─ 60GHz injection-locked oscillator(ILO) with 20GHz phase lock loop(PLL)

─ 60GHz transmitter(Tx)─ 60GHz receiver(Rx)

• Measurement and Comparison• Conclusion

65nm CMOSTx:1.96mm2

Rx:1.77mm2

PLL:1.37mm2

Logic:0.38mm2

LNA

4.2m

m

65nm CMOS (RF)

LNAQ MIXER

I MIXER

LO BUF.

LO BUF.

Q.OSC.

Logic

I MIXER

Q MIXER

LO BUF.

LO BUF.

Q.OSC.PA

PLL LO BUF.

Die Photo

18

19

RF Measurement Setup

I/Q

Control signals

RF board(Tx mode)

I/Q

Control signals

RF board(Rx mode)

Power supply Power supply

AWGAgilent M8190A

OscilloscopeAgilent DSA91304A

Laptop PC

I/Q output (Rx)

I/Q input (Tx)

DC supply

DC supply16.3mm x 14.4mm

6-dBi antenna

Tx

[4] R. Suga, et al., EuMC 2011

Rx

with VSA 89600

-40

-30

-20

-10

0

10

55.08 58.32 61.5

-40

-30

-20

-10

0

10

57.24 60.48 63.7-40

-30

-20

-10

0

10

59.40 62.64 65.8

-40

-30

-20

-10

0

10

61.56 64.80 68.0

-40

-30

-20

-10

0

10

59.40 62.64 65.8

20

7.0Gb/s 16QAM (max 10Gb/s)

Channel ch.1 ch.2 ch.3 ch.4 Max rate

Constellation

Spectrum

Data rate* 7.0Gb/s 7.0Gb/s 7.0Gb/s 7.0Gb/s 10.0Gb/s(ch.3)

EVM** -23.0dB -23.0dB -23.3dB -22.8dB -23.0dB (ch.3)

Distance*** 0.3m 0.5m 0.5m 0.3m >0.01m (ch.3)

*The roll-off factor is 0.25. The bandwidth is 2.16GHz except for Max rate.**EVM through Tx and Rx boards. ***Maximum distance within a BER of 10-3. The 6-dBi antenna in the package is used.

21

Arch. Max. rate in 16QAM

Distance for BER <10-3

PDC (Tx/Rx)

IMEC[5] Direct 7Gb/sch.1-4(EVM < -17dB)(not wireless)

176mW/112mW(w/o PLL)

CEA-LETI[6] Hetero 3.8Gb/s

ch.1-4

EVM=-20.7dB(Tx)

EVM=-19.2dB(Rx)

1,357mW/ 454mW

SiBeam[7] Hetero 7Gb/s

ch.2-3 (EVM < -19dB)50m (LOS)16m (NLOS)

1,820mW/ 1,250mW

This work

Direct 10Gb/sch.1-4 (EVM < -23dB) 1.3-1.6m (QPSK) 0.3-0.5m (16QAM)

319mW/ 223mW

Performance Comparison

[5] V. Vidojkovic, et al., ISSCC 2012 [6] A. Siligaris, et al., ISSCC 2011[7] S. Emami, et al., ISSCC 2011

02468

101214161820

2007 2008 2009 2010 2011 2012 2013

Da

ta r

ate

[G

b/s

]

Year

UCB

NEC OOK

Univ. of Toronto

FSKOOK

SiBeam, CEA-LETI

16QAM

QPSK+16QAMTokyo Tech

Toshiba

IMEC

direct-conversionother arch.

all oscillators inc.

QPSK+16QAM

Performance Comparison

23

Outline

• Motivation• RF Front-end

─ 60GHz injection-locked oscillator(ILO) with 20GHz phase lock loop(PLL)

─ 60GHz transmitter(Tx)─ 60GHz receiver(Rx)

• Measurement and Comparison• Conclusion

24

Summary and Conclusion• A 60-GHz direct-conversion wireless transceiver is

implemented using CMOS 65nm process.• Excellent phase noise has been realized in full 4-

channels.• The first complete transceiver covering full 4

channels with 16QAM.• Max 10Gbps data rate has been realized.• A high-speed low-power mmW transceiver has

been realized.

25

Thank you for your attention.

26

Backup slides

27

60GHz Quadrature LO Scenario

• 60GHz quadrature PLL– Phase noise degradation

e.g. -75dBc/Hz@1MHz-offset at 60GHz [1]

• 60GHz PLL with 90o hybrid [2]

– I/Q mismatch

• 60GHz quadrature ILO with 20GHz PLL[This work]

– ILO: Injection-locked oscillator– Very wide tuning – Excellent phase noise

[1] K. Scheir, et al., ISSCC 2009[2] C. Marcu, et al., ISSCC 2009

Schematic of QILO

• I-Q coupling with tail transistor• Half side injection

QnIn

Ip Qp

VDDINJn

INJp

Vctrl

Vsw1

Vsw2

Vsw

varactor

28

back-to-back layout

• I-Q coupling path– coventional ： 40um 　 　 this work ： 8um– reduction of parasitic component – Low I-Q mismatch

Die photo of QILO Schematic

VDD VDD

Q-

Q+I+

I-

180um

85u

m

29

Layout of ILO

30

Injection Locked Oscillator （ ILO ）

Phase noise is determined by following equation[12].

[12] X. Zhang, TMTT 1992

60GHz60/n GHz

Injection Lock

n=1,2,3… Free-run: 60.1GHz → Locked: 60GHz

60GHz60.1GHz60GHz

Pulling of VCOs

31

MIM Transmission Line• De-coupling use• Modeling accuracy• Avoiding self-resonance of

parallel-plate capacitors

0123456789

10

0 10 20 30 40 50 60 70Frequency [GHz]

Z0

[Oh

m]

MeasuredModel

GND

MIM TL

GND

GND

GND

TL

MIM capacitor

MIM transmission line

50 transmission line

T. Suzuki, et al., ISSCC 2008 32

33

RF Performance Summary

Tx

CG 18dB

P1dB -2dBm

Psat 5.6dBm

Rx

CG 23dB (high-gain mode)

9dB (low-gain mode)

NF < 4.9dB (high-gain mode)

IIP3 -14dBm (low-gain mode)

LO

Injection PLL 19.44, 20.16, 20.88, 21.60GHz

Ref. spur <-58dBc @ 20.16GHz

Locking range 1.4GHz

Quadrature ILO 58.0-64.7GHz (free-run)

Phase noise@1MHz-offset < -95dBc/Hz (every channel)

34

Measured Rx SNR

-80

-70

-60

-50

-40

-30

-20

-10

0

10

20

30

40

-70 -60 -50 -40 -30 -20 -10

SN

DR

[dB

]P

ou

t, IM

3, N

ois

e F

loo

r[d

Bm

]

Pin [dBm]

High GainLow Gain

SNDR

Pout

IM3

NoiseFloor

16QAM(17dB)

QPSK(10dB)

Link Budget

35

Modulation QPSK 16QAMDistance 1.5m 0.5mData rate (2.16GHz-BW) 3.5Gb/s 7.0Gb/sTx output 6.0dBm

Back-off 4.0dB 5.0dB

Tx/Rx antenna gain 6.0dBi

Implementation loss -3.0dB

NF 6.0dB

Received CNR 14.0dB 22.5dB

Margin +4.6dB +4.3dB

Mixer Layout (Core)

36

LO+ LO-

RF+

RF-

RF+

RF- LO-

LO+

Symmetric core Asymmetric core

• Mixer core excluding intersection─ LO line and RF line cross in matching network

• Mixer core including intersection─ bad symmetrical property

Symmetric Core Layout

37

• Symmetric core needs crossed and complicated matching network.

LO-

RF-

LO+

RF+

IF+

IF-

LOp LOn

RFp

RFn

Mixer core

Asymmetric Core Layout

38

• Asymmetric core can realize simple matching network.

LO+

LO-RF-

RF+

IF+ IF-

LOpLOn

RFp

RFn

Mixer core

I/Q Mismatch by Mixer Layout

• Sideband Rejection Ratio (SRR)

39

SRRAmplitude

ErrorPhaseError

Symmetriccore

-24.5 [dB] 0.04[dB] 6.8[deg]

Asymmetriccore

-42.3[dB] 0.02[dB] 0.9[deg]

60GHz LORF output

I Mixer

Q Mixer

0o

90o

0o

BB input

90o

BB inpu[GHz]

[dB

m]

SRR [dB]

LO leak

40

Arch. Max. rate in 16QAM

Distance for BER <10-3

PDC (Tx/Rx)

IMEC[5] Direct 7Gb/sch.1-4(EVM < -17dB)(not wireless)

176mW/112mW(w/o PLL)

CEA-LETI[6] Hetero 3.8Gb/s

ch.1-4

EVM=-20.7dB(Tx)

EVM=-19.2dB(Rx)

1,357mW/ 454mW

SiBeam[7] Hetero 7Gb/s

ch.2-3 (EVM < -19dB)50m (LOS)16m (NLOS)

1,820mW/ 1,250mW

This work

Direct 10Gb/sch.1-4 (EVM < -23dB) 1.3-1.6m (QPSK) 0.3-0.5m (16QAM)

319mW/ 223mW

Performance Comparison

[5] V. Vidojkovic, et al., ISSCC 2012 [6] A. Siligaris, et al., ISSCC 2011[7] S. Emami, et al., ISSCC 2011

41

Max. rate in 16QAM

Distance for BER <10-3 with 2.16GHz-BW

Area

IMEC[5] 7Gb/sch.1-4(EVM < -17dB)(not wireless)

0.7mm2

CEA-LETI [6]

3.8Gb/sch.1-4

EVM=-20.7dB(Tx)

EVM=-19.2dB(Rx)

9.3mm2(TRx)0.46mm2(PA)

SiBeam [7]

3.8Gb/sch.2-3 (EVM < -19dB)50m (LOS)16m (NLOS)

72.2mm2(Tx)72.7mm2(Rx)

This work 10Gb/sch.1-4 (EVM < -23dB) 1.3-1.6m (QPSK) 0.3-0.5m (16QAM)

5.48mm2

Performance Comparison

[5] V. Vidojkovic, et al., ISSCC 2012 [6] A. Siligaris, et al., ISSCC 2011[7] S. Emami, et al., ISSCC 2011

42

Integration #ch.Data rate (16QAM)

PDC (Tx/Rx)

IMEC[5] RF (Direct) 47Gb/s(not wireless)

176mW/112mW

(w/o PLL)

CEA-LETI [6]

RF (Hetero) 4 3.8Gb/s1,357mW / 454mW

SiBeam [7] RF (Hetero) 2 3.8Gb/s 1,820mW/ 1,250mW

Tokyo Tech(This work)

RF (Direct) 4RF: w/ wider-BW

10Gb/s319mW

/ 223mW

Performance Comparison

[5] V. Vidojkovic, et al., ISSCC 2012 [6] A. Siligaris, et al., ISSCC 2011[7] S. Emami, et al., ISSCC 2011

43

Challenges for 60GHz Transceivers• Direct-conversion full CMOS integration• 16QAM/8PSK/QPSK/BPSK support for

IEEE802.15.3c, WiGig, Wireless HD, etc.• 60GHz quadrature LO

– Low phase noise for 16QAM– Wide frequency tuning (58-to-65GHz)– I/Q phase balance

• 60GHz LNA– Low NF & High linearity– Wide bandwidth (gain flatness)

• 60GHz PA– 10dBm output– High PAE (>10%)

44

PPF

Injection-Locked Oscillator

I Q

20GHz

60GHz

PPF:polyphase filter[3] W. Chan, el al., ISSCC 2008

20GHz

60GHz

I Q

Previous work [3] This work

I/Q mismatch Single-side injection- Small I/Q mismatch - The same locking range