4h-sic p-i-n diodes on lightly doped free-standing substrates chowdhury.pdf · lightly doped...
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4H-SiC P-i-N Diodes on
Lightly Doped Free-standing Substrates
S. Chowdhury, C. Hitchcock, R. Dahal, I. Bhat and T. Paul Chow
Department of Electrical, Computer and Systems Engineering
Rensselaer Polytechnic Institute
February 26th, 2015
Slide 2
Outline
Introduction
– Wide-bandgap semiconductors
Experimental Details
– Lightly doped 4H-SiC Substrates
– P-i-N diode fabrication
Device Characterization
Summary and Future Work
Slide 3
Material Properties of Semiconductors
4H-SiC has emerged as most promising candidate for
power devices
High quality materials and processes are available
Material Eg
(eV) ni
(cm-3) εr
μn
(cm2/V.s)
Ec
(MV/cm)
vsat
(107 cm/s)
λ
(W/cm.K)
Si
1.1 1.5×1010 11.8 1350 0.25 – 0.35 1.0 1.5
GaAs 1.4 1.8×106 12.8 8500 0.4 2.0 0.5
4H-SiC 3.26 8.2×10-9 10 900a
800c 1.8 – 2.9 2.0 4.5
6H-SiC 3.0 2.3×10-6 9.7 370a
50c 2.4 2.0 4.5
GaN 3.4 1.9×10-10 9.5 1000 2.5 – 3.9 2.5 1.3
Slide 4
Power Device Structures
Power MOSFET IGBT GTO
IGBTs and GTOs preferred over MOSFETs for high
BV requirements
– Conductivity modulation reduces on-state power loss
– P+ layer is needed for hole injection
Slide 5
Lightly Doped 4H-SiC Substrates
Ultra-high voltage SiC devices require thick, lightly-
doped drift layer
– Lightly-doped 4H-SiC substrates are difficult to grow
– Thick n- epi-layer is grown on n+ substrate
N+ substrate is removed to yield lightly doped 4H-SiC
free-standing substrate (FSS)
N+ substrate ~ 350 μm
N- epi ~ 180 μm
N- free-standing wafer ~ 180 μm
Substrate
removal
Si-face
C-face
Si-face
C-face
Both Si-face and C-face available
for device fabrication
Slide 6
Material Characterization
4-inch 4H-SiC FSS wafer
4-inch 4H-SiC wafer With substrate, bow:~38 µm
After substrate
removal bow:~21µm
• Carrier lifetime is not
affected by substrate
removal process
• Smaller bow indicating
lower stress
Slide 7
Diode Fabrication
• Anode formed by
aluminum ion
implantation
• Cathode formed by
phosphorus ion
implantation
• Activation anneal:
1675 oC, 30 min, Ar
• Ohmic contact
anneal: 1000 oC, 2
min, Ar
Slide 8
I-V Characteristics
Good conductivity
modulation - ron much lower
than drift layer resistance ≈
500 mΩ.cm2
Higher VF and ron of FSS
diodes is possibly due to
additional implant damage
from cathode implant
Slide 9
I-V characteristics
Recombination through multiple shallow and deep levels
Modified SNS theory: 𝑛 = 𝑠+2𝑑
𝑠+𝑑=
4
3
Number of shallow levels, s = 2 Number of deep levels, d = 1
Slide 10
Dynamic Characteristics
Good agreement between electrical
(OCVD) and optical (MPCD) lifetime
measurement results
OCVD measurement
𝝉𝑯𝑳 = 𝟐𝒌𝑻
𝒒
𝒅𝑽
𝒅𝒕
−𝟏
JRP = 200 A/cm2
QRR = 7.5 μC/cm2
Reverse Recovery
Slide 11
Lifetime enhancement on FSS wafer by C implantation
As-received
Carbon implant
τ = 2.1 μs
τ = 9.7 μs
Initial measurement
(2.1 μs)
Carbon implant – double
sided (Dose = 1e14 cm-2)
Drive-in anneal
(T = 1600 oC)
Final measurement
(9.7 μs)
Slide 12
Summary
Demonstrated lightly doped 4H-SiC free-standing wafers
– Good surface quality with minimal wafer bow
– Carrier lifetime is not affected by substrate removal
– Enhancement of carrier lifetime by C implantation
Fabricated pin diodes on lightly doped substrates
– Comparable performance with conventional diodes
– Good agreement between electrical and optical lifetime
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