2019 (gan)功率ic应用设计大赛培训专场一郭春明(cmg), 技术总监

Navitas Proprietary & Confidential, Under NDA

2019 纳微半导体氮化镓(GaN)功率IC应用设计大赛培训专场 (一)

郭春明(CMG), 技术总监

File r4-21-19

2019 纳微半导体氮化镓(GaN)功率IC应用设计大赛

大赛时间：2019年5月6日——10月31日；样片申请截止日期：7月31日2

*扫码了解大赛详情及报名*

大赛介绍

参赛方案设为：65W PD(type C) 和 100W C+C+A 两种电源方案，任选其一；

活动总奖金超320,000元，最高单项奖 60,000元，史无前例哦！

期待您的挑战！

大赛时间：2019年5月6日——10月31日；样片申请截止日期：7月31日

•氮化镓(GaN)材料简介

• Navitas氮化镓集成IC详解

• Navitas GaN IC 在PD里面的应用

• Navitas GaN IC 在高频PFC/LLC里面的应用

氮化镓

•什么是氮化镓？• 氮化镓（GaN，Gallium nitride）是氮和镓组成的化合物半导体

•氮化镓是第三代半导体材料的一种• 第一代硅和锗

• 第二代砷化镓为代表

• 第三代氮化镓和碳化硅（宽禁带半导体）

Performance of WBG materials

物理特性 4H-SiC Si GaN

禁带宽度[eV] 3.23 1.1 3.4

临界电场强度[MV/cm] 2.9 0.3 3.3

饱和电子迁移率[107cm/s] 2.5 1 2.5

电子迁移率[cm²/V/s] 900/115 1400/450 1800/2DEG

与传统硅材料相比,氮化镓（GaN）材料具有以下特性：1. x3 禁带宽度2. x10 临界电场强度3. x2.5饱和电子迁移率

1. 高耐压2. 高频率3. 高效率4. 高抗辐射能力

Lateral GaN Advantage

• WBG GaN material allows high electric fields so high carrier density can be achieved

• Two-dimensional electron gas with AlGaN/GaN heteroepitaxy structure gives very high mobility in the channel and drain drift region

• Lateral device structure achieves extremely low Qg and QOSS and allows integration

• Integration on silicon substrates means mature low cost wafer fabrication is available

Si Landscape

GaN / SiC Landscape

GaN器件的常见结构

增强型常闭结构 E-Mode

1. 简化了驱动2. 增强了可靠性3. 减小电路空间4. 速度更快

驱动集成型常闭结构

级联型常通结构 D-Mode

Benefits of e-Mode GaN

• Lower Rdson

• No reverse recovery loss

• Negligible gate driver loss

• Small output capacitance

NV6115

E-Mode GaN Reverse Conduction

NV6115• GaN FETs support reverse conduction

in off mode

• For 650V Navitas GaN, VSD is typically 3.5V

• Reverse conduction without Qrrloss

• It supports full rated current

What is the desired Gate voltage range

Discrete Approach Requires Rdamp

Rdamp ….does?

World’s First GaNFast™ Power ICs

Navitas

Benefit of GaNFast™ Power ICs

Clean, Controlled FET Gate

• Discrete driver• Gate loop

inductance creates overshoot(even with good layout)

• Reliability concern

• GaNFast Power IC• No gate loop

parasitic

• Clean and fast gate signal

• No CdV/dt turn-on

• No IV crossover turn-off switching losses

Discrete Driver & Discrete FET

2 V Overshoot

4V Undershoot

Integrated Drive→ Simple & Robust

Wide Range VCC

(10-30V)

Regulator ensures VGS within SOA

No inductance or ringing in gate loop

Total layout flexibility & simplicity

PWM Hysteresis for noise immunity

Gate protected from external noise

(Not pinned out of package)

Under voltage lockout protects the driver & FET when full

power supply is not available

Internal Circuit

Recommendation Parameter Value

650V GaN Power IC

iDrive Family Part number Package (mm) RDS(ON) (typ, mΩ) FSW (max)

SingleNV6115 5x6

1602 MHz

NV6117 120

Application Circuit

NV6115/7 Startup Process

Turn On 条件：- Vcc > 10V(批量),- PWM 有信号- VDD 在5.5~7V的工作范围

Voltage Slew Rate Control

• dV/dt controllable from 180 V/ns to 10 V/ns for EMI suppression

Reduce Bias Power

• Quiescent current is high, and may require a cutoff switch during standby

Zener Diode: Use Stable Zener

• To reduce quiescent current, Zener bias current is very low (10-100uA)

• Use recommended diodes, or select Zener with sharp knee at 10uA

• Add a resistor to increase bias to stabilize Zener voltage

External Zener sets reference voltage for internal circuit. Large deviation from 6.2V affects circuit operation

Layout

• Use 4-layer PCB to spread heat. Be careful when current sense resistor is used

NV6115/7 (Parallel Configuration)

Maximum 2x Parallel !Boost Circuit, BCM/DCM Modes only !

Reduce Input Power Loop

• Minimize power loop• Reduce inductance to minimize ringing

• Important for EMI

Maximize GaN Thermal Coppers

High Side Vsw Copper

• High side copper can cover high side components and traces

• Including bias caps and high side Zener

• Cathode of the bootstrap diode and output of isolator

• Don’t extend ground or Vbus+ copper beneath high side components

No High Side and Low Side Overlap

• Low side and high side copper and components shouldn’t overlap

• Vbus+ copper shouldn’t overlap high side components

GaNFast USB-C Chargers Have Arrived

Challenge: “Mu One”

• 14 mm profile

• CE, UL, etc.

Mu One 45W Apple 27W

Images courtesy Made-in-Mind

45 W in 11 mm = HF Planar ACF

• Size : 29 cc (41 cc with case)

• Density : 1.7 W/cc (27 W/in3), 1.1 W/cc (18 W/in3) cased

Proprietary; Authorized Use with Navitas License

• Planar Magnetics:

• Low profile

• Automated assembly

• Predictable performance

• High yield

Type-CReceptacle

Planar Transformer

Bulk Caps

AC Bridge

NV611x Power ICs ACF IC UCC28780

SR FET

EMIFilter

45 W Mu One: Cool, Quiet

World’s Thinnest 65W USB-PD

0.5 1 1.5 2 2.5 3 3.5 4 4.5

115Vac

Vo=9V Vo=15V

230Vac

Vo=20V

115 VAC, 20 V / 3.25 A, 25°C ambient, no case, no airflow, no heatsink20mins steady state operation. Maximum case <70°C

Power, Output

65 W USB-PD

TopologyACF with NV6115, NV6117 GaNFast Power ICs

Frequency 600 kHzSize 27 cc (45 cc with case)

Density2.4 W/cc (39 W/in3) uncased1.5 W/cc (24 W/in3) cased

Efficiency93.3% peak (115 VAC)93.2% at 90 VAC, full loadDoE Level VI, Euro CoC (EuP) Tier 2

150 W, 19 V: 200kHz/500 kHz

Power, Output 150 W, 19 V

Topology CrCM PFC NCP1615 & LLC NCP13992AB, NV6115 GaNFastFrequency PFC min. 200 kHz, LLC typ. 500 kHzSize 63 cc (101 cc with case)

Density2.4 W/cc (39 W/in3)1.5 W/cc (24 W/in3) cased

Efficiency95% peak, 93% at 90 VAC, full loadDoE Level VI, Euro CoC (EuP) Tier 2

Highest Density 300 W, 19 V

TopologyInterleaved CrCM Boost PFC(NCP1632 + NV6117)ZVS LLC (NCP13992 + NV6117)

Frequency PFC = 200 kHz min., LLC = 500 kHz

Size, Density

75 x 150 x 15 mm = 168 cc = 1.8 W/cc (30 W/in3) PCBA80 x 155 x 20 mm = 248 cc = 1.2W/cc (20 W/in3) cased

Enabling High-Density Adapters

Ultra-thin LED TV

All-in-One PCs

Next-Gen Gaming

Consoles

Magnetics Frequencies – 10x Every Decade

A. J. Hanson, J. A. Belk, S. Lim, C. R. Sullivan and D. J. Perreault, "Measurements and Performance Factor Comparisons of Magnetic Materials at High Frequency,"

in IEEE Transactions on Power Electronics, vol. 31, no. 11, pp. 7909-7925, Nov. 2016.

Y. Han, G. Cheung, A. Li, C. R. Sullivan and D. J. Perreault, "Evaluation of Magnetic Materials for Very High Frequency Power Applications," in IEEE

Transactions on Power Electronics, vol. 27, no. 1, pp. 425-435, Jan. 2012.

Boost PFC Circuit Modes

Boost PFC Circuit Analysis

150W Boost PFC Calculations

0 100 200 300 400 500 600 700 800 900 1000

Frequency [kHz]

150W Boost Inductance vs. Frequency

Pout 150 W output power

EFF 93 % total system efficiency @ AC low line

Pin 161 W input power

VACmin 90 VAC AC low line voltage

Vout 400 V DC bus voltage

IACrms 1.78 Arms AC RMS input current

Ipeak 4.99 Apk PFC inductor peak current

fsw 200 kHz switching frequency @ low line and peak of line

Lpfc 80 uH PFC inductor value

Rcs 0.100 Ohm current sensing resistor value

𝐿 =𝐸𝐹𝐹 ∙ ( 2 ∙ 𝑉𝑖𝑛)2

4 ∙ 𝐹𝑠𝑤 ∙ 𝑃𝑜𝑢𝑡 ∙ (1 +2 ∙ 𝑉𝑖𝑛

𝑉𝑜𝑢𝑡 − 2 ∙ 𝑉𝑖𝑛)

150W Boost PFC Inductor Size

PFC Controllers Comparison

Company Part # PFCFSW max

HV Startup X2-cap Discharge

DCM Mode StandbyMode

Package

ON Semi NCP1615CDR2G 200kHz Y Y Y Y SOIC-16

TI UCC28056 100kHz N N Y Y SOT-26

ST STCMB1(combo)

100kHz Y Y N Y SOIC-20W

MPS HR1200(combo)

100kHz Y Y Y Y SOIC-28

LLC Circuit Operating Points

150W LLC Circuit Design

Fsw 500 kHz switching frequency

Coss_GaNFET 50 pF NV6115 = 50pF

Coss_BD 10 pF bootstrap diode capacitance

C_parasitics 10 pF pcb, x'fmr windings

Coss_SRFET 12 pF div by N^2, NVFMSC670CNL = 690pF x 2 = 1380pF/11^2 = 12pF

Coss_Total 82 pF

Ts 2 usec switching period (1/Fsw)

td 0.18 usec controller dead-time

To 1.64 usec resonant period (Ts - 2*td)

Tolerance 10 % ZVS margin

Lm 203 uH x'fmr magnetizing inductance value = To*Td/(16*Coss)-ZVS margin tolerance

Lm:Lr 10 Lm to Lr ratio

Lr 20 uH resonant inductor value

Ls 6 uH x'fmr leakage inductance

Tolerance 10 % below resonance margin

Cr 3.5 nF resonant capacitor value

150W LLC Transformer Size

LLC Controllers Comparison

Company Part # LLCFSW max

HV Startup X2-cap Discharge

Burst Mode

HBADTmin

Package

ON Semi NCP13992 500kHz Y Y Y 160nsec SOIC-16

TI UCC25630 300kHz Y Y Y 500nsec SOIC-16

NXP TEA19161 200kHz Y Y Y 350nsec SOIC-16

ST STCMB1(combo)

100kHz Y Y Y NotVerified

SOIC-20W

MPS HR1200(combo)

100kHz Y Y Y NotVerified

SOIC-28

150W Demoboard (Specifications)

Ref. Parameter Value Units

VIN Input Voltage 90-265 VAC

47-63 Hz

VOUT Output Voltage 19 V

IOUT Output Current (100% load) 8 A

IOUT_LIM Output Current Limitation (short-circuit or over-load) 9.5 A

POUT Output Power (max) 150 W

FSW Switching Frequency PFC (120V, 100% load) 200 kHz

PFC (220V, 100% load) 100 kHz

LLC 500 kHz

ɳ Efficiency 230 VAC, 150 W 94.9 %

115 VAC, 150 W 93.8 %

PSTBY Standby Power Consumption 115 VAC < in progress mW

230 VAC < in progress mW

PF Power Factor 0.95

Board Dimensions 110 x 50 x 12.5 mm

Board Volume (uncased) 68.75 cc

Power Density (uncased) 35.75 W/in3

2.18 W/cc

Customer LxWxH (uncased) Size (uncased)

Size Increase vs. Navitas (uncased)

Navitas 110 x 50 x 12.5 mm 68.75 cc N/A

Customer #1 129 x 55 x 16.3 mm 115.65 cc + 40.6 %

Customer #2 5.575 x 1.975 x 0.675 in. 121.8 cc + 43.6 %

Customer #3 115 x 55 x 16.2 mm 103.1 cc + 33.3 %

150W Demoboard (Power Board PCB Bot Layer)

Bot Silk Layer

150W Demoboard (Power Board Mid1/Mid2 Layers)

Mid1 Layer Mid2 Layer

150W Demoboard (90V, 130W, peak of line)

Size Reduction

150W 100K(PFC)/250K(LLC) Vs 200K/500K

150W 200K(PFC)/500K(LLC) Vs 100K/250K

150W PFC Demo: Schematic

150W PFC Demo Board 100 x 50 x 20mm

• Low profile

• ‘No-heatsink’ design

• 150W, DCM (boundary) mode

• Run at PFC IC limit (L6562A)• 120V = 167-230kHz

• 220V = 230-500kHz(265V peaks at 1MHz)

• Simple “No heatsink” design• 100x50x20mm

• Si vs. GaN• Efficiency, temperature,

PF, etc.

PackRDS(ON

COSS(er)

COSS(tr)

R*QGmΩ.nC

R*COSS(tr)

mΩ.pF

R*COSS(er)

mΩ.pF

NV6115 5x6 170 2.5 30 50 400 8,000 4,800

IPL65R199CP

8x8 180 32 69 180 5,760 32,400 12,400

IPL60R130C7

8x8 115 35 53 579 4,025 66,600 6,100

GaN Benefits

>50% n/a >10x >2x >10x >10x >7x >2.5x

150W PFC: SuperJunction Si vs. GaN Power IC

Si Hits the Frequency Roadblock

0 30 60 90 120 150

Navitas 120V

Navitas 220V

Si CP 120V

OutputPower (W)

• GaN running cool (61°C) at full load• Efficiency up 1% vs. Si CP

• Loss 20-35% lower

• Power Factor >99.5%

• CP Si running >90°C

• C7 Si too hot to run at 220VAC

• Si COSS is 50x-100x worse than GaN at VDS < 30V

• High loss due to large stored charge while hard-switching

Silicon’s High COSS Creates Partial ZVS

• Turn-off losses low due to integrated drive

• Near loss-less ZVS turn-on transition

• Minimize deadtime for low reverse conduction loss

• No voltage spikes / overshoot

Si GaN

Vendors Hitachi TDK/EPCOS Ferroxcube DMR NCD TP

Core Material ML95S ML91S N49 3F36 DMR50 LP5W TP5

Fsw 300k~600k 500k~1M 200k~500k 200k~400k 200k~300k 300k~500k 200k~400k

High Frequency Core

Navitas Proprietary & Confidential, Under NDA63

Backup Slides

Vendors suggested

Primary Litz wire：规格联系人

1st，MWS 0.05mm*25 Eric YELICH <eric@mwswire.com>

2nd，JWS 0.05mm*25 尹肖華' <yxh@nt1.jswire.com.tw>

Triple insulated wire：规格联系人

1st：Totoku 0.1mm*40Hiraih@totoku.co.jp

sugawaras@totoku.co.jp

2nd：锐磁 0.1mm*40 刘小刚 <liuxg88@163.com>

Core 规格联系人

TDG TP5，TP5E 张林权<13916932111>

NCD LP5

HITACHI ML95S,ML91S

*设计赛报名*

期待您的挑战！

2019 (gan)功率ic应用设计大赛培训专场一郭春明(cmg), 技术总监

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2019 (gan)功率ic应用设计大赛 培训专场 一 郭春明(cmg), 技术总监

2019 (gan)功率ic应用设计大赛培训专场一郭春明(cmg), 技术总监