2 verilog rtl
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VERILOGRTL-Level
by
Sivanantham S
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RTL
Register Transfer Level Provides higher level of abstraction
increases productivity
Specify the functionality / behavior / algorithm rather
than gates & connection
ECE301 VLSI System Desig n2
.
Perform logic optimization
Specification as per template to avoid synthesis surprises
GIGO
Think in terms of Hardware engineer
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Number System
Syntax : number
size : specifies number of bits in DECIMAL
optional. Default number atleast 32
base_format : specifies the radix
optional. Default is decimal
ECE301 VLSI System Desig n3
d or D for decimal
h or H for hexadecimal
b or B for binary
o or O for octal
Underscore (_) is allowed to improve readability
cannot be the first character
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Number System Example
Example for sized number : 30 binary : 6b01_1110 same as 6b11110
octal : 6o36
decimal : 6d30
hexadecimal : 6h1E
ECE301 VLSI System Desig n4
Example of unsized number
No size or format : 30 (decimal number 30, 32-bit wide)
No size : h1E (in hexadecimal, 32-bit wide)
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Continuous Assignment
Syntax : assign LHS = RHS ; wire out ;
assign out = a | b ;
LHS must be a net declared before usage
RHS can be reg, net or function
ECE301 VLSI System Desig n5
LHS is evaluated whenever RHS changes
Implicit assignment
short cut. Combines declaration and assignment
wire out = a | b ;
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Width Mismatch Rules
Mismatch when LHS width not equal to RHS width
Warning issued. Proceeds with simulation
Verilog is not strongly typed language as VHDL
RHS width greater than LHS width
ECE301 VLSI System Desig n6
LSBs are selected. MSBs are dropped
RHS width less than LHS width
RHS width increased to match LHS width Fill MSBs with zero.
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Arithmetic Operator
add (+) subtract (-)
multiply (*)
divide (/)
ECE301 VLSI System Desig n7
remainder from division
takes sign of first operand
Examples 13 % 3 equals 1
9 % -2 equals 1
-9 % 2 equals -1
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Addition Examples
Can mix base_format. Remember width mismatch rules
wire [7:0] out = 8 + 8b00_10;
wire [7:0] out = 4b10 + 4h5;
wire [7:0] out = 8o10 + 8h5;
Answer is 10
Answer is 7
Answer is 13
ECE301 VLSI System Desig n8
wire [7:0] out = 8 + 4o10;
wire [3:0] out = 8 + 4o10;
One bit x entire result is x
wire [3:0] out = 4b10x0 + 4b1110 ;
Answer is 16
Answer is 0
Answer is 4bxxxx
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Subtraction Examples
Negative number : 2s complement wire [7:0] out = 8 - 4b00_10; //Answer is 6
wire [7:0] out = 4b10 - 4h5; //Answer is 25
ECE301 VLSI System Desig n9
-0000_0010 -2 -0000_0101 -5
0000_1000 +8 +0000_0010 +2
+1111_1110 +1111_10110000_0110 +6 1111_1101 FD (253)
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Mul and Div Examples
Multiplication wire [7:0] out = 6 * 2 ; //Answer 12
wire [7:0] out = 6 * 2b10; //Answer 12
Division : Truncate fractional part
wire [7:0] out = 6 / 2 ; //Answer 3
ECE301 VLSI System Desig n10
wire [7:0] out = 6 /4 ; //Answer 1
Remember one bit x entire result is x
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Synthesis of Arithmetic Operator
Modulus and division operator supported only if operands are constant
Addition, subtraction and multiplication
are fully supported by synthesis tool
Example
a b
ECE301 VLSI System Desig n11
module adder (out,a , b) ;
input [3:0] a, b ;
output [3:0] out ;
wire [3:0] out = a + b ;
endmoduleout
+
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Synthesis Addition Operator
Addition operator always does NOT infer an adder. wire [3:0] out = 1 + 2 ;
will infer no logic
both operands are constant
wire [3:0] out = a + 1 ;
ECE301 VLSI System Desig n12
will infer incrementer
requires only half adders (less area)
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Logical Operator
Logical NEGATION ( ! ) Logical AND ( && )
Logical OR ( || )
Result is always 1 (true), 0 (false) or x (unknown)
ECE301 VLSI System Desig n13
.
Operand value is one if its value is other than zero.
Operand itself can be a result of another expression.
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Logical Operator Example
wire out = 3 && 0 ; wire out = 3 || 0 ;
wire out = 4b0101 && 4hF ;
wire out = 4b0101 || 4hF
Answer is false
Answer is true
Answer is true
Answer is true
ECE301 VLSI System Desig n14
parentheses decides logical group
wire out = 3 && (! 0 );
wire out = 4bx101 && 4hf ; wire out = 4bxxxx && 4hf ;
Answer is true
Answer is true
Answer is x
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Relational Operator
Greater than ( >)
Less than (=)
Less than or equal (
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Relational Operator contd
case equality (===) case inequality (!==)
case equality and inequality is not supported by synthesis
Synopsys treats the result as false always
Example
ECE301 VLSI System Desig n16
wire out = (1bx == 1bx) ; //Answer is x
wire out = (1bx ===1bx) ; //Answer is true
wire out = (1bx != 1bz) ; //Answer is x
wire out = (1bx !== 1bz) ; //Answer is true
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Example
//4-bit magnitude comparator
module mag_comp (a_lt_b, a_gt_b, a_eq_b, a, b) ;
output a_lt_b, a_gt_b, a_eq_b ;
input [3:0] a, b ;
ECE301 VLSI System Desig n17
wire a_lt_b, a_gt_b, a_eq_b ;
assign a_lt_b = ( a < b ) ;
assign a_gt_b = ( a > b ) ;assign a_eq_b = (a == b ) ;
endmodule
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Bitwise Operator
NOT (~) AND (&)
if one input value is x and the other 0, result value is 0
if one input value is x and the other 1, result value is x
OR (|)
ECE301 VLSI System Desig n18
if one input value is x and the other 0, result value is x
if one input value is x and the other 1, result value is 1
XOR (^)
any input value is x, result value is x
XNOR (^~ or ~^)
any input value is X result value is X
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Bitwise Operator. contd
NAND (~&) if one input value is x and the other 0, result value is 1
if one input value is x and the other 1, result value is x
(&~) is not allowed
NOR (~|)
ECE301 VLSI System Desig n19
if one input value is x and the other 0, result value is x
if one input value is x and the other 1, result value is 0
(|~) is not allowed
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Example of Bitwise Operator
wire [3:0] out = ~ 4b1011;
wire [3:0] out = 4b1010 & 4b0101
wire [3:0] out = 4b1010 | 4b0101;
wire [3:0] out = 4bx010 | 4b101x;
Answer 4b0100
Answer 4b0000
Answer 4b1111
Answer 4b101x
ECE301 VLSI System Desig n20
=
wire [3:0] out = 4b1101 & 2b11;
wire [3:0] out = 8hA0 | 4hF;
Answer 4b0001
Answer 4b1111
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QUIZ
EVALUATE THE FOLLOWING EXPRESSIONS
wire [3:0] out = ! 4b1011;
wire [3:0] out = 4b1010 && 4b0101;
wire [3:0] out = 4b1010 4b0101;
False
True
True
ECE301 VLSI System Desig n21
wire [3:0] out = 4bx010 || 4b101x;
wire [3:0] out = 4b1101 && 2b11;
wire [3:0] out = 8hA0 || 4hF;
True
True
True
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Reduction Operator
Unary operation (Only one operand) Symbol same as bitwise operator
Perform bitwise operation on vector, result is scalar
Examples
ECE301 VLSI System Desig n22
wire out = &4b1011; //Result is 0
1 & 1 & 0 & 1
wire out = | 4b1011;// Results is 1
wire out = ^4b1011 ; Result is 1 EVEN PARITY GENERATOR
wire out = ~^4b1011 ; Result is 0
ODD PARITY GENERATOR
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Shift Operator
Right shift (>>) Left shift ( 1
Result is 4b0101. Division
wire [3:0] out = 4b0010
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Concatenation Operator
Concatenation Operator ({}) Allows appending of multiple operands
Operands must be sized wire [7:0] out = {4, 6} not allowed
Shift Register, S2P Conversion, Barrel Shifter
ECE301 VLSI System Desig n24
Example. A = 1b1, B = 2b00, C = 2b10, D = 3b110
Y = { A, B, C, D, 4b1111};
Answer is 12b1001_0110_1111
Y = { A, B[0], C[1])
Result is 3b101
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Replication Operator
Special case of concatenation Repetitive concatenation ( {{}} )
Used to set or clear wide register or bus
Examples
out = 32 1b1
ECE301 VLSI System Desig n25
Answer is 32hffff_ffff_ffff_ffff
out = { 4{1b1}, 4{2b01}};
Answer is 121111_0101_0101
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Conditional Operator
Condition Operator ( ?: ) ternary operator
condtion ? True_statement : false_statement
equivalent to if else
Conditional operators can be nested.
ECE301 VLSI System Desig n26
Example
assign out = sel ? a : b ; //2-to1 multiplexer
assign out = en ? a : 1bz ; //Tristate buffer
assign out = sel1 ? A : sel2 ? B : C ; //3-to-1 mux
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Quiz
Write a verilog code for 4-bit adder/subtractor blockshown below :
a_sb = 0 then add ; a_sb = 1 then sub
a b
ECE301 VLSI System Desig n27
add_sub a_sb
out
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Answer
//4-bit adder and subtractormodule add_sub ( out, a, b, a_sb ) ;
input a_sb ;
input [3:0] a, b ;
ECE301 VLSI System Desig n28
wire [3:0] b_int = b ^ {4{a_sb}} ;
wire [3:0] out = a + b_int + a_sb ;
endmodule
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Operator Precedence
Operators Operator Symbols
Unary
Multiply, Divide, Modulus
+ - ! ~
* / %
Add, Subtract + -
Parentheses has highest priority. Without that the priority is as follows :-
HIGH
ECE301 VLSI System Desig n29
Shift
>
Relational
Equality
< >=
== != === !==
Reduction
Logical
& ~& ^ ^~ | ~|
&& ||
Conditional ?:LOW
Execution order left-to-right for same priority
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Examples
wire [15:0] out = 128 >> 1 + 2 *2 ;//Answer is 4wire[15:0] out = (128 >> 1) + 2*2// Answer is 68
wire[15:0] out = ((128 >> 1) + 2) * 2 ;// Answer 132
Parentheses also controls synthesis result
wire out = a + b + c + d ;
ECE301 VLSI System Desig n30
w re ou = a + + c + ;
+b
a
+c +
dout
+d
c
+b
a
+out
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Parameters
Declare runtime constant. parameter p1 = 8, real_constant = 2.309 ;
Parameters are local to a module.
Used to configure design values
def aram : override arameter value
ECE301 VLSI System Desig n31
Specify the complete hierarchy
New value within module instance using #.
Multiple parameter order same as declared in module
Not necessary to assign new values to all parameters
cannot skip over a parameter
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Example
module adder (cout, sum, a, b, cin);parameter width = 8 ;
output cout ;
output [width-1:0] sum ;
input cin ;
input [width-1:0] a,b ;
ECE301 VLSI System Desig n32
assign {cout, sum} = a + b + cin ;
endmodule
adder #(16) adder_16bit(.cout(cout), .sum(sum), .a(a), .b(b), .cin(cin)) ;module top ();
endmodule
defparam top.A1.width = 16 ;
adder A1(.cout(cout), .sum(sum), .a(a), .b(b), .cin(cin)) ;
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`define
Compiler directive Globally substitutes text
Example
`define WIDTH 20;
` -
ECE301 VLSI System Desig n33
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Assignment 4
Write the Verilog codes for the following usingcontinuous assignments and operators only :
4-to-1 mux
3-to-8 line decoder
bcd-to 7 segment decoder
ECE301 VLSI System Desig n34
expandable 4-bit magnitude comparator
binary to gray code encoder
gray code to binary decoder
4-bit full adder rotate by 2 bit or 4 bit position
signed number division : division by 2 or 4
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Structured Procedure
Provide means to specify concurrency Real hardware operates concurrently
Differentiates HDL from other programming language
Programming Languages are sequential
always and initial
ECE301 VLSI System Desig n35
initial cannot be synthesized
covered in the next section
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always block
always block run concurrently. Can have one or multiple procedural assignment
statements.
Multiple statements must be enclosed within begin end
Procedural assignment statement run sequentially
ECE301 VLSI System Desig n36
sensitivity list decides when always block is entered
Syntax :always @(sensitivity_list)
begin
multiple/single procedural assignment statement
end
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Procedural assignments
Blocking LHS = RHS ;
Non-Blocking
LHS
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Blocking assignments
LHS = RHS ; Evaluate (RHS), assign (value to LHS), proceed
Equivalent to variable assignment in VHDL :=
Execution order as specified in block statement
BLOCKS only in that concurrent block
ECE301 VLSI System Desig n38
Does not BLOCK in other concurrent block
SHOULD be used in models and testbench
Simulation efficient
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Non-blocking assignments
LHS
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Sensitivity list
Specifies event when always block is entered. Event (@) is change in the value of reg or net.
posedge specifies the rising edge. 0 to x, x to 1, 0 to 1
negedge specifies the falling edge.
ECE301 VLSI System Desig n40
1 to x, 1 to 0, x to 0
Event OR multiple event trigger. Must be of same type.
Examples always @ (en or in) //used for latch
always @ (a or b or c) // Used to specify combo logic
always @(posedge clk or posedge rst) //Flip Flops
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Combo Example
//2-to-muxmodule (y, a, b, sel)
output y ;
input a, b,sel ;
wire a,b,sel ;
ECE301 VLSI System Desig n41
reg z ;
always @(a or b or sel)
z = (a & (~sel)) | (b & sel) ;
endmodule
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Combo Example
//implementation of a.b + c using procedural assignmentmodule (z, a, b,c)
output z ;
input a, b,c ;
wire a,b,c ;
ECE301 VLSI System Desig n42
reg z ;
always @(a or b or c)
z = (a & b) | c ;
endmodule
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Incomplete Sensitivity List
Not all RHS in sensitivity list.
Results in simulation v/s synthesis mis-matches.
always @( a or b )
out = a & b & c ;Mismatch
ECE301 VLSI System Desig n43
a
b
c
out
&out
a
b
c
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Example
What is the infered hardware withalways @(posedge clk or posedge rst)
begin
if (rst)
shift_reg = 4b0 ;
else
Blocking ?
Non-Blocking ?
ECE301 VLSI System Desig n44
shift_reg[0] = serial_in ;shift_reg[1] = shift_reg[0];shift_reg[2] = shift_reg[1];shift_reg[3] = shift_reg[2];
end
end
_ = _shift_reg[1]
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Quiz
Write a verilog code for 4-bit shift register usingprocedural block and blocking statements only
always @(posedge clk or posedge rst)
begin
if (rst)
shift_reg = 4b0 ;
ECE301 VLSI System Desig n45
else
begin
shift_reg[3] = shift_reg[2] ;
shift_reg[2] = shift_reg[1] ;
shift_reg[1] = shift_reg[0] ;shift_reg[0] = serial_data ;
end
end
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Another Example
A = 3 ;B = 4 ;
A
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Conditional Statements
if () true_statement(s) if()
true_statement(s)
else
false_statement(s)
Group multiple statements
ECE301 VLSI System Desig n47
true_statement(s)
else if()
true_statement(s)else
false_statement(s)
using begin and end
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Case Statements
Multiway Branching Syntax : case (expression)
alternative_1 : statement(s)_1;
alternative_1 : statement(s)_1;
ECE301 VLSI System Desig n48
default : default_statement(s);
endcase
Default statement(s) is executed when none of thebranch condition are met.
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Example
//2-to1 muxmodule mux (y, sel, a, b);
input sel, a, b ;
output y ;
reg y ;
always @(sel or a or b)
//2-to1 muxmodule mux (y, sel, a, b);
input sel, a, b ;
output y ;
reg y;
always @(sel or a or b)
ECE301 VLSI System Desig n49
begin
if(sel)
y
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Advanced Case Statements
casez syntax is similar to casez values in alternatives and case expression are
treated as Dont care (?)
casex syntax is similar to case
z as well as x values in alternatives and case
ECE301 VLSI System Desig n50
expression are treated as Dont care (?)
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Example//Example of 4-line priority encoder
module priority_encoder4 (y, in) ;
input [3:0] in ;
output [1:0] y ;
reg [1:0] y ;
always @(in)
begin
ECE301 VLSI System Desig n51
casex (in) //x represents dont care
4b1xxx : y = 2d0 ;
4b01xx : y = 2d1 ;
4b001x : y = 2d2 ;
4b0001 : y = 2d3 ;endcase
end
endmodule
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Rules for Combo logic
Rules to infer combinational logic using proceduralstatements are
All net and reg on the RHS must be specified in the
sensitivity list
sensitiviy list must not have posedge or negedge
ECE301 VLSI System Desig n52
reg mus e ass gne n every con ro pa .
OR LHS reg must be assigned a default value at the
start.
Thin line separates combo logic and latch inference
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QUIZ
What is the inferred hardware ?always @(a or b or en )
begin
if(en)
y1 = a ;
ECE301 VLSI System Desig n53
e se
y2 = b ;
end
Changes to infer y1 = en & a ;
y2 = ~en & b ;
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Assignment 5
Write the Verilog codes for the following usingstructured procedure and operators only :
4-to-1 mux : 74153
3-to-8 line decoder :74138
BCD-to-7 segment decoder
ECE301 VLSI System Desig n54
expandable 4-bit magnitude comparator : SN7485
bcd-to-decimal decoder : SN7442
excess 3 to decimal decoder : SN7443
4-bit full adder rotate by 2 bit or 4 bit position
signed number division : division by 2 or 4
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Decoder Solutionmodule decoder (out, in);
parameter in_width = 4 ;
parameter out_width = 16 ;
output [out_width-1:0] out ;
input [in_width-1:0] in ;
ECE301 VLSI System Desig n55
begin
out = 0 ;
out(in) = 1b1 ;
end
endmodule
decoder #(4,16) decode4_16 (.out(out), .in(in) ) ;
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Basic Latch
D-Latch with active highenable
module latch (q, d, enb ) ;
input d, enb ;
output q ;
D-Latch with active lowenable
module latch (q, d, enb ) ;
input d, enb ;
output q ;
ECE301 VLSI System Desig n56
reg q ;
always @( enb or d )
begin
if(enb)
q = d ;
end
endmodule
reg q ;
always @( enb or d )
begin
if(!enb)
q = d ;
end
endmodule
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D Latch
D-Latch with active high enable and resetmodule latch_r (q, d, enb, rst ) ;input d, enb, rst ;
output q ;
reg q ;
alwa s @ rst or enb or d
ECE301 VLSI System Desig n57
begin
if(rst)
q = 1b0 ;
else if(enb)q = d ;
end
endmodule
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D Flip-Flop
Rising edge D-Flip Flopmodule d_ff ( q, d, clk ) ;
input d, clk ;
output q ;
re ;
Falling edge D-Flip Flopmodule d_ff ( q, d, clk ) ;
input d, clk ;
output q ;
reg q ;
ECE301 VLSI System Desig n58
always @( posedge clk )
begin
q = d ;
endendmodule
always @( negedge clk )
begin
q = d ;
endendmodule
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D FF with reset
Rising edge D Flip-Flop with asynchronous resetmodule dff_ar (q, d, clk, rst ) ;input d, clk, rst ;
output q ;
reg q ;
alwa s @ osed e clk or osed e rst
ECE301 VLSI System Desig n59
begin
if(rst)
q = 1b0 ;
elseq = d ;
end
endmodule
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D FF . contd Rising edge D Flip-Flop with asynchronous reset and
clock enable
module dff_en ( q, d, enb, clk, rst ) ;
input d, clk, enb, rst ;
output q ;
reg q ;
ECE301 VLSI System Desig n61
begin
if(rst)
q
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Power of 2 Countermodule
counter_16 ( q, clk, rst ) ;input clk, rst ;
output [3:0] q ;
reg [3:0] q ;
always @( posedge clk or posedge rst )
ECE301 VLSI System Desig n62
eg n
if(rst)
q
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Non-Power of 2 Countermodule counter_12 ( q, clk, rst ) ;
input clk, rst ;
output [3:0] q ;
reg [3:0] q ;
wire [3:0] q_next = (q == 4d11) ? 4b0 : (q + 1) ;
alwa s @ osed e clk or osed e rst
ECE301 VLSI System Desig n63
begin
if(rst)
q
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Assignment 6
Write the Verilog codes for the following 4-bit ripple counter
Modulo 10 synchronous counter
8-bit programmable up/down counter
4-bit up/down counter with load and enable input
ECE301 VLSI System Desig n64
Modulo 5 ring (one-hot) counter
Modulo 10 Johnson (switched tail)counter
Modulo 15 Linear Feedback Shift Register (LFSR)
shift register with right shift, left shift and load inputs
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Finite State Machines
Moore FSM output depends on current state only
Mealy FSM
output depends on current state and inputs
ECE301 VLSI System Desig n65
Next State Decode O/p Decode
clkInput
Output
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FSM Details
State Encoding
Binary Gray One-hot Johnson
0 000 000 0000_0001 00_00
1 001 001 0000_0010 00_01
2 010 011 0000_0100 00_11
ECE301 VLSI System Desig n66
_ _
4 100 110 0001_0000 11_11
5 101 111 0010_0000 11_10
6 110 101 0100_0000 11_00
7 111 100 1000_0000 10_00
log2(S) log2(S) S S/2
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FSM Issues
Unused state
Lock-up state
use default state assignment
specify fail-safe transitions
ECE301 VLSI System Desig n67
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FSM Styles
Two unclocked block and one clocked block one combo always to assign next state one registered always to update state register
another unclocked always to assign output
Two clocked block and one unclocked block
ECE301 VLSI System Desig n68
one registered always to update state register
another registered always to assign output
One unclocked block and one clocked block
one combo always to assign output and next state
one registered always to update state register
One clocked block
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Example Moore FSM
S0
0
S1
0
enb
enb
ECE301 VLSI System Desig n69
S3
0
S2
1
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FSM Examples
Two unclocked block and one clocked block moore1.v
Two clocked block and one unclocked block moore2.v
One unclocked block and one clocked block
ECE301 VLSI System Desig n70
moore .v
One clocked block moore4.v
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Output Encoded FSM
IDLE
0
READ
rd=1
go=1
=
ECE301 VLSI System Desig n71
DONE
ds=1
DLY
rd=1
ws=0
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Design Procedure
Table with states+1 rows and outputs+1 columns Table of 5 rows and 3 columns
First Column rows write down states
From second column record FSM outputs
ECE301 VLSI System Desig n72
No duplicate patters. State encoding is done.
Else add additional bits to distinguish states
one additional bit if two patterns match
two additional bit if three or four patterns match
three additional bit if five to eight patterns match
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State Table
State ds rd
IDLE 0 0
READ 0 1
DLY 0 1
State ds rd X0
IDLE 0 0 0
ECE301 VLSI System Desig n73
DONE 1 0DLY 0 1 1
DONE 1 0 0
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Example Mealy FSM
S0 S1
10/1
00/0
0x/0
00/0x1/0
ECE301 VLSI System Desig n74
S2
S3 1x/1
01/110/1
11/1
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FSM Examples
Two unclocked block and one clocked block mealy1.v
ECE301 VLSI System Desig n75
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Subroutines
Re-use commonly used codes Avoid repetition of codes
functions and tasks.
Function can infer combinatorial logic
Function alwa s return sin le value.
ECE301 VLSI System Desig n76
Tasks are supported by synthesis tool
if no timing constructs are used
commonly used in models and testbenches
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Functions
Avoid repetition of code lines Function must have one input.
Can have multiple inputs
Function always return single value.
Function execute in zero simulation time
ECE301 VLSI System Desig n77
cannot have any delay, event or timing control
Function can call another function.
Function cannot call task
functions are used for conversion and calculations
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functions examplemodule gray_counter (out, clk, rst) ;
output [3:0] out ;
input clk, rst ;
reg [3:0] out ;
function bin2gray ;
ECE301 VLSI System Desig n78
npu : nary ;
begin
bin2gray[3] = binary[3];
bin2gray[2] = binary[3] ^ binary[2] ;
bin2gray[1] = binary[2] ^ binary[1] ;bin2gray[0] = binary[1] ^ binary[0] ;
end
endfunction
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functions example contdreg [3:0] cnt ;
always @( posedge rst or posedge clk )
begin
if ( rst )
begin
cnt = 4b0 ;
out = 4b0 ;
ECE301 VLSI System Desig n79
end
else
begin
cnt = cnt + 1 ;
out = bin2gray(cnt) ;end
end
endmodule
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task
task can have zero or more arguments arguments can be of type input, output or inout ;
task pass multiple value through output and inout.
task can contain delay, event or timing control
may execute in non-zero simulation time
ECE301 VLSI System Desig n80
task can call another task or function.
Mostly used in testbenches
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task examplemodule operation ;
parameter delay = 10 ;
reg [15:0] A, B;
reg [15:0] AB_AND, AB_OR ;
always @ ( A or B )
bitwise_oper (AB_AND, AB_OR, A, B );
task bitwise_oper ;
ECE301 VLSI System Desig n81
output [15:0] ab_and, ab_or ;
input [15:0] a, b ;
begin
# delay ab_and = a & b ; ab_or = a | b ;
end
endtask
endmodule
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For Loop
Perform similar operation for a fixed time Syntax: for (start;stop;incr)module bin2gray (out, in) ;
input [15:0] in ;
output [15:0] out ;
reg [15:0] out ;
ECE301 VLSI System Desig n82
integer i ;
always @(in)
begin
out[15] = in[15] ;
for (i = 14; i > 0; i = i - 1)out [i] = in[i] ^ in [i+1] ;
end
endmodule
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While Loop Perform similar operation until condition is TRUE
Syntax: while (condition)
module bin2gray (out, in) ;
input [15:0] in ;
output [15:0] out ;
reg [15:0] out ;
ECE301 VLSI System Desig n83
always @(in)
begin
out[15] = in[15]
count = 14;
while (count > 0)out [i] = in[i] ^ in [i+1]
count = count -1 ;
end
endmodule
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Assignment 7
Write the Verilog codes for the following Problem 6-3 of Fletcher : Page 430
Problem 6-10 of Fletcher : Page 433
Problem 6-35 of Fletcher : Page 436
ECE301 VLSI System Desig n84
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Overview
Goal : Develop RTL code that is simple and regular Simple constructs
Simple clocking schemes
Consistent coding styles & naming conventions
ECE301 VLSI System Desig n86
Regular partitioning scheme
Readable RTL
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General Naming Conventions Use consistent and standard naming convention
sensible and meaningful names
Use short descriptive names for parameters
Use consistent ordering for bits of buses.
Suggested [MSB:LSB]
ECE301 VLSI System Desig n87
Do not use HDL reserved words
Use same name throughout hierarchy for Global nets
One module per file
keep file and module name the same
Comment code
comments preferably on separate lines
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Signal Naming Conventions
Use naming conventions to indicate type of signal input, output register output, active low etc
Examples
CLK_* Clock signal
ECE301 VLSI System Desig n88
_ ct ve ow s gna
*_R Registered signal
*_A Asynchronous signal
*_NXT Date before being registered *_Z Tristate-signal
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Standard File Header
////////////////////////////////////////////////////////////////////////////////////////////// File : design.v
// Author: Anand Venkitachalam
// $Id$
// ABSTRACT: Description of the design object
ECE301 VLSI System Desig n89
, ,
// MODIFICATION HISTORY:
// $log$
// Anand 11-Sept-2002 original
// Paresh 12-Oct-2002// (C) Copyright 2002 MYCOMPANY Inc. All rights reserved
//////////////////////////////////////////////////////////////////////////////////////////////
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Major Constructs Header
////////////////////////////////////////////////////////////////////////////////////////////// FUNCTION: double_trouble
// Author: Anand Venkitachalam
// ABSTRACT: to double throughput of filter
// KEYWORDS: dsp, telecom, graphics
ECE301 VLSI System Desig n90
// Anand 11-Sept-2002 original
// Paresh 12-Oct-2002 revised as .
// This function performs the interpolation of data.
////////////////////////////////////////////////////////////////////////////////////////////// Use for each function and task
Use for each major section of code
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Basic RTL Format
Restrict Line length avoid line wrap-back
line length less than 72 characters
Use indentation
dont use tab for indentation
my_adder U1 (.A(a_in),
.B(b_in),
ECE301 VLSI System Desig n91
PORT declaration
follow a order. Say output, input, inout
Declare one port per line
while declaring and instantiating
Use Named instantiation
.SUM(result) );
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Use Labels
Labels improve readability & debugging Else simulator generates arbitrary labels
Label always@ and function constructs
ECE301 VLSI System Desig n92
:
always @(posedge CLK)
begin : MY_LABEL
.
.end
:
MY_LABEL : process (CLK)
begin :
.
.end process MY_LABEL ;
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More Guidelines
Use begin end even for single statements
Parameterize modules using `define
Avoid multiple clocks, gated clocks and async
highlight them if you cannot avoid
ECE301 VLSI System Desig n93
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RTL Coding guidelines
Avoid latches watchout for unwanted LATCH inference
Use non-blocking assignment for sequential logic
Use blocking assignment for combo logic
ECE301 VLSI System Desig n94
(fullcase/parallel case)
FSM style : 2 or 3 always
Register all module outputs
Avoid tool specific commands. paragams
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Coding for Portability : VHDL
Use only IEEE Standard types
Avoid creating too many subtypes
Avoid using types std_ulogic and
std_ulogic_vector
95
Avoid using types bit or bit_vector
Many simulator dont provide built in arithmetic
functions of these types
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